141 	ql_write32(qdev, SEM, sem_bits | sem_mask);  in ql_sem_trylock()
158 	ql_write32(qdev, SEM, sem_mask);  in ql_sem_unlock()
245 	ql_write32(qdev, ICB_L, (u32) map);  in ql_write_cfg()
246 	ql_write32(qdev, ICB_H, (u32) (map >> 32));  in ql_write_cfg()
250 	ql_write32(qdev, CFG, (mask | value));  in ql_write_cfg()
278 			ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */  in ql_get_mac_addr_reg()
292 			ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */  in ql_get_mac_addr_reg()
307 				ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */  in ql_get_mac_addr_reg()
351 			ql_write32(qdev, MAC_ADDR_IDX, (offset++) |  in ql_set_mac_addr_reg()
354 			ql_write32(qdev, MAC_ADDR_DATA, lower);  in ql_set_mac_addr_reg()
360 			ql_write32(qdev, MAC_ADDR_IDX, (offset++) |  in ql_set_mac_addr_reg()
364 			ql_write32(qdev, MAC_ADDR_DATA, upper);  in ql_set_mac_addr_reg()
384 			ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */  in ql_set_mac_addr_reg()
387 			ql_write32(qdev, MAC_ADDR_DATA, lower);  in ql_set_mac_addr_reg()
393 			ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */  in ql_set_mac_addr_reg()
396 			ql_write32(qdev, MAC_ADDR_DATA, upper);  in ql_set_mac_addr_reg()
402 			ql_write32(qdev, MAC_ADDR_IDX, (offset) |	/* offset */  in ql_set_mac_addr_reg()
416 			ql_write32(qdev, MAC_ADDR_DATA, cam_output);  in ql_set_mac_addr_reg()
432 			ql_write32(qdev, MAC_ADDR_IDX, offset |	/* offset */  in ql_set_mac_addr_reg()
505 	ql_write32(qdev, RT_IDX,  in ql_get_routing_reg()
611 		ql_write32(qdev, RT_IDX, value);  in ql_set_routing_reg()
612 		ql_write32(qdev, RT_DATA, enable ? mask : 0);  in ql_set_routing_reg()
620 	ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);  in ql_enable_interrupts()
625 	ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));  in ql_disable_interrupts()
644 		ql_write32(qdev, INTR_EN,  in ql_enable_completion_interrupt()
652 		ql_write32(qdev, INTR_EN,  in ql_enable_completion_interrupt()
674 		ql_write32(qdev, INTR_EN,  in ql_disable_completion_interrupt()
730 	ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);  in ql_read_flash_word()
873 	ql_write32(qdev, XGMAC_DATA, data);  in ql_write_xgmac_reg()
875 	ql_write32(qdev, XGMAC_ADDR, reg);  in ql_write_xgmac_reg()
892 	ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);  in ql_read_xgmac_reg()
1019 	ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));  in ql_8012_port_initialize()
2349 		ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |  in qlge_vlan_mode()
2352 		ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);  in qlge_vlan_mode()
2548 		ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));  in qlge_isr()
3771 	ql_write32(qdev, SYS, mask | value);  in ql_adapter_initialize()
3780 	ql_write32(qdev, NIC_RCV_CFG, (mask | value));  in ql_adapter_initialize()
3783 	ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);  in ql_adapter_initialize()
3793 	ql_write32(qdev, FSC, mask | value);  in ql_adapter_initialize()
3795 	ql_write32(qdev, SPLT_HDR, SPLT_LEN);  in ql_adapter_initialize()
3802 	ql_write32(qdev, RST_FO, RST_FO_RR_MASK | RST_FO_RR_RCV_FUNC_CQ);  in ql_adapter_initialize()
3812 	ql_write32(qdev, MGMT_RCV_CFG, mask);  in ql_adapter_initialize()
3813 	ql_write32(qdev, MGMT_RCV_CFG, mask | value);  in ql_adapter_initialize()
3897 	ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);  in ql_adapter_reset()