102 	qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);  in qed_int_assertion()
114 		qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,  in qed_int_assertion()
158 	qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);  in qed_int_deassertion()
370 	qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,  in qed_int_sb_attn_setup()
372 	qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,  in qed_int_sb_attn_setup()
483 		qed_wr(p_hwfn, p_ptt, val, lower_32_bits(sb_phys));  in qed_int_cau_conf_sb()
484 		qed_wr(p_hwfn, p_ptt, val + sizeof(u32),  in qed_int_cau_conf_sb()
488 		qed_wr(p_hwfn, p_ptt, val, sb_entry.data);  in qed_int_cau_conf_sb()
489 		qed_wr(p_hwfn, p_ptt, val + sizeof(u32), sb_entry.params);  in qed_int_cau_conf_sb()
547 		qed_wr(p_hwfn, p_ptt,  in qed_int_cau_conf_pi()
783 	qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);  in qed_int_igu_enable_int()
793 		qed_wr(p_hwfn, p_ptt,  in qed_int_igu_enable()
797 	qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);  in qed_int_igu_enable()
798 	qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);  in qed_int_igu_enable()
804 	qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);  in qed_int_igu_enable()
825 	qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);  in qed_int_igu_disable_int()
854 	qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);  in qed_int_igu_cleanup_sb()
858 	qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);  in qed_int_igu_cleanup_sb()
902 		qed_wr(p_hwfn, p_ptt,  in qed_int_igu_init_pure_rt_single()
919 	qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);  in qed_int_igu_init_pure_rt()