42 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \  argument
43 	ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
62 static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn,  in qed_attn_update_idx()  argument
90 static int qed_int_assertion(struct qed_hwfn *p_hwfn,  in qed_int_assertion()  argument
93 	struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;  in qed_int_assertion()
97 	igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,  in qed_int_assertion()
99 	DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",  in qed_int_assertion()
102 	qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);  in qed_int_assertion()
104 	DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,  in qed_int_assertion()
112 		qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);  in qed_int_assertion()
114 		qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,  in qed_int_assertion()
118 	DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +  in qed_int_assertion()
124 	DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n",  in qed_int_assertion()
138 static int qed_int_deassertion(struct qed_hwfn  *p_hwfn,  in qed_int_deassertion()  argument
141 	struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;  in qed_int_deassertion()
145 		DP_ERR(p_hwfn, "Unexpected - non-link deassertion\n");  in qed_int_deassertion()
148 	DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +  in qed_int_deassertion()
155 	aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,  in qed_int_deassertion()
158 	qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);  in qed_int_deassertion()
166 static int qed_int_attentions(struct qed_hwfn *p_hwfn)  in qed_int_attentions()  argument
168 	struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;  in qed_int_attentions()
196 		DP_INFO(p_hwfn,  in qed_int_attentions()
201 		DP_INFO(p_hwfn,  in qed_int_attentions()
204 		DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,  in qed_int_attentions()
209 		rc = qed_int_assertion(p_hwfn, asserted_bits);  in qed_int_attentions()
215 		rc = qed_int_deassertion(p_hwfn, deasserted_bits);  in qed_int_attentions()
223 static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn,  in qed_sb_ack_attn()  argument
247 	struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie;  in qed_int_sp_dpc()  local
254 	if (!p_hwfn->p_sp_sb) {  in qed_int_sp_dpc()
255 		DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n");  in qed_int_sp_dpc()
259 	sb_info = &p_hwfn->p_sp_sb->sb_info;  in qed_int_sp_dpc()
260 	arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);  in qed_int_sp_dpc()
262 		DP_ERR(p_hwfn->cdev,  in qed_int_sp_dpc()
267 	if (!p_hwfn->p_sb_attn) {  in qed_int_sp_dpc()
268 		DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn");  in qed_int_sp_dpc()
271 	sb_attn = p_hwfn->p_sb_attn;  in qed_int_sp_dpc()
273 	DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n",  in qed_int_sp_dpc()
274 		   p_hwfn, p_hwfn->my_id);  in qed_int_sp_dpc()
284 			p_hwfn->cdev,  in qed_int_sp_dpc()
290 		DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,  in qed_int_sp_dpc()
297 			p_hwfn->cdev,  in qed_int_sp_dpc()
302 		rc |= qed_attn_update_idx(p_hwfn, sb_attn);  in qed_int_sp_dpc()
303 		DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,  in qed_int_sp_dpc()
315 	if (!p_hwfn->p_dpc_ptt) {  in qed_int_sp_dpc()
316 		DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n");  in qed_int_sp_dpc()
322 		qed_int_attentions(p_hwfn);  in qed_int_sp_dpc()
329 			pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];  in qed_int_sp_dpc()
331 				pi_info->comp_cb(p_hwfn, pi_info->cookie);  in qed_int_sp_dpc()
339 		qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);  in qed_int_sp_dpc()
344 static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn)  in qed_int_sb_attn_free()  argument
346 	struct qed_dev *cdev   = p_hwfn->cdev;  in qed_int_sb_attn_free()
347 	struct qed_sb_attn_info *p_sb   = p_hwfn->p_sb_attn;  in qed_int_sb_attn_free()
352 					  SB_ATTN_ALIGNED_SIZE(p_hwfn),  in qed_int_sb_attn_free()
359 static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn,  in qed_int_sb_attn_setup()  argument
362 	struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;  in qed_int_sb_attn_setup()
370 	qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,  in qed_int_sb_attn_setup()
371 	       lower_32_bits(p_hwfn->p_sb_attn->sb_phys));  in qed_int_sb_attn_setup()
372 	qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,  in qed_int_sb_attn_setup()
373 	       upper_32_bits(p_hwfn->p_sb_attn->sb_phys));  in qed_int_sb_attn_setup()
376 static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn,  in qed_int_sb_attn_init()  argument
381 	struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;  in qed_int_sb_attn_init()
387 	sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +  in qed_int_sb_attn_init()
390 	qed_int_sb_attn_setup(p_hwfn, p_ptt);  in qed_int_sb_attn_init()
393 static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn,  in qed_int_sb_attn_alloc()  argument
396 	struct qed_dev *cdev = p_hwfn->cdev;  in qed_int_sb_attn_alloc()
410 				    SB_ATTN_ALIGNED_SIZE(p_hwfn),  in qed_int_sb_attn_alloc()
420 	p_hwfn->p_sb_attn = p_sb;  in qed_int_sb_attn_alloc()
421 	qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);  in qed_int_sb_attn_alloc()
430 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,  in qed_init_cau_sb_entry()  argument
454 	if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {  in qed_init_cau_sb_entry()
456 		if (!p_hwfn->cdev->rx_coalesce_usecs)  in qed_init_cau_sb_entry()
457 			p_hwfn->cdev->rx_coalesce_usecs =  in qed_init_cau_sb_entry()
459 		if (!p_hwfn->cdev->tx_coalesce_usecs)  in qed_init_cau_sb_entry()
460 			p_hwfn->cdev->tx_coalesce_usecs =  in qed_init_cau_sb_entry()
468 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,  in qed_int_cau_conf_sb()  argument
478 	qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,  in qed_int_cau_conf_sb()
481 	if (p_hwfn->hw_init_done) {  in qed_int_cau_conf_sb()
483 		qed_wr(p_hwfn, p_ptt, val, lower_32_bits(sb_phys));  in qed_int_cau_conf_sb()
484 		qed_wr(p_hwfn, p_ptt, val + sizeof(u32),  in qed_int_cau_conf_sb()
488 		qed_wr(p_hwfn, p_ptt, val, sb_entry.data);  in qed_int_cau_conf_sb()
489 		qed_wr(p_hwfn, p_ptt, val + sizeof(u32), sb_entry.params);  in qed_int_cau_conf_sb()
492 		STORE_RT_REG_AGG(p_hwfn,  in qed_int_cau_conf_sb()
497 		STORE_RT_REG_AGG(p_hwfn,  in qed_int_cau_conf_sb()
504 	if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {  in qed_int_cau_conf_sb()
505 		u8 timeset = p_hwfn->cdev->rx_coalesce_usecs >>  in qed_int_cau_conf_sb()
509 		qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,  in qed_int_cau_conf_sb()
513 		timeset = p_hwfn->cdev->tx_coalesce_usecs >>  in qed_int_cau_conf_sb()
517 			qed_int_cau_conf_pi(p_hwfn, p_ptt,  in qed_int_cau_conf_sb()
525 void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,  in qed_int_cau_conf_pi()  argument
546 	if (p_hwfn->hw_init_done) {  in qed_int_cau_conf_pi()
547 		qed_wr(p_hwfn, p_ptt,  in qed_int_cau_conf_pi()
551 		STORE_RT_REG(p_hwfn,  in qed_int_cau_conf_pi()
557 void qed_int_sb_setup(struct qed_hwfn *p_hwfn,  in qed_int_sb_setup()  argument
565 	qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,  in qed_int_sb_setup()
578 static u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn,  in qed_get_igu_sb_id()  argument
585 		igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;  in qed_get_igu_sb_id()
587 		igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb;  in qed_get_igu_sb_id()
589 	DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "SB [%s] index is 0x%04x\n",  in qed_get_igu_sb_id()
595 int qed_int_sb_init(struct qed_hwfn *p_hwfn,  in qed_int_sb_init()  argument
605 	sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);  in qed_int_sb_init()
608 		p_hwfn->sbs_info[sb_id] = sb_info;  in qed_int_sb_init()
609 		p_hwfn->num_sbs++;  in qed_int_sb_init()
612 	sb_info->cdev = p_hwfn->cdev;  in qed_int_sb_init()
617 	sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +  in qed_int_sb_init()
623 	qed_int_sb_setup(p_hwfn, p_ptt, sb_info);  in qed_int_sb_init()
628 int qed_int_sb_release(struct qed_hwfn *p_hwfn,  in qed_int_sb_release()  argument
633 		DP_ERR(p_hwfn, "Do Not free sp sb using this function");  in qed_int_sb_release()
641 	p_hwfn->sbs_info[sb_id] = NULL;  in qed_int_sb_release()
642 	p_hwfn->num_sbs--;  in qed_int_sb_release()
647 static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn)  in qed_int_sp_sb_free()  argument
649 	struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb;  in qed_int_sp_sb_free()
653 			dma_free_coherent(&p_hwfn->cdev->pdev->dev,  in qed_int_sp_sb_free()
654 					  SB_ALIGNED_SIZE(p_hwfn),  in qed_int_sp_sb_free()
661 static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn,  in qed_int_sp_sb_alloc()  argument
671 		DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_sb_info'\n");  in qed_int_sp_sb_alloc()
676 	p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,  in qed_int_sp_sb_alloc()
677 				    SB_ALIGNED_SIZE(p_hwfn),  in qed_int_sp_sb_alloc()
680 		DP_NOTICE(p_hwfn, "Failed to allocate status block\n");  in qed_int_sp_sb_alloc()
686 	p_hwfn->p_sp_sb = p_sb;  in qed_int_sp_sb_alloc()
687 	qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt,  in qed_int_sp_sb_alloc()
695 static void qed_int_sp_sb_setup(struct qed_hwfn *p_hwfn,  in qed_int_sp_sb_setup()  argument
698 	if (!p_hwfn)  in qed_int_sp_sb_setup()
701 	if (p_hwfn->p_sp_sb)  in qed_int_sp_sb_setup()
702 		qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);  in qed_int_sp_sb_setup()
704 		DP_NOTICE(p_hwfn->cdev,  in qed_int_sp_sb_setup()
707 	if (p_hwfn->p_sb_attn)  in qed_int_sp_sb_setup()
708 		qed_int_sb_attn_setup(p_hwfn, p_ptt);  in qed_int_sp_sb_setup()
710 		DP_NOTICE(p_hwfn->cdev,  in qed_int_sp_sb_setup()
714 int qed_int_register_cb(struct qed_hwfn *p_hwfn,  in qed_int_register_cb()  argument
720 	struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;  in qed_int_register_cb()
739 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi)  in qed_int_unregister_cb()  argument
741 	struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;  in qed_int_unregister_cb()
753 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn)  in qed_int_get_sp_sb_id()  argument
755 	return p_hwfn->p_sp_sb->sb_info.igu_sb_id;  in qed_int_get_sp_sb_id()
758 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,  in qed_int_igu_enable_int()  argument
764 	p_hwfn->cdev->int_mode = int_mode;  in qed_int_igu_enable_int()
765 	switch (p_hwfn->cdev->int_mode) {  in qed_int_igu_enable_int()
783 	qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);  in qed_int_igu_enable_int()
786 int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,  in qed_int_igu_enable()  argument
793 		qed_wr(p_hwfn, p_ptt,  in qed_int_igu_enable()
797 	qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);  in qed_int_igu_enable()
798 	qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);  in qed_int_igu_enable()
804 	qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);  in qed_int_igu_enable()
805 	if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {  in qed_int_igu_enable()
806 		rc = qed_slowpath_irq_req(p_hwfn);  in qed_int_igu_enable()
808 			DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n");  in qed_int_igu_enable()
811 		p_hwfn->b_int_requested = true;  in qed_int_igu_enable()
814 	qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);  in qed_int_igu_enable()
815 	p_hwfn->b_int_enabled = 1;  in qed_int_igu_enable()
820 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,  in qed_int_igu_disable_int()  argument
823 	p_hwfn->b_int_enabled = 0;  in qed_int_igu_disable_int()
825 	qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);  in qed_int_igu_disable_int()
829 void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,  in qed_int_igu_cleanup_sb()  argument
854 	qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);  in qed_int_igu_cleanup_sb()
858 	qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);  in qed_int_igu_cleanup_sb()
871 		val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);  in qed_int_igu_cleanup_sb()
880 		DP_NOTICE(p_hwfn,  in qed_int_igu_cleanup_sb()
885 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,  in qed_int_igu_init_pure_rt_single()  argument
895 		qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque);  in qed_int_igu_init_pure_rt_single()
898 	qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque);  in qed_int_igu_init_pure_rt_single()
902 		qed_wr(p_hwfn, p_ptt,  in qed_int_igu_init_pure_rt_single()
906 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,  in qed_int_igu_init_pure_rt()  argument
911 	u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb;  in qed_int_igu_init_pure_rt()
912 	u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt;  in qed_int_igu_init_pure_rt()
916 	val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);  in qed_int_igu_init_pure_rt()
919 	qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);  in qed_int_igu_init_pure_rt()
921 	DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,  in qed_int_igu_init_pure_rt()
926 		qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,  in qed_int_igu_init_pure_rt()
927 						p_hwfn->hw_info.opaque_fid,  in qed_int_igu_init_pure_rt()
931 		sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;  in qed_int_igu_init_pure_rt()
932 		DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,  in qed_int_igu_init_pure_rt()
934 		qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,  in qed_int_igu_init_pure_rt()
935 						p_hwfn->hw_info.opaque_fid,  in qed_int_igu_init_pure_rt()
940 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,  in qed_int_igu_read_cam()  argument
949 	p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_ATOMIC);  in qed_int_igu_read_cam()
951 	if (!p_hwfn->hw_info.p_igu_info)  in qed_int_igu_read_cam()
954 	p_igu_info = p_hwfn->hw_info.p_igu_info;  in qed_int_igu_read_cam()
962 	for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);  in qed_int_igu_read_cam()
966 		val = qed_rd(p_hwfn, p_ptt,  in qed_int_igu_read_cam()
981 		DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,  in qed_int_igu_read_cam()
987 			if (blk->function_id == p_hwfn->rel_pf_id) {  in qed_int_igu_read_cam()
998 						DP_NOTICE(p_hwfn->cdev,  in qed_int_igu_read_cam()
1000 							  p_hwfn->rel_pf_id);  in qed_int_igu_read_cam()
1011 	DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,  in qed_int_igu_read_cam()
1020 		DP_NOTICE(p_hwfn,  in qed_int_igu_read_cam()
1036 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn)  in qed_int_igu_init_rt()  argument
1042 	STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);  in qed_int_igu_init_rt()
1045 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn)  in qed_int_igu_read_sisr_reg()  argument
1055 	intr_status_lo = REG_RD(p_hwfn,  in qed_int_igu_read_sisr_reg()
1058 	intr_status_hi = REG_RD(p_hwfn,  in qed_int_igu_read_sisr_reg()
1066 static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn)  in qed_int_sp_dpc_setup()  argument
1068 	tasklet_init(p_hwfn->sp_dpc,  in qed_int_sp_dpc_setup()
1069 		     qed_int_sp_dpc, (unsigned long)p_hwfn);  in qed_int_sp_dpc_setup()
1070 	p_hwfn->b_sp_dpc_enabled = true;  in qed_int_sp_dpc_setup()
1073 static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn)  in qed_int_sp_dpc_alloc()  argument
1075 	p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_ATOMIC);  in qed_int_sp_dpc_alloc()
1076 	if (!p_hwfn->sp_dpc)  in qed_int_sp_dpc_alloc()
1082 static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn)  in qed_int_sp_dpc_free()  argument
1084 	kfree(p_hwfn->sp_dpc);  in qed_int_sp_dpc_free()
1087 int qed_int_alloc(struct qed_hwfn *p_hwfn,  in qed_int_alloc()  argument
1092 	rc = qed_int_sp_dpc_alloc(p_hwfn);  in qed_int_alloc()
1094 		DP_ERR(p_hwfn->cdev, "Failed to allocate sp dpc mem\n");  in qed_int_alloc()
1097 	rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt);  in qed_int_alloc()
1099 		DP_ERR(p_hwfn->cdev, "Failed to allocate sp sb mem\n");  in qed_int_alloc()
1102 	rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt);  in qed_int_alloc()
1104 		DP_ERR(p_hwfn->cdev, "Failed to allocate sb attn mem\n");  in qed_int_alloc()
1110 void qed_int_free(struct qed_hwfn *p_hwfn)  in qed_int_free()  argument
1112 	qed_int_sp_sb_free(p_hwfn);  in qed_int_free()
1113 	qed_int_sb_attn_free(p_hwfn);  in qed_int_free()
1114 	qed_int_sp_dpc_free(p_hwfn);  in qed_int_free()
1117 void qed_int_setup(struct qed_hwfn *p_hwfn,  in qed_int_setup()  argument
1120 	qed_int_sp_sb_setup(p_hwfn, p_ptt);  in qed_int_setup()
1121 	qed_int_sp_dpc_setup(p_hwfn);  in qed_int_setup()
1124 int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,  in qed_int_get_num_sbs()  argument
1127 	struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info;  in qed_int_get_num_sbs()