47 	u64 d64;
52 		u64 reserved_62_63:2;
54 		u64 len:14;
56 		u64 tstamp:1;
58 		u64 code:7;
60 		u64 addr:40;
62 		u64 addr:40;
63 		u64 code:7;
64 		u64 tstamp:1;
65 		u64 len:14;
66 		u64 reserved_62_63:2;
120 	u64 mix;
121 	u64 agl;
122 	u64 agl_prt_ctl;
126 	u64 *tx_ring;
135 	u64 *rx_ring;
165 	mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA);  in octeon_mgmt_set_rx_irq()
167 	cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);  in octeon_mgmt_set_rx_irq()
177 	mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA);  in octeon_mgmt_set_tx_irq()
179 	cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);  in octeon_mgmt_set_tx_irq()
258 	mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);  in octeon_mgmt_clean_tx_buffers()
262 		mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);  in octeon_mgmt_clean_tx_buffers()
278 		mix_orcnt.u64 = 0;  in octeon_mgmt_clean_tx_buffers()
282 		cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64);  in octeon_mgmt_clean_tx_buffers()
293 			u64 ns;  in octeon_mgmt_clean_tx_buffers()
308 		mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);  in octeon_mgmt_clean_tx_buffers()
326 	u64 drop, bad;  in octeon_mgmt_update_rx_stats()
350 	s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0);  in octeon_mgmt_update_tx_stats()
351 	s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1);  in octeon_mgmt_update_tx_stats()
366 static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p,  in octeon_mgmt_dequeue_rx_buffer()
408 			u64 ns = *(u64 *)skb->data;  in octeon_mgmt_receive_one()
467 	mix_ircnt.u64 = 0;  in octeon_mgmt_receive_one()
469 	cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64);  in octeon_mgmt_receive_one()
479 	mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT);  in octeon_mgmt_receive_packets()
487 		mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT);  in octeon_mgmt_receive_packets()
520 	mix_ctl.u64 = 0;  in octeon_mgmt_reset_hw()
521 	cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);  in octeon_mgmt_reset_hw()
523 		mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);  in octeon_mgmt_reset_hw()
526 	cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);  in octeon_mgmt_reset_hw()
530 	mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST);  in octeon_mgmt_reset_hw()
531 	if (mix_bist.u64)  in octeon_mgmt_reset_hw()
533 			(unsigned long long)mix_bist.u64);  in octeon_mgmt_reset_hw()
535 	agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST);  in octeon_mgmt_reset_hw()
536 	if (agl_gmx_bist.u64)  in octeon_mgmt_reset_hw()
538 			 (unsigned long long)agl_gmx_bist.u64);  in octeon_mgmt_reset_hw()
542 	u64 cam[6];
543 	u64 cam_mask;
553 		cs->cam[i] |= (u64)addr[i] << (8 * (cs->cam_index));  in octeon_mgmt_cam_state_add()
605 	agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);  in octeon_mgmt_set_rx_filtering()
608 	cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64);  in octeon_mgmt_set_rx_filtering()
610 	adr_ctl.u64 = 0;  in octeon_mgmt_set_rx_filtering()
615 	cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64);  in octeon_mgmt_set_rx_filtering()
627 	cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64);  in octeon_mgmt_set_rx_filtering()
674 	mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR);  in octeon_mgmt_interrupt()
677 	cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64);  in octeon_mgmt_interrupt()
710 		ptp.u64 = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_CFG);  in octeon_mgmt_ioctl_hwtstamp()
716 			u64 clock_comp = (NSEC_PER_SEC << 32) /	octeon_get_io_clock_rate();  in octeon_mgmt_ioctl_hwtstamp()
723 			u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP);  in octeon_mgmt_ioctl_hwtstamp()
732 			cvmx_write_csr(CVMX_MIO_PTP_CLOCK_CFG, ptp.u64);  in octeon_mgmt_ioctl_hwtstamp()
751 		rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL);  in octeon_mgmt_ioctl_hwtstamp()
753 		cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);  in octeon_mgmt_ioctl_hwtstamp()
772 			rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL);  in octeon_mgmt_ioctl_hwtstamp()
774 			cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);  in octeon_mgmt_ioctl_hwtstamp()
807 	prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);  in octeon_mgmt_disable_link()
811 	cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);  in octeon_mgmt_disable_link()
816 			prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);  in octeon_mgmt_disable_link()
830 	prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);  in octeon_mgmt_enable_link()
834 	cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);  in octeon_mgmt_enable_link()
841 	prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);  in octeon_mgmt_update_link()
883 	cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);  in octeon_mgmt_update_link()
886 	prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);  in octeon_mgmt_update_link()
892 		prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);  in octeon_mgmt_update_link()
893 		agl_clk.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_CLK);  in octeon_mgmt_update_link()
902 		cvmx_write_csr(p->agl + AGL_GMX_TX_CLK, agl_clk.u64);  in octeon_mgmt_update_link()
1011 	mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);  in octeon_mgmt_open()
1016 		cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);  in octeon_mgmt_open()
1018 			mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);  in octeon_mgmt_open()
1023 		agl_gmx_inf_mode.u64 = 0;  in octeon_mgmt_open()
1025 		cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);  in octeon_mgmt_open()
1034 		drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);  in octeon_mgmt_open()
1044 		cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);  in octeon_mgmt_open()
1047 	oring1.u64 = 0;  in octeon_mgmt_open()
1050 	cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64);  in octeon_mgmt_open()
1052 	iring1.u64 = 0;  in octeon_mgmt_open()
1055 	cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64);  in octeon_mgmt_open()
1065 	mix_ctl.u64 = 0;  in octeon_mgmt_open()
1074 	cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);  in octeon_mgmt_open()
1088 		agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);  in octeon_mgmt_open()
1090 		cvmx_write_csr(p->agl_prt_ctl,	agl_prtx_ctl.u64);  in octeon_mgmt_open()
1099 		agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);  in octeon_mgmt_open()
1105 		cvmx_write_csr(p->agl_prt_ctl,	agl_prtx_ctl.u64);  in octeon_mgmt_open()
1114 		agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);  in octeon_mgmt_open()
1116 		cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);  in octeon_mgmt_open()
1119 		agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);  in octeon_mgmt_open()
1124 		cvmx_write_csr(p->agl_prt_ctl,	agl_prtx_ctl.u64);  in octeon_mgmt_open()
1162 	mix_irhwm.u64 = 0;  in octeon_mgmt_open()
1164 	cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64);  in octeon_mgmt_open()
1167 	mix_orhwm.u64 = 0;  in octeon_mgmt_open()
1169 	cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64);  in octeon_mgmt_open()
1172 	mix_intena.u64 = 0;  in octeon_mgmt_open()
1175 	cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);  in octeon_mgmt_open()
1179 	rxx_frm_ctl.u64 = 0;  in octeon_mgmt_open()
1204 	cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);  in octeon_mgmt_open()
1505 	p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size);  in octeon_mgmt_probe()
1506 	p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size);  in octeon_mgmt_probe()
1507 	p->agl_prt_ctl = (u64)devm_ioremap(&pdev->dev, p->agl_prt_ctl_phys,  in octeon_mgmt_probe()