3223 	u32 phyreg, txreg;  in nv_force_linkspeed()  local
3258 			txreg = NVREG_TX_DEFERRAL_RGMII_1000;  in nv_force_linkspeed()
3260 			txreg = NVREG_TX_DEFERRAL_RGMII_10_100;  in nv_force_linkspeed()
3262 		txreg = NVREG_TX_DEFERRAL_DEFAULT;  in nv_force_linkspeed()
3264 	writel(txreg, base + NvRegTxDeferral);  in nv_force_linkspeed()
3267 		txreg = NVREG_TX_WM_DESC1_DEFAULT;  in nv_force_linkspeed()
3271 			txreg = NVREG_TX_WM_DESC2_3_1000;  in nv_force_linkspeed()
3273 			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;  in nv_force_linkspeed()
3275 	writel(txreg, base + NvRegTxWatermark);  in nv_force_linkspeed()
3309 	u32 control_1000, status_1000, phyreg, pause_flags, txreg;  in nv_update_linkspeed()  local
3441 			txreg = NVREG_TX_DEFERRAL_RGMII_1000;  in nv_update_linkspeed()
3445 					txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;  in nv_update_linkspeed()
3447 					txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;  in nv_update_linkspeed()
3449 				txreg = NVREG_TX_DEFERRAL_RGMII_10_100;  in nv_update_linkspeed()
3454 			txreg = NVREG_TX_DEFERRAL_MII_STRETCH;  in nv_update_linkspeed()
3456 			txreg = NVREG_TX_DEFERRAL_DEFAULT;  in nv_update_linkspeed()
3458 	writel(txreg, base + NvRegTxDeferral);  in nv_update_linkspeed()
3461 		txreg = NVREG_TX_WM_DESC1_DEFAULT;  in nv_update_linkspeed()
3464 			txreg = NVREG_TX_WM_DESC2_3_1000;  in nv_update_linkspeed()
3466 			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;  in nv_update_linkspeed()
3468 	writel(txreg, base + NvRegTxWatermark);  in nv_update_linkspeed()
5609 	u32 powerstate, txreg;  in nv_probe()  local
5778 	txreg = readl(base + NvRegTransmitPoll);  in nv_probe()
5787 	} else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {  in nv_probe()
5811 		writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);  in nv_probe()