3223 	u32 phyreg, txreg;  in nv_force_linkspeed()  local
3233 		phyreg = readl(base + NvRegSlotTime);  in nv_force_linkspeed()
3234 		phyreg &= ~(0x3FF00);  in nv_force_linkspeed()
3236 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_force_linkspeed()
3238 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_force_linkspeed()
3240 			phyreg |= NVREG_SLOTTIME_1000_FULL;  in nv_force_linkspeed()
3241 		writel(phyreg, base + NvRegSlotTime);  in nv_force_linkspeed()
3244 	phyreg = readl(base + NvRegPhyInterface);  in nv_force_linkspeed()
3245 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);  in nv_force_linkspeed()
3247 		phyreg |= PHY_HALF;  in nv_force_linkspeed()
3249 		phyreg |= PHY_100;  in nv_force_linkspeed()
3252 		phyreg |= PHY_1000;  in nv_force_linkspeed()
3253 	writel(phyreg, base + NvRegPhyInterface);  in nv_force_linkspeed()
3255 	if (phyreg & PHY_RGMII) {  in nv_force_linkspeed()
3309 	u32 control_1000, status_1000, phyreg, pause_flags, txreg;  in nv_update_linkspeed()  local
3418 		phyreg = readl(base + NvRegSlotTime);  in nv_update_linkspeed()
3419 		phyreg &= ~(0x3FF00);  in nv_update_linkspeed()
3422 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_update_linkspeed()
3424 			phyreg |= NVREG_SLOTTIME_1000_FULL;  in nv_update_linkspeed()
3425 		writel(phyreg, base + NvRegSlotTime);  in nv_update_linkspeed()
3428 	phyreg = readl(base + NvRegPhyInterface);  in nv_update_linkspeed()
3429 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);  in nv_update_linkspeed()
3431 		phyreg |= PHY_HALF;  in nv_update_linkspeed()
3433 		phyreg |= PHY_100;  in nv_update_linkspeed()
3435 		phyreg |= PHY_1000;  in nv_update_linkspeed()
3436 	writel(phyreg, base + NvRegPhyInterface);  in nv_update_linkspeed()
3439 	if (phyreg & PHY_RGMII) {  in nv_update_linkspeed()