Lines Matching refs:phyaddr
765 int phyaddr; member
1183 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) in phy_reset()
1192 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_reset()
1217 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) in init_realtek_8211b()
1239 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); in init_realtek_8211c()
1241 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) in init_realtek_8211c()
1243 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1246 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); in init_realtek_8211c()
1249 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) in init_realtek_8211c()
1252 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1264 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201()
1267 if (mii_rw(dev, np->phyaddr, in init_realtek_8201()
1280 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1283 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1287 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1290 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1304 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); in init_cicada()
1307 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) in init_cicada()
1309 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in init_cicada()
1311 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) in init_cicada()
1314 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); in init_cicada()
1316 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) in init_cicada()
1326 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1329 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1332 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1334 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1336 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1340 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1342 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1345 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1348 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1352 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1354 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1356 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1358 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1361 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1364 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1366 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1368 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1372 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1374 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1377 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1393 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in phy_init()
1395 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { in phy_init()
1426 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in phy_init()
1430 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { in phy_init()
1440 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in phy_init()
1443 mii_control_1000 = mii_rw(dev, np->phyaddr, in phy_init()
1451 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { in phy_init()
1459 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1467 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { in phy_init()
1516 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); in phy_init()
1519 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1523 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) in phy_init()
3230 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_force_linkspeed()
3316 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_update_linkspeed()
3329 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3330 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3365 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_update_linkspeed()
3366 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); in nv_update_linkspeed()
3370 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_update_linkspeed()
3371 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); in nv_update_linkspeed()
3438 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ in nv_update_linkspeed()
4295 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_get_settings()
4305 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_get_settings()
4317 ecmd->phy_address = np->phyaddr; in nv_get_settings()
4334 if (ecmd->phy_address != np->phyaddr) { in nv_set_settings()
4392 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_settings()
4406 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_settings()
4409 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_settings()
4413 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_settings()
4418 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_settings()
4429 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_settings()
4436 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_settings()
4455 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_settings()
4459 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_settings()
4461 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_settings()
4464 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_settings()
4477 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_settings()
4538 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_nway_reset()
4548 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_nway_reset()
4732 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_pauseparam()
4738 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_pauseparam()
4742 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_pauseparam()
4744 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_pauseparam()
4773 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_loopback()
4783 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol); in nv_set_loopback()
4927 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
4928 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5357 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_open()
5358 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); in nv_open()
5443 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, in nv_open()
5558 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_close()
5559 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); in nv_close()
5935 int phyaddr = i & 0x1F; in nv_probe() local
5938 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); in nv_probe()
5943 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); in nv_probe()
5951 np->phyaddr = phyaddr; in nv_probe()
5959 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; in nv_probe()
5973 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_probe()
6003 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr); in nv_probe()
6050 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); in nv_restore_phy()
6051 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); in nv_restore_phy()
6054 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); in nv_restore_phy()
6055 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); in nv_restore_phy()
6058 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_restore_phy()
6060 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); in nv_restore_phy()