1261 	u32 phy_reserved;  in init_realtek_8201()  local
1264 		phy_reserved = mii_rw(dev, np->phyaddr,  in init_realtek_8201()
1266 		phy_reserved |= PHY_REALTEK_INIT7;  in init_realtek_8201()
1268 			   PHY_REALTEK_INIT_REG6, phy_reserved))  in init_realtek_8201()
1277 	u32 phy_reserved;  in init_realtek_8201_cross()  local
1283 		phy_reserved = mii_rw(dev, np->phyaddr,  in init_realtek_8201_cross()
1285 		phy_reserved &= ~PHY_REALTEK_INIT_MSK1;  in init_realtek_8201_cross()
1286 		phy_reserved |= PHY_REALTEK_INIT3;  in init_realtek_8201_cross()
1288 			   PHY_REALTEK_INIT_REG2, phy_reserved))  in init_realtek_8201_cross()
1301 	u32 phy_reserved;  in init_cicada()  local
1304 		phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);  in init_cicada()
1305 		phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);  in init_cicada()
1306 		phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);  in init_cicada()
1307 		if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))  in init_cicada()
1309 		phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);  in init_cicada()
1310 		phy_reserved |= PHY_CICADA_INIT5;  in init_cicada()
1311 		if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))  in init_cicada()
1314 	phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);  in init_cicada()
1315 	phy_reserved |= PHY_CICADA_INIT6;  in init_cicada()
1316 	if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))  in init_cicada()
1324 	u32 phy_reserved;  in init_vitesse()  local
1332 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1334 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))  in init_vitesse()
1336 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1338 	phy_reserved &= ~PHY_VITESSE_INIT_MSK1;  in init_vitesse()
1339 	phy_reserved |= PHY_VITESSE_INIT3;  in init_vitesse()
1340 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))  in init_vitesse()
1348 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1350 	phy_reserved &= ~PHY_VITESSE_INIT_MSK1;  in init_vitesse()
1351 	phy_reserved |= PHY_VITESSE_INIT3;  in init_vitesse()
1352 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))  in init_vitesse()
1354 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1356 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))  in init_vitesse()
1364 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1366 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))  in init_vitesse()
1368 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1370 	phy_reserved &= ~PHY_VITESSE_INIT_MSK2;  in init_vitesse()
1371 	phy_reserved |= PHY_VITESSE_INIT8;  in init_vitesse()
1372 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))  in init_vitesse()
6045 	u16 phy_reserved, mii_control;  in nv_restore_phy()  local
6051 		phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);  in nv_restore_phy()
6052 		phy_reserved &= ~PHY_REALTEK_INIT_MSK1;  in nv_restore_phy()
6053 		phy_reserved |= PHY_REALTEK_INIT8;  in nv_restore_phy()
6054 		mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);  in nv_restore_phy()