40 	writeq(val64, &vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_set_zero_rx_frm_len()
172 	writeq(*data0, &vp_reg->rts_access_steer_data0);  in vxge_hw_vpath_fw_api()
173 	writeq(*data1, &vp_reg->rts_access_steer_data1);  in vxge_hw_vpath_fw_api()
529 		writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,  in __vxge_hw_legacy_swapper_set()
531 		writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,  in __vxge_hw_legacy_swapper_set()
533 		writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,  in __vxge_hw_legacy_swapper_set()
535 		writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,  in __vxge_hw_legacy_swapper_set()
540 		writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,  in __vxge_hw_legacy_swapper_set()
542 		writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,  in __vxge_hw_legacy_swapper_set()
547 		writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,  in __vxge_hw_legacy_swapper_set()
549 		writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,  in __vxge_hw_legacy_swapper_set()
1048 			writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask);  in vxge_hw_device_hw_info_get()
1972 	writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);  in vxge_hw_device_setpause_data()
3083 	writeq(val64, &vpath_reg->vpath_general_cfg1);  in __vxge_hw_vpath_swapper_set()
3109 		writeq(val64, &vpath_reg->kdfcctl_cfg0);  in __vxge_hw_kdfc_swapper_set()
3263 		writeq(value, (void __iomem *)hldev->legacy_reg + offset);  in vxge_hw_mgmt_reg_write()
3270 		writeq(value, (void __iomem *)hldev->toc_reg + offset);  in vxge_hw_mgmt_reg_write()
3277 		writeq(value, (void __iomem *)hldev->common_reg + offset);  in vxge_hw_mgmt_reg_write()
3289 		writeq(value, (void __iomem *)hldev->mrpcim_reg + offset);  in vxge_hw_mgmt_reg_write()
3305 		writeq(value, (void __iomem *)hldev->srpcim_reg[index] +  in vxge_hw_mgmt_reg_write()
3319 		writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] +  in vxge_hw_mgmt_reg_write()
3332 		writeq(value, (void __iomem *)hldev->vpath_reg[index] +  in vxge_hw_mgmt_reg_write()
3590 	writeq(val64, &vp_reg->pci_config_access_cfg1);  in __vxge_hw_vpath_pci_read()
3592 	writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ,  in __vxge_hw_vpath_pci_read()
4092 	writeq(val64, &vp_reg->prc_cfg1);  in __vxge_hw_vpath_prc_configure()
4096 	writeq(val64, &vpath->vp_reg->prc_cfg6);  in __vxge_hw_vpath_prc_configure()
4121 	writeq(val64, &vp_reg->prc_cfg7);  in __vxge_hw_vpath_prc_configure()
4123 	writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(  in __vxge_hw_vpath_prc_configure()
4139 	writeq(val64, &vp_reg->prc_cfg4);  in __vxge_hw_vpath_prc_configure()
4185 	writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);  in __vxge_hw_vpath_kdfc_configure()
4187 	writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,  in __vxge_hw_vpath_kdfc_configure()
4202 	writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);  in __vxge_hw_vpath_kdfc_configure()
4203 	writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);  in __vxge_hw_vpath_kdfc_configure()
4232 	writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(  in __vxge_hw_vpath_mac_configure()
4247 		writeq(val64, &vp_reg->xmac_rpa_vcfg);  in __vxge_hw_vpath_mac_configure()
4263 		writeq(val64, &vp_reg->rxmac_vcfg0);  in __vxge_hw_vpath_mac_configure()
4277 		writeq(val64, &vp_reg->rxmac_vcfg1);  in __vxge_hw_vpath_mac_configure()
4299 	writeq(0, &vp_reg->tim_dest_addr);  in __vxge_hw_vpath_tim_configure()
4300 	writeq(0, &vp_reg->tim_vpath_map);  in __vxge_hw_vpath_tim_configure()
4301 	writeq(0, &vp_reg->tim_bitmap);  in __vxge_hw_vpath_tim_configure()
4302 	writeq(0, &vp_reg->tim_remap);  in __vxge_hw_vpath_tim_configure()
4305 		writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(  in __vxge_hw_vpath_tim_configure()
4311 	writeq(val64, &vp_reg->tim_pci_cfg);  in __vxge_hw_vpath_tim_configure()
4358 		writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4387 		writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4416 		writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4465 		writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4494 		writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4523 		writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4528 	writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);  in __vxge_hw_vpath_tim_configure()
4529 	writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);  in __vxge_hw_vpath_tim_configure()
4530 	writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);  in __vxge_hw_vpath_tim_configure()
4531 	writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);  in __vxge_hw_vpath_tim_configure()
4532 	writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);  in __vxge_hw_vpath_tim_configure()
4533 	writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);  in __vxge_hw_vpath_tim_configure()
4538 	writeq(val64, &vp_reg->tim_wrkld_clc);  in __vxge_hw_vpath_tim_configure()
4601 	writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);  in __vxge_hw_vpath_initialize()
4732 	writeq(val64, &vpath->vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_mtu_set()
4870 	writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);  in vxge_hw_vpath_open()
4925 	writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),  in vxge_hw_vpath_rx_doorbell_init()
5087 	writeq(vpath->stats_block->dma_addr,  in vxge_hw_vpath_recover_from_reset()