34 vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)  in vxge_hw_vpath_set_zero_rx_frm_len()  argument
38 	val64 = readq(&vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_set_zero_rx_frm_len()
40 	writeq(val64, &vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_set_zero_rx_frm_len()
41 	val64 = readq(&vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_set_zero_rx_frm_len()
49 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in vxge_hw_vpath_wait_receive_idle()  local
55 	vp_reg = vpath->vp_reg;  in vxge_hw_vpath_wait_receive_idle()
57 	vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);  in vxge_hw_vpath_wait_receive_idle()
64 	val64 = readq(&vp_reg->prc_cfg6);  in vxge_hw_vpath_wait_receive_idle()
74 		rxd_count = readq(&vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_wait_receive_idle()
79 		val64 = readq(&vp_reg->frm_in_progress_cnt);  in vxge_hw_vpath_wait_receive_idle()
161 	struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;  in vxge_hw_vpath_fw_api()  local
172 	writeq(*data0, &vp_reg->rts_access_steer_data0);  in vxge_hw_vpath_fw_api()
173 	writeq(*data1, &vp_reg->rts_access_steer_data1);  in vxge_hw_vpath_fw_api()
183 					   &vp_reg->rts_access_steer_ctrl,  in vxge_hw_vpath_fw_api()
199 					&vp_reg->rts_access_steer_ctrl,  in vxge_hw_vpath_fw_api()
207 	val64 = readq(&vp_reg->rts_access_steer_ctrl);  in vxge_hw_vpath_fw_api()
209 		*data0 = readq(&vp_reg->rts_access_steer_data0);  in vxge_hw_vpath_fw_api()
210 		*data1 = readq(&vp_reg->rts_access_steer_data1);  in vxge_hw_vpath_fw_api()
741 		hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];  in __vxge_hw_device_host_info_get()
1055 		vpath.vp_reg = bar0 + val64;  in vxge_hw_device_hw_info_get()
1078 		vpath.vp_reg = bar0 + val64;  in vxge_hw_device_hw_info_get()
1418 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_stats_access()  local
1425 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_stats_access()
1432 				&vp_reg->xmac_stats_access_cmd,  in __vxge_hw_vpath_stats_access()
1436 		*stat = readq(&vp_reg->xmac_stats_access_data);  in __vxge_hw_vpath_stats_access()
1516 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_stats_get()  local
1522 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_stats_get()
1524 	val64 = readq(&vp_reg->vpath_debug_stats0);  in __vxge_hw_vpath_stats_get()
1528 	val64 = readq(&vp_reg->vpath_debug_stats1);  in __vxge_hw_vpath_stats_get()
1532 	val64 = readq(&vp_reg->vpath_debug_stats2);  in __vxge_hw_vpath_stats_get()
1536 	val64 = readq(&vp_reg->vpath_debug_stats3);  in __vxge_hw_vpath_stats_get()
1540 	val64 = readq(&vp_reg->vpath_debug_stats4);  in __vxge_hw_vpath_stats_get()
1544 	val64 = readq(&vp_reg->vpath_debug_stats5);  in __vxge_hw_vpath_stats_get()
1548 	val64 = readq(&vp_reg->vpath_debug_stats6);  in __vxge_hw_vpath_stats_get()
1552 	val64 = readq(&vp_reg->vpath_genstats_count01);  in __vxge_hw_vpath_stats_get()
1557 	val64 = readq(&vp_reg->vpath_genstats_count01);  in __vxge_hw_vpath_stats_get()
1562 	val64 = readq(&vp_reg->vpath_genstats_count23);  in __vxge_hw_vpath_stats_get()
1567 	val64 = readq(&vp_reg->vpath_genstats_count01);  in __vxge_hw_vpath_stats_get()
1572 	val64 = readq(&vp_reg->vpath_genstats_count4);  in __vxge_hw_vpath_stats_get()
1577 	val64 = readq(&vp_reg->vpath_genstats_count5);  in __vxge_hw_vpath_stats_get()
1608 	val64 = readq(&vp_reg->rx_multi_cast_stats);  in __vxge_hw_vpath_stats_get()
1612 	val64 = readq(&vp_reg->rx_frm_transferred);  in __vxge_hw_vpath_stats_get()
1616 	val64 = readq(&vp_reg->rxd_returned);  in __vxge_hw_vpath_stats_get()
1620 	val64 = readq(&vp_reg->dbg_stats_rx_mpa);  in __vxge_hw_vpath_stats_get()
1628 	val64 = readq(&vp_reg->dbg_stats_rx_fau);  in __vxge_hw_vpath_stats_get()
1636 	val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);  in __vxge_hw_vpath_stats_get()
2844 	ring->vp_reg = vp->vpath->vp_reg;  in __vxge_hw_ring_create()
3488 	fifo->vp_reg = vpath->vp_reg;  in __vxge_hw_fifo_create()
3583 	struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_pci_read()  local
3590 	writeq(val64, &vp_reg->pci_config_access_cfg1);  in __vxge_hw_vpath_pci_read()
3593 			&vp_reg->pci_config_access_cfg2);  in __vxge_hw_vpath_pci_read()
3597 			&vp_reg->pci_config_access_cfg2,  in __vxge_hw_vpath_pci_read()
3603 	val64 = readq(&vp_reg->pci_config_access_status);  in __vxge_hw_vpath_pci_read()
3957 	rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_check_leak()
3958 	rxd_spat = readq(&ring->vp_reg->prc_cfg6);  in vxge_hw_vpath_check_leak()
4081 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_prc_configure()  local
4084 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_prc_configure()
4090 	val64 = readq(&vp_reg->prc_cfg1);  in __vxge_hw_vpath_prc_configure()
4092 	writeq(val64, &vp_reg->prc_cfg1);  in __vxge_hw_vpath_prc_configure()
4094 	val64 = readq(&vpath->vp_reg->prc_cfg6);  in __vxge_hw_vpath_prc_configure()
4096 	writeq(val64, &vpath->vp_reg->prc_cfg6);  in __vxge_hw_vpath_prc_configure()
4098 	val64 = readq(&vp_reg->prc_cfg7);  in __vxge_hw_vpath_prc_configure()
4121 	writeq(val64, &vp_reg->prc_cfg7);  in __vxge_hw_vpath_prc_configure()
4125 					vpath->ringh) >> 3), &vp_reg->prc_cfg5);  in __vxge_hw_vpath_prc_configure()
4127 	val64 = readq(&vp_reg->prc_cfg4);  in __vxge_hw_vpath_prc_configure()
4139 	writeq(val64, &vp_reg->prc_cfg4);  in __vxge_hw_vpath_prc_configure()
4154 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_kdfc_configure()  local
4157 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_kdfc_configure()
4158 	status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);  in __vxge_hw_vpath_kdfc_configure()
4163 	val64 = readq(&vp_reg->kdfc_drbl_triplet_total);  in __vxge_hw_vpath_kdfc_configure()
4185 	writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);  in __vxge_hw_vpath_kdfc_configure()
4188 		&vp_reg->kdfc_fifo_trpl_ctrl);  in __vxge_hw_vpath_kdfc_configure()
4190 	val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);  in __vxge_hw_vpath_kdfc_configure()
4202 	writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);  in __vxge_hw_vpath_kdfc_configure()
4203 	writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);  in __vxge_hw_vpath_kdfc_configure()
4226 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_mac_configure()  local
4229 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_mac_configure()
4233 			vpath->vsport_number), &vp_reg->xmac_vsport_choice);  in __vxge_hw_vpath_mac_configure()
4237 		val64 = readq(&vp_reg->xmac_rpa_vcfg);  in __vxge_hw_vpath_mac_configure()
4247 		writeq(val64, &vp_reg->xmac_rpa_vcfg);  in __vxge_hw_vpath_mac_configure()
4248 		val64 = readq(&vp_reg->rxmac_vcfg0);  in __vxge_hw_vpath_mac_configure()
4263 		writeq(val64, &vp_reg->rxmac_vcfg0);  in __vxge_hw_vpath_mac_configure()
4265 		val64 = readq(&vp_reg->rxmac_vcfg1);  in __vxge_hw_vpath_mac_configure()
4277 		writeq(val64, &vp_reg->rxmac_vcfg1);  in __vxge_hw_vpath_mac_configure()
4292 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_tim_configure()  local
4296 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_tim_configure()
4299 	writeq(0, &vp_reg->tim_dest_addr);  in __vxge_hw_vpath_tim_configure()
4300 	writeq(0, &vp_reg->tim_vpath_map);  in __vxge_hw_vpath_tim_configure()
4301 	writeq(0, &vp_reg->tim_bitmap);  in __vxge_hw_vpath_tim_configure()
4302 	writeq(0, &vp_reg->tim_remap);  in __vxge_hw_vpath_tim_configure()
4307 			VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);  in __vxge_hw_vpath_tim_configure()
4309 	val64 = readq(&vp_reg->tim_pci_cfg);  in __vxge_hw_vpath_tim_configure()
4311 	writeq(val64, &vp_reg->tim_pci_cfg);  in __vxge_hw_vpath_tim_configure()
4315 		val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4358 		writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4361 		val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4387 		writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4388 		val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4416 		writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4422 		val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4465 		writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4468 		val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4494 		writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4495 		val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4523 		writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4528 	writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);  in __vxge_hw_vpath_tim_configure()
4529 	writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);  in __vxge_hw_vpath_tim_configure()
4530 	writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);  in __vxge_hw_vpath_tim_configure()
4531 	writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);  in __vxge_hw_vpath_tim_configure()
4532 	writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);  in __vxge_hw_vpath_tim_configure()
4533 	writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);  in __vxge_hw_vpath_tim_configure()
4538 	writeq(val64, &vp_reg->tim_wrkld_clc);  in __vxge_hw_vpath_tim_configure()
4555 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_initialize()  local
4563 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_initialize()
4565 	status =  __vxge_hw_vpath_swapper_set(vpath->vp_reg);  in __vxge_hw_vpath_initialize()
4581 	val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);  in __vxge_hw_vpath_initialize()
4601 	writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);  in __vxge_hw_vpath_initialize()
4673 	vpath->vp_reg = hldev->vpath_reg[vp_id];  in __vxge_hw_vp_initialize()
4727 	val64 = readq(&vpath->vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_mtu_set()
4732 	writeq(val64, &vpath->vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_mtu_set()
4870 	writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);  in vxge_hw_vpath_open()
4918 		new_count = readq(&vpath->vp_reg->rxdmem_size);  in vxge_hw_vpath_rx_doorbell_init()
4926 		&vpath->vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_rx_doorbell_init()
4927 	readl(&vpath->vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_rx_doorbell_init()
4930 	val64 = readq(&vpath->vp_reg->prc_cfg6);  in vxge_hw_vpath_rx_doorbell_init()
5088 		&vpath->vp_reg->stats_cfg);  in vxge_hw_vpath_recover_from_reset()