Lines Matching refs:val64
121 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ argument
1019 register u64 val64 = 0; in s2io_verify_pci_mode() local
1022 val64 = readq(&bar0->pci_mode); in s2io_verify_pci_mode()
1023 mode = (u8)GET_PCI_MODE(val64); in s2io_verify_pci_mode()
1025 if (val64 & PCI_MODE_UNKNOWN_MODE) in s2io_verify_pci_mode()
1053 register u64 val64 = 0; in s2io_print_pci_mode() local
1058 val64 = readq(&bar0->pci_mode); in s2io_print_pci_mode()
1059 mode = (u8)GET_PCI_MODE(val64); in s2io_print_pci_mode()
1061 if (val64 & PCI_MODE_UNKNOWN_MODE) in s2io_print_pci_mode()
1103 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode); in s2io_print_pci_mode()
1121 register u64 val64 = 0; in init_tti() local
1133 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count); in init_tti()
1135 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078); in init_tti()
1137 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) | in init_tti()
1143 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN; in init_tti()
1144 writeq(val64, &bar0->tti_data1_mem); in init_tti()
1147 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | in init_tti()
1158 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) | in init_tti()
1163 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | in init_tti()
1169 writeq(val64, &bar0->tti_data2_mem); in init_tti()
1171 val64 = TTI_CMD_MEM_WE | in init_tti()
1174 writeq(val64, &bar0->tti_command_mem); in init_tti()
1198 register u64 val64 = 0; in init_nic() local
1218 val64 = 0xA500000000ULL; in init_nic()
1219 writeq(val64, &bar0->sw_reset); in init_nic()
1221 val64 = readq(&bar0->sw_reset); in init_nic()
1225 val64 = 0; in init_nic()
1226 writeq(val64, &bar0->sw_reset); in init_nic()
1228 val64 = readq(&bar0->sw_reset); in init_nic()
1235 val64 = readq(&bar0->adapter_status); in init_nic()
1236 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING)) in init_nic()
1246 val64 = readq(&bar0->mac_cfg); in init_nic()
1247 val64 |= MAC_RMAC_BCAST_ENABLE; in init_nic()
1249 writel((u32)val64, add); in init_nic()
1251 writel((u32) (val64 >> 32), (add + 4)); in init_nic()
1254 val64 = readq(&bar0->mac_int_mask); in init_nic()
1255 val64 = readq(&bar0->mc_int_mask); in init_nic()
1256 val64 = readq(&bar0->xgxs_int_mask); in init_nic()
1259 val64 = dev->mtu; in init_nic()
1260 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in init_nic()
1274 val64 = readq(&bar0->dtx_control); in init_nic()
1280 val64 = 0; in init_nic()
1281 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1282 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1283 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1284 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1289 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) | in init_nic()
1299 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1300 val64 = 0; in init_nic()
1304 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1305 val64 = 0; in init_nic()
1309 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1310 val64 = 0; in init_nic()
1314 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1315 val64 = 0; in init_nic()
1331 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1333 &bar0->tx_fifo_partition_0, (unsigned long long)val64); in init_nic()
1339 val64 = readq(&bar0->tx_pa_cfg); in init_nic()
1340 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | in init_nic()
1344 writeq(val64, &bar0->tx_pa_cfg); in init_nic()
1347 val64 = 0; in init_nic()
1351 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3); in init_nic()
1353 writeq(val64, &bar0->rx_queue_priority); in init_nic()
1359 val64 = 0; in init_nic()
1370 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share); in init_nic()
1374 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share); in init_nic()
1378 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share); in init_nic()
1382 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share); in init_nic()
1386 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share); in init_nic()
1390 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share); in init_nic()
1394 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share); in init_nic()
1398 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share); in init_nic()
1402 writeq(val64, &bar0->rx_queue_cfg); in init_nic()
1410 val64 = 0x0; in init_nic()
1411 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1412 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1413 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1414 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1415 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1418 val64 = 0x0001000100010001ULL; in init_nic()
1419 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1420 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1421 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1422 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1423 val64 = 0x0001000100000000ULL; in init_nic()
1424 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1427 val64 = 0x0001020001020001ULL; in init_nic()
1428 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1429 val64 = 0x0200010200010200ULL; in init_nic()
1430 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1431 val64 = 0x0102000102000102ULL; in init_nic()
1432 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1433 val64 = 0x0001020001020001ULL; in init_nic()
1434 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1435 val64 = 0x0200010200000000ULL; in init_nic()
1436 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1439 val64 = 0x0001020300010203ULL; in init_nic()
1440 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1441 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1442 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1443 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1444 val64 = 0x0001020300000000ULL; in init_nic()
1445 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1448 val64 = 0x0001020304000102ULL; in init_nic()
1449 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1450 val64 = 0x0304000102030400ULL; in init_nic()
1451 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1452 val64 = 0x0102030400010203ULL; in init_nic()
1453 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1454 val64 = 0x0400010203040001ULL; in init_nic()
1455 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1456 val64 = 0x0203040000000000ULL; in init_nic()
1457 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1460 val64 = 0x0001020304050001ULL; in init_nic()
1461 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1462 val64 = 0x0203040500010203ULL; in init_nic()
1463 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1464 val64 = 0x0405000102030405ULL; in init_nic()
1465 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1466 val64 = 0x0001020304050001ULL; in init_nic()
1467 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1468 val64 = 0x0203040500000000ULL; in init_nic()
1469 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1472 val64 = 0x0001020304050600ULL; in init_nic()
1473 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1474 val64 = 0x0102030405060001ULL; in init_nic()
1475 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1476 val64 = 0x0203040506000102ULL; in init_nic()
1477 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1478 val64 = 0x0304050600010203ULL; in init_nic()
1479 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1480 val64 = 0x0405060000000000ULL; in init_nic()
1481 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1484 val64 = 0x0001020304050607ULL; in init_nic()
1485 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1486 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1487 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1488 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1489 val64 = 0x0001020300000000ULL; in init_nic()
1490 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1495 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1496 val64 |= (TX_FIFO_PARTITION_EN); in init_nic()
1497 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1505 val64 = 0x0; in init_nic()
1506 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1507 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1508 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1509 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1510 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1512 val64 = 0x8080808080808080ULL; in init_nic()
1513 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1516 val64 = 0x0001000100010001ULL; in init_nic()
1517 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1518 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1519 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1520 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1521 val64 = 0x0001000100000000ULL; in init_nic()
1522 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1524 val64 = 0x8080808040404040ULL; in init_nic()
1525 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1528 val64 = 0x0001020001020001ULL; in init_nic()
1529 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1530 val64 = 0x0200010200010200ULL; in init_nic()
1531 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1532 val64 = 0x0102000102000102ULL; in init_nic()
1533 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1534 val64 = 0x0001020001020001ULL; in init_nic()
1535 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1536 val64 = 0x0200010200000000ULL; in init_nic()
1537 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1539 val64 = 0x8080804040402020ULL; in init_nic()
1540 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1543 val64 = 0x0001020300010203ULL; in init_nic()
1544 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1545 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1546 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1547 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1548 val64 = 0x0001020300000000ULL; in init_nic()
1549 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1551 val64 = 0x8080404020201010ULL; in init_nic()
1552 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1555 val64 = 0x0001020304000102ULL; in init_nic()
1556 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1557 val64 = 0x0304000102030400ULL; in init_nic()
1558 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1559 val64 = 0x0102030400010203ULL; in init_nic()
1560 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1561 val64 = 0x0400010203040001ULL; in init_nic()
1562 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1563 val64 = 0x0203040000000000ULL; in init_nic()
1564 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1566 val64 = 0x8080404020201008ULL; in init_nic()
1567 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1570 val64 = 0x0001020304050001ULL; in init_nic()
1571 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1572 val64 = 0x0203040500010203ULL; in init_nic()
1573 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1574 val64 = 0x0405000102030405ULL; in init_nic()
1575 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1576 val64 = 0x0001020304050001ULL; in init_nic()
1577 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1578 val64 = 0x0203040500000000ULL; in init_nic()
1579 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1581 val64 = 0x8080404020100804ULL; in init_nic()
1582 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1585 val64 = 0x0001020304050600ULL; in init_nic()
1586 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1587 val64 = 0x0102030405060001ULL; in init_nic()
1588 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1589 val64 = 0x0203040506000102ULL; in init_nic()
1590 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1591 val64 = 0x0304050600010203ULL; in init_nic()
1592 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1593 val64 = 0x0405060000000000ULL; in init_nic()
1594 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1596 val64 = 0x8080402010080402ULL; in init_nic()
1597 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1600 val64 = 0x0001020304050607ULL; in init_nic()
1601 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1602 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1603 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1604 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1605 val64 = 0x0001020300000000ULL; in init_nic()
1606 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1608 val64 = 0x8040201008040201ULL; in init_nic()
1609 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1614 val64 = 0; in init_nic()
1616 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1619 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22); in init_nic()
1621 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1653 val64 = STAT_BC(0x320); in init_nic()
1654 writeq(val64, &bar0->stat_byte_cnt); in init_nic()
1661 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) | in init_nic()
1663 writeq(val64, &bar0->mac_link_util); in init_nic()
1681 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count); in init_nic()
1683 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF); in init_nic()
1684 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) | in init_nic()
1689 writeq(val64, &bar0->rti_data1_mem); in init_nic()
1691 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | in init_nic()
1694 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | in init_nic()
1697 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | in init_nic()
1699 writeq(val64, &bar0->rti_data2_mem); in init_nic()
1702 val64 = RTI_CMD_MEM_WE | in init_nic()
1705 writeq(val64, &bar0->rti_command_mem); in init_nic()
1716 val64 = readq(&bar0->rti_command_mem); in init_nic()
1717 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) in init_nic()
1739 val64 = readq(&bar0->mac_cfg); in init_nic()
1740 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD); in init_nic()
1742 writel((u32) (val64), add); in init_nic()
1744 writel((u32) (val64 >> 32), (add + 4)); in init_nic()
1745 val64 = readq(&bar0->mac_cfg); in init_nic()
1749 val64 = readq(&bar0->mac_cfg); in init_nic()
1750 val64 |= MAC_CFG_RMAC_STRIP_FCS; in init_nic()
1752 writeq(val64, &bar0->mac_cfg); in init_nic()
1755 writel((u32) (val64), add); in init_nic()
1757 writel((u32) (val64 >> 32), (add + 4)); in init_nic()
1764 val64 = readq(&bar0->rmac_pause_cfg); in init_nic()
1765 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff)); in init_nic()
1766 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time); in init_nic()
1767 writeq(val64, &bar0->rmac_pause_cfg); in init_nic()
1775 val64 = 0; in init_nic()
1777 val64 |= (((u64)0xFF00 | in init_nic()
1781 writeq(val64, &bar0->mc_pause_thresh_q0q3); in init_nic()
1783 val64 = 0; in init_nic()
1785 val64 |= (((u64)0xFF00 | in init_nic()
1789 writeq(val64, &bar0->mc_pause_thresh_q4q7); in init_nic()
1795 val64 = readq(&bar0->pic_control); in init_nic()
1796 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits); in init_nic()
1797 writeq(val64, &bar0->pic_control); in init_nic()
1810 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN | in init_nic()
1812 writeq(val64, &bar0->misc_control); in init_nic()
1813 val64 = readq(&bar0->pic_control2); in init_nic()
1814 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15)); in init_nic()
1815 writeq(val64, &bar0->pic_control2); in init_nic()
1818 val64 = TMAC_AVG_IPG(0x17); in init_nic()
1819 writeq(val64, &bar0->tmac_avg_ipg); in init_nic()
2083 u64 val64 = readq(&bar0->adapter_status); in verify_pcc_quiescent() local
2089 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE)) in verify_pcc_quiescent()
2092 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE)) in verify_pcc_quiescent()
2097 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == in verify_pcc_quiescent()
2101 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) == in verify_pcc_quiescent()
2123 u64 val64 = readq(&bar0->adapter_status); in verify_xena_quiescence() local
2126 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) { in verify_xena_quiescence()
2130 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) { in verify_xena_quiescence()
2134 if (!(val64 & ADAPTER_STATUS_PFC_READY)) { in verify_xena_quiescence()
2138 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) { in verify_xena_quiescence()
2142 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) { in verify_xena_quiescence()
2146 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) { in verify_xena_quiescence()
2150 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) { in verify_xena_quiescence()
2154 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) { in verify_xena_quiescence()
2164 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) && in verify_xena_quiescence()
2170 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == in verify_xena_quiescence()
2215 register u64 val64 = 0; in start_nic() local
2227 val64 = readq(&bar0->prc_ctrl_n[i]); in start_nic()
2229 val64 |= PRC_CTRL_RC_ENABLED; in start_nic()
2231 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3; in start_nic()
2233 val64 |= PRC_CTRL_GROUP_READS; in start_nic()
2234 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF); in start_nic()
2235 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000); in start_nic()
2236 writeq(val64, &bar0->prc_ctrl_n[i]); in start_nic()
2241 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2242 val64 |= RX_PA_CFG_IGNORE_L2_ERR; in start_nic()
2243 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2247 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2248 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; in start_nic()
2249 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2258 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2259 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE; in start_nic()
2260 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in start_nic()
2261 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2266 val64 = readq(&bar0->adapter_control); in start_nic()
2267 val64 &= ~ADAPTER_ECC_EN; in start_nic()
2268 writeq(val64, &bar0->adapter_control); in start_nic()
2274 val64 = readq(&bar0->adapter_status); in start_nic()
2278 dev->name, (unsigned long long)val64); in start_nic()
2291 val64 = readq(&bar0->adapter_control); in start_nic()
2292 val64 |= ADAPTER_EOI_TX_ON; in start_nic()
2293 writeq(val64, &bar0->adapter_control); in start_nic()
2306 val64 = readq(&bar0->gpio_control); in start_nic()
2307 val64 |= 0x0000800000000000ULL; in start_nic()
2308 writeq(val64, &bar0->gpio_control); in start_nic()
2309 val64 = 0x0411040400000000ULL; in start_nic()
2310 writeq(val64, (void __iomem *)bar0 + 0x2700); in start_nic()
2413 register u64 val64 = 0; in stop_nic() local
2423 val64 = readq(&bar0->adapter_control); in stop_nic()
2424 val64 &= ~(ADAPTER_CNTL_EN); in stop_nic()
2425 writeq(val64, &bar0->adapter_control); in stop_nic()
2843 u64 val64 = 0xFFFFFFFFFFFFFFFFULL; in s2io_netpoll() local
2853 writeq(val64, &bar0->rx_traffic_int); in s2io_netpoll()
2854 writeq(val64, &bar0->tx_traffic_int); in s2io_netpoll()
3098 u64 val64; in s2io_mdio_write() local
3103 val64 = MDIO_MMD_INDX_ADDR(addr) | in s2io_mdio_write()
3106 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3107 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_write()
3108 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3112 val64 = MDIO_MMD_INDX_ADDR(addr) | in s2io_mdio_write()
3117 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3118 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_write()
3119 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3122 val64 = MDIO_MMD_INDX_ADDR(addr) | in s2io_mdio_write()
3126 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3127 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_write()
3128 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3143 u64 val64 = 0x0; in s2io_mdio_read() local
3149 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr) in s2io_mdio_read()
3152 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3153 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_read()
3154 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3158 val64 = MDIO_MMD_INDX_ADDR(addr) | in s2io_mdio_read()
3162 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3163 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_read()
3164 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3188 u64 val64; in s2io_chk_xpak_counter() local
3195 val64 = *regs_stat & mask; in s2io_chk_xpak_counter()
3196 val64 = val64 >> (index * 0x2); in s2io_chk_xpak_counter()
3197 val64 = val64 + 1; in s2io_chk_xpak_counter()
3198 if (val64 == 3) { in s2io_chk_xpak_counter()
3222 val64 = 0x0; in s2io_chk_xpak_counter()
3224 val64 = val64 << (index * 0x2); in s2io_chk_xpak_counter()
3225 *regs_stat = (*regs_stat & (~mask)) | (val64); in s2io_chk_xpak_counter()
3244 u64 val64 = 0x0; in s2io_updt_xpak_counter() local
3253 val64 = 0x0; in s2io_updt_xpak_counter()
3254 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); in s2io_updt_xpak_counter()
3255 if ((val64 == 0xFFFF) || (val64 == 0x0000)) { in s2io_updt_xpak_counter()
3258 (unsigned long long)val64); in s2io_updt_xpak_counter()
3263 if (val64 != MDIO_CTRL1_SPEED10G) { in s2io_updt_xpak_counter()
3266 (unsigned long long)val64, MDIO_CTRL1_SPEED10G); in s2io_updt_xpak_counter()
3273 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); in s2io_updt_xpak_counter()
3277 val64 = 0x0; in s2io_updt_xpak_counter()
3278 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); in s2io_updt_xpak_counter()
3280 flag = CHECKBIT(val64, 0x7); in s2io_updt_xpak_counter()
3286 if (CHECKBIT(val64, 0x6)) in s2io_updt_xpak_counter()
3289 flag = CHECKBIT(val64, 0x3); in s2io_updt_xpak_counter()
3295 if (CHECKBIT(val64, 0x2)) in s2io_updt_xpak_counter()
3298 flag = CHECKBIT(val64, 0x1); in s2io_updt_xpak_counter()
3304 if (CHECKBIT(val64, 0x0)) in s2io_updt_xpak_counter()
3309 val64 = 0x0; in s2io_updt_xpak_counter()
3310 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); in s2io_updt_xpak_counter()
3312 if (CHECKBIT(val64, 0x7)) in s2io_updt_xpak_counter()
3315 if (CHECKBIT(val64, 0x6)) in s2io_updt_xpak_counter()
3318 if (CHECKBIT(val64, 0x3)) in s2io_updt_xpak_counter()
3321 if (CHECKBIT(val64, 0x2)) in s2io_updt_xpak_counter()
3324 if (CHECKBIT(val64, 0x1)) in s2io_updt_xpak_counter()
3327 if (CHECKBIT(val64, 0x0)) in s2io_updt_xpak_counter()
3346 u64 val64; in wait_for_cmd_complete() local
3352 val64 = readq(addr); in wait_for_cmd_complete()
3354 if (!(val64 & busy_bit)) { in wait_for_cmd_complete()
3359 if (val64 & busy_bit) { in wait_for_cmd_complete()
3408 u64 val64; in s2io_reset() local
3423 val64 = SW_RESET_ALL; in s2io_reset()
3424 writeq(val64, &bar0->sw_reset); in s2io_reset()
3499 val64 = readq(&bar0->gpio_control); in s2io_reset()
3500 val64 |= 0x0000800000000000ULL; in s2io_reset()
3501 writeq(val64, &bar0->gpio_control); in s2io_reset()
3502 val64 = 0x0411040400000000ULL; in s2io_reset()
3503 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_reset()
3511 val64 = readq(&bar0->pcc_err_reg); in s2io_reset()
3512 writeq(val64, &bar0->pcc_err_reg); in s2io_reset()
3532 u64 val64, valt, valr; in s2io_set_swapper() local
3539 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3540 if (val64 != 0x0123456789ABCDEFULL) { in s2io_set_swapper()
3551 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3552 if (val64 == 0x0123456789ABCDEFULL) in s2io_set_swapper()
3559 dev->name, (unsigned long long)val64); in s2io_set_swapper()
3569 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3571 if (val64 != valt) { in s2io_set_swapper()
3583 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3584 if (val64 == valt) in s2io_set_swapper()
3589 unsigned long long x = val64; in s2io_set_swapper()
3595 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3596 val64 &= 0xFFFF000000000000ULL; in s2io_set_swapper()
3603 val64 |= (SWAPPER_CTRL_TXP_FE | in s2io_set_swapper()
3615 val64 |= SWAPPER_CTRL_XMSI_SE; in s2io_set_swapper()
3616 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3623 val64 |= (SWAPPER_CTRL_TXP_FE | in s2io_set_swapper()
3639 val64 |= SWAPPER_CTRL_XMSI_SE; in s2io_set_swapper()
3640 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3642 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3648 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3649 if (val64 != 0x0123456789ABCDEFULL) { in s2io_set_swapper()
3653 dev->name, (unsigned long long)val64); in s2io_set_swapper()
3663 u64 val64; in wait_for_msix_trans() local
3667 val64 = readq(&bar0->xmsi_access); in wait_for_msix_trans()
3668 if (!(val64 & s2BIT(15))) in wait_for_msix_trans()
3684 u64 val64; in restore_xmsi_data() local
3694 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6)); in restore_xmsi_data()
3695 writeq(val64, &bar0->xmsi_access); in restore_xmsi_data()
3707 u64 val64, addr, data; in store_xmsi_data() local
3716 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6)); in store_xmsi_data()
3717 writeq(val64, &bar0->xmsi_access); in store_xmsi_data()
3833 u64 val64, saved64; in s2io_test_msi() local
3846 saved64 = val64 = readq(&bar0->scheduled_int_ctrl); in s2io_test_msi()
3847 val64 |= SCHED_INT_CTRL_ONE_SHOT; in s2io_test_msi()
3848 val64 |= SCHED_INT_CTRL_TIMER_EN; in s2io_test_msi()
3849 val64 |= SCHED_INT_CTRL_INT2MSI(1); in s2io_test_msi()
3850 writeq(val64, &bar0->scheduled_int_ctrl); in s2io_test_msi()
4018 register u64 val64; in s2io_xmit() local
4201 val64 = fifo->list_info[put_off].list_phy_addr; in s2io_xmit()
4202 writeq(val64, &tx_fifo->TxDL_Pointer); in s2io_xmit()
4204 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST | in s2io_xmit()
4207 val64 |= TX_FIFO_SPECIAL_FUNC; in s2io_xmit()
4209 writeq(val64, &tx_fifo->List_Control); in s2io_xmit()
4320 u64 val64; in s2io_txpic_intr_handle() local
4322 val64 = readq(&bar0->pic_int_status); in s2io_txpic_intr_handle()
4323 if (val64 & PIC_INT_GPIO) { in s2io_txpic_intr_handle()
4324 val64 = readq(&bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4325 if ((val64 & GPIO_INT_REG_LINK_DOWN) && in s2io_txpic_intr_handle()
4326 (val64 & GPIO_INT_REG_LINK_UP)) { in s2io_txpic_intr_handle()
4331 val64 |= GPIO_INT_REG_LINK_DOWN; in s2io_txpic_intr_handle()
4332 val64 |= GPIO_INT_REG_LINK_UP; in s2io_txpic_intr_handle()
4333 writeq(val64, &bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4334 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4335 val64 &= ~(GPIO_INT_MASK_LINK_UP | in s2io_txpic_intr_handle()
4337 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4338 } else if (val64 & GPIO_INT_REG_LINK_UP) { in s2io_txpic_intr_handle()
4339 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4341 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4342 val64 |= ADAPTER_CNTL_EN; in s2io_txpic_intr_handle()
4343 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4344 val64 |= ADAPTER_LED_ON; in s2io_txpic_intr_handle()
4345 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4354 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4355 val64 &= ~GPIO_INT_MASK_LINK_DOWN; in s2io_txpic_intr_handle()
4356 val64 |= GPIO_INT_MASK_LINK_UP; in s2io_txpic_intr_handle()
4357 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4359 } else if (val64 & GPIO_INT_REG_LINK_DOWN) { in s2io_txpic_intr_handle()
4360 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4363 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4364 val64 &= ~GPIO_INT_MASK_LINK_UP; in s2io_txpic_intr_handle()
4365 val64 |= GPIO_INT_MASK_LINK_DOWN; in s2io_txpic_intr_handle()
4366 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4369 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4370 val64 = val64 & (~ADAPTER_LED_ON); in s2io_txpic_intr_handle()
4371 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4374 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4390 u64 val64; in do_s2io_chk_alarm_bit() local
4391 val64 = readq(addr); in do_s2io_chk_alarm_bit()
4392 if (val64 & value) { in do_s2io_chk_alarm_bit()
4393 writeq(val64, addr); in do_s2io_chk_alarm_bit()
4414 u64 temp64 = 0, val64 = 0; in s2io_handle_errors() local
4441 val64 = readq(&bar0->mac_rmac_err_reg); in s2io_handle_errors()
4442 writeq(val64, &bar0->mac_rmac_err_reg); in s2io_handle_errors()
4443 if (val64 & RMAC_LINK_STATE_CHANGE_INT) in s2io_handle_errors()
4459 val64 = readq(&bar0->ring_bump_counter1); in s2io_handle_errors()
4461 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16)); in s2io_handle_errors()
4466 val64 = readq(&bar0->ring_bump_counter2); in s2io_handle_errors()
4468 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16)); in s2io_handle_errors()
4474 val64 = readq(&bar0->txdma_int_status); in s2io_handle_errors()
4476 if (val64 & TXDMA_PFC_INT) { in s2io_handle_errors()
4489 if (val64 & TXDMA_TDA_INT) { in s2io_handle_errors()
4501 if (val64 & TXDMA_PCC_INT) { in s2io_handle_errors()
4516 if (val64 & TXDMA_TTI_INT) { in s2io_handle_errors()
4527 if (val64 & TXDMA_LSO_INT) { in s2io_handle_errors()
4539 if (val64 & TXDMA_TPA_INT) { in s2io_handle_errors()
4550 if (val64 & TXDMA_SM_INT) { in s2io_handle_errors()
4557 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4558 if (val64 & MAC_INT_STATUS_TMAC_INT) { in s2io_handle_errors()
4570 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4571 if (val64 & XGXS_INT_STATUS_TXGXS) { in s2io_handle_errors()
4581 val64 = readq(&bar0->rxdma_int_status); in s2io_handle_errors()
4582 if (val64 & RXDMA_INT_RC_INT_M) { in s2io_handle_errors()
4607 if (val64 & RXDMA_INT_RPA_INT_M) { in s2io_handle_errors()
4617 if (val64 & RXDMA_INT_RDA_INT_M) { in s2io_handle_errors()
4634 if (val64 & RXDMA_INT_RTI_INT_M) { in s2io_handle_errors()
4644 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4645 if (val64 & MAC_INT_STATUS_RMAC_INT) { in s2io_handle_errors()
4657 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4658 if (val64 & XGXS_INT_STATUS_RXGXS) { in s2io_handle_errors()
4665 val64 = readq(&bar0->mc_int_status); in s2io_handle_errors()
4666 if (val64 & MC_INT_STATUS_MC_INT) { in s2io_handle_errors()
4673 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) { in s2io_handle_errors()
4674 writeq(val64, &bar0->mc_err_reg); in s2io_handle_errors()
4675 if (val64 & MC_ERR_REG_ECC_ALL_DBL) { in s2io_handle_errors()
4681 if (val64 & in s2io_handle_errors()
4813 u64 val64; in s2io_updt_stats() local
4818 val64 = SET_UPDT_CLICKS(10) | in s2io_updt_stats()
4820 writeq(val64, &bar0->stat_cfg); in s2io_updt_stats()
4823 val64 = readq(&bar0->stat_cfg); in s2io_updt_stats()
4824 if (!(val64 & s2BIT(0))) in s2io_updt_stats()
4940 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask = in s2io_set_multicast() local
4952 val64 = RMAC_ADDR_CMD_MEM_WE | in s2io_set_multicast()
4955 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4969 val64 = RMAC_ADDR_CMD_MEM_WE | in s2io_set_multicast()
4972 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4985 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4986 val64 |= MAC_CFG_RMAC_PROM_ENABLE; in s2io_set_multicast()
4989 writel((u32)val64, add); in s2io_set_multicast()
4991 writel((u32) (val64 >> 32), (add + 4)); in s2io_set_multicast()
4994 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
4995 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; in s2io_set_multicast()
4996 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
5000 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
5007 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
5008 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE; in s2io_set_multicast()
5011 writel((u32)val64, add); in s2io_set_multicast()
5013 writel((u32) (val64 >> 32), (add + 4)); in s2io_set_multicast()
5016 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
5017 val64 |= RX_PA_CFG_STRIP_VLAN_TAG; in s2io_set_multicast()
5018 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
5022 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
5047 val64 = RMAC_ADDR_CMD_MEM_WE | in s2io_set_multicast()
5051 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5077 val64 = RMAC_ADDR_CMD_MEM_WE | in s2io_set_multicast()
5081 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5170 u64 val64; in do_s2io_add_mac() local
5176 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | in do_s2io_add_mac()
5178 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_add_mac()
5216 u64 tmp64 = 0xffffffffffff0000ULL, val64; in do_s2io_read_unicast_mc() local
5220 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | in do_s2io_read_unicast_mc()
5222 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_read_unicast_mc()
5432 u64 val64; in s2io_set_led() local
5436 val64 = readq(&bar0->gpio_control); in s2io_set_led()
5438 val64 |= GPIO_CTRL_GPIO_0; in s2io_set_led()
5440 val64 &= ~GPIO_CTRL_GPIO_0; in s2io_set_led()
5442 writeq(val64, &bar0->gpio_control); in s2io_set_led()
5444 val64 = readq(&bar0->adapter_control); in s2io_set_led()
5446 val64 |= ADAPTER_LED_ON; in s2io_set_led()
5448 val64 &= ~ADAPTER_LED_ON; in s2io_set_led()
5450 writeq(val64, &bar0->adapter_control); in s2io_set_led()
5475 u64 val64 = readq(&bar0->adapter_control); in s2io_ethtool_set_led() local
5476 if (!(val64 & ADAPTER_CNTL_EN)) { in s2io_ethtool_set_led()
5543 u64 val64; in s2io_ethtool_getpause_data() local
5547 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_getpause_data()
5548 if (val64 & RMAC_PAUSE_GEN_ENABLE) in s2io_ethtool_getpause_data()
5550 if (val64 & RMAC_PAUSE_RX_ENABLE) in s2io_ethtool_getpause_data()
5570 u64 val64; in s2io_ethtool_setpause_data() local
5574 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5576 val64 |= RMAC_PAUSE_GEN_ENABLE; in s2io_ethtool_setpause_data()
5578 val64 &= ~RMAC_PAUSE_GEN_ENABLE; in s2io_ethtool_setpause_data()
5580 val64 |= RMAC_PAUSE_RX_ENABLE; in s2io_ethtool_setpause_data()
5582 val64 &= ~RMAC_PAUSE_RX_ENABLE; in s2io_ethtool_setpause_data()
5583 writeq(val64, &bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5608 u64 val64; in read_eeprom() local
5612 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | in read_eeprom()
5617 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in read_eeprom()
5620 val64 = readq(&bar0->i2c_control); in read_eeprom()
5621 if (I2C_CONTROL_CNTL_END(val64)) { in read_eeprom()
5622 *data = I2C_CONTROL_GET_DATA(val64); in read_eeprom()
5632 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | in read_eeprom()
5635 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5636 val64 |= SPI_CONTROL_REQ; in read_eeprom()
5637 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5639 val64 = readq(&bar0->spi_control); in read_eeprom()
5640 if (val64 & SPI_CONTROL_NACK) { in read_eeprom()
5643 } else if (val64 & SPI_CONTROL_DONE) { in read_eeprom()
5674 u64 val64; in write_eeprom() local
5678 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | in write_eeprom()
5683 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in write_eeprom()
5686 val64 = readq(&bar0->i2c_control); in write_eeprom()
5687 if (I2C_CONTROL_CNTL_END(val64)) { in write_eeprom()
5688 if (!(val64 & I2C_CONTROL_NACK)) in write_eeprom()
5701 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | in write_eeprom()
5704 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5705 val64 |= SPI_CONTROL_REQ; in write_eeprom()
5706 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5708 val64 = readq(&bar0->spi_control); in write_eeprom()
5709 if (val64 & SPI_CONTROL_NACK) { in write_eeprom()
5712 } else if (val64 & SPI_CONTROL_DONE) { in write_eeprom()
5897 u64 val64 = 0, exp_val; in s2io_register_test() local
5900 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_register_test()
5901 if (val64 != 0x123456789abcdefULL) { in s2io_register_test()
5906 val64 = readq(&bar0->rmac_pause_cfg); in s2io_register_test()
5907 if (val64 != 0xc000ffff00000000ULL) { in s2io_register_test()
5912 val64 = readq(&bar0->rx_queue_cfg); in s2io_register_test()
5917 if (val64 != exp_val) { in s2io_register_test()
5922 val64 = readq(&bar0->xgxs_efifo_cfg); in s2io_register_test()
5923 if (val64 != 0x000000001923141EULL) { in s2io_register_test()
5928 val64 = 0x5A5A5A5A5A5A5A5AULL; in s2io_register_test()
5929 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5930 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
5931 if (val64 != 0x5A5A5A5A5A5A5A5AULL) { in s2io_register_test()
5936 val64 = 0xA5A5A5A5A5A5A5A5ULL; in s2io_register_test()
5937 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5938 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
5939 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) { in s2io_register_test()
6102 u64 val64; in s2io_link_test() local
6104 val64 = readq(&bar0->adapter_status); in s2io_link_test()
6105 if (!(LINK_IS_UP(val64))) in s2io_link_test()
6129 u64 val64; in s2io_rldram_test() local
6132 val64 = readq(&bar0->adapter_control); in s2io_rldram_test()
6133 val64 &= ~ADAPTER_ECC_EN; in s2io_rldram_test()
6134 writeq(val64, &bar0->adapter_control); in s2io_rldram_test()
6136 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6137 val64 |= MC_RLDRAM_TEST_MODE; in s2io_rldram_test()
6138 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6140 val64 = readq(&bar0->mc_rldram_mrs); in s2io_rldram_test()
6141 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE; in s2io_rldram_test()
6142 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6144 val64 |= MC_RLDRAM_MRS_ENABLE; in s2io_rldram_test()
6145 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6148 val64 = 0x55555555aaaa0000ULL; in s2io_rldram_test()
6150 val64 ^= 0xFFFFFFFFFFFF0000ULL; in s2io_rldram_test()
6151 writeq(val64, &bar0->mc_rldram_test_d0); in s2io_rldram_test()
6153 val64 = 0xaaaa5a5555550000ULL; in s2io_rldram_test()
6155 val64 ^= 0xFFFFFFFFFFFF0000ULL; in s2io_rldram_test()
6156 writeq(val64, &bar0->mc_rldram_test_d1); in s2io_rldram_test()
6158 val64 = 0x55aaaaaaaa5a0000ULL; in s2io_rldram_test()
6160 val64 ^= 0xFFFFFFFFFFFF0000ULL; in s2io_rldram_test()
6161 writeq(val64, &bar0->mc_rldram_test_d2); in s2io_rldram_test()
6163 val64 = (u64) (0x0000003ffffe0100ULL); in s2io_rldram_test()
6164 writeq(val64, &bar0->mc_rldram_test_add); in s2io_rldram_test()
6166 val64 = MC_RLDRAM_TEST_MODE | in s2io_rldram_test()
6169 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6172 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6173 if (val64 & MC_RLDRAM_TEST_DONE) in s2io_rldram_test()
6181 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO; in s2io_rldram_test()
6182 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6185 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6186 if (val64 & MC_RLDRAM_TEST_DONE) in s2io_rldram_test()
6194 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6195 if (!(val64 & MC_RLDRAM_TEST_PASS)) in s2io_rldram_test()
6706 u64 val64 = new_mtu; in s2io_change_mtu() local
6708 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in s2io_change_mtu()
6726 register u64 val64; in s2io_set_link() local
6748 val64 = readq(&bar0->adapter_status); in s2io_set_link()
6749 if (LINK_IS_UP(val64)) { in s2io_set_link()
6752 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6753 val64 |= ADAPTER_CNTL_EN; in s2io_set_link()
6754 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6757 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6758 val64 |= GPIO_CTRL_GPIO_0; in s2io_set_link()
6759 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6760 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6762 val64 |= ADAPTER_LED_ON; in s2io_set_link()
6763 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6773 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6774 val64 |= ADAPTER_LED_ON; in s2io_set_link()
6775 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6780 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6781 val64 &= ~GPIO_CTRL_GPIO_0; in s2io_set_link()
6782 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6783 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6786 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6787 val64 = val64 & (~ADAPTER_LED_ON); in s2io_set_link()
6788 writeq(val64, &bar0->adapter_control); in s2io_set_link()
7071 register u64 val64 = 0; in do_s2io_card_down() local
7115 val64 = readq(&bar0->adapter_status); in do_s2io_card_down()
7126 (unsigned long long)val64); in do_s2io_card_down()
7655 register u64 val64 = 0; in rts_ds_steer() local
7660 val64 = RTS_DS_MEM_DATA(ring); in rts_ds_steer()
7661 writeq(val64, &bar0->rts_ds_mem_data); in rts_ds_steer()
7663 val64 = RTS_DS_MEM_CTRL_WE | in rts_ds_steer()
7667 writeq(val64, &bar0->rts_ds_mem_ctrl); in rts_ds_steer()
7713 u64 val64 = 0, tmp64 = 0; in s2io_init_nic() local
7997 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | in s2io_init_nic()
7999 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_init_nic()
8061 val64 = readq(&bar0->gpio_control); in s2io_init_nic()
8062 val64 |= 0x0000800000000000ULL; in s2io_init_nic()
8063 writeq(val64, &bar0->gpio_control); in s2io_init_nic()
8064 val64 = 0x0411040400000000ULL; in s2io_init_nic()
8065 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_init_nic()
8066 val64 = readq(&bar0->gpio_control); in s2io_init_nic()