Lines Matching refs:bar0
1018 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_verify_pci_mode() local
1022 val64 = readq(&bar0->pci_mode); in s2io_verify_pci_mode()
1052 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_print_pci_mode() local
1058 val64 = readq(&bar0->pci_mode); in s2io_print_pci_mode()
1120 struct XENA_dev_config __iomem *bar0 = nic->bar0; in init_tti() local
1144 writeq(val64, &bar0->tti_data1_mem); in init_tti()
1169 writeq(val64, &bar0->tti_data2_mem); in init_tti()
1174 writeq(val64, &bar0->tti_command_mem); in init_tti()
1176 if (wait_for_cmd_complete(&bar0->tti_command_mem, in init_tti()
1196 struct XENA_dev_config __iomem *bar0 = nic->bar0; in init_nic() local
1219 writeq(val64, &bar0->sw_reset); in init_nic()
1221 val64 = readq(&bar0->sw_reset); in init_nic()
1226 writeq(val64, &bar0->sw_reset); in init_nic()
1228 val64 = readq(&bar0->sw_reset); in init_nic()
1235 val64 = readq(&bar0->adapter_status); in init_nic()
1245 add = &bar0->mac_cfg; in init_nic()
1246 val64 = readq(&bar0->mac_cfg); in init_nic()
1248 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1250 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1254 val64 = readq(&bar0->mac_int_mask); in init_nic()
1255 val64 = readq(&bar0->mc_int_mask); in init_nic()
1256 val64 = readq(&bar0->xgxs_int_mask); in init_nic()
1260 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in init_nic()
1265 &bar0->dtx_control, UF); in init_nic()
1273 &bar0->dtx_control, UF); in init_nic()
1274 val64 = readq(&bar0->dtx_control); in init_nic()
1281 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1282 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1283 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1284 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1299 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1304 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1309 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1314 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1329 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable); in init_nic()
1331 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1333 &bar0->tx_fifo_partition_0, (unsigned long long)val64); in init_nic()
1339 val64 = readq(&bar0->tx_pa_cfg); in init_nic()
1344 writeq(val64, &bar0->tx_pa_cfg); in init_nic()
1353 writeq(val64, &bar0->rx_queue_priority); in init_nic()
1402 writeq(val64, &bar0->rx_queue_cfg); in init_nic()
1411 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1412 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1413 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1414 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1415 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1419 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1420 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1421 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1422 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1424 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1428 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1430 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1432 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1434 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1436 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1440 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1441 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1442 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1443 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1445 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1449 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1451 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1453 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1455 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1457 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1461 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1463 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1465 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1467 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1469 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1473 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1475 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1477 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1479 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1481 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1485 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1486 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1487 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1488 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1490 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1495 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1497 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1506 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1507 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1508 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1509 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1510 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1513 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1517 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1518 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1519 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1520 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1522 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1525 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1529 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1531 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1533 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1535 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1537 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1540 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1544 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1545 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1546 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1547 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1549 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1552 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1556 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1558 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1560 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1562 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1564 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1567 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1571 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1573 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1575 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1577 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1579 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1582 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1586 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1588 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1590 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1592 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1594 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1597 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1601 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1602 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1603 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1604 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1606 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1609 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1616 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1621 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1635 &bar0->rts_frm_len_n[i]); in init_nic()
1650 writeq(mac_control->stats_mem_phy, &bar0->stat_addr); in init_nic()
1654 writeq(val64, &bar0->stat_byte_cnt); in init_nic()
1663 writeq(val64, &bar0->mac_link_util); in init_nic()
1689 writeq(val64, &bar0->rti_data1_mem); in init_nic()
1699 writeq(val64, &bar0->rti_data2_mem); in init_nic()
1705 writeq(val64, &bar0->rti_command_mem); in init_nic()
1716 val64 = readq(&bar0->rti_command_mem); in init_nic()
1734 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3); in init_nic()
1735 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7); in init_nic()
1738 add = &bar0->mac_cfg; in init_nic()
1739 val64 = readq(&bar0->mac_cfg); in init_nic()
1741 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1743 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1745 val64 = readq(&bar0->mac_cfg); in init_nic()
1748 add = &bar0->mac_cfg; in init_nic()
1749 val64 = readq(&bar0->mac_cfg); in init_nic()
1752 writeq(val64, &bar0->mac_cfg); in init_nic()
1754 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1756 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1764 val64 = readq(&bar0->rmac_pause_cfg); in init_nic()
1767 writeq(val64, &bar0->rmac_pause_cfg); in init_nic()
1781 writeq(val64, &bar0->mc_pause_thresh_q0q3); in init_nic()
1789 writeq(val64, &bar0->mc_pause_thresh_q4q7); in init_nic()
1795 val64 = readq(&bar0->pic_control); in init_nic()
1797 writeq(val64, &bar0->pic_control); in init_nic()
1800 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout); in init_nic()
1801 writeq(0x0, &bar0->read_retry_delay); in init_nic()
1802 writeq(0x0, &bar0->write_retry_delay); in init_nic()
1812 writeq(val64, &bar0->misc_control); in init_nic()
1813 val64 = readq(&bar0->pic_control2); in init_nic()
1815 writeq(val64, &bar0->pic_control2); in init_nic()
1819 writeq(val64, &bar0->tmac_avg_ipg); in init_nic()
1859 struct XENA_dev_config __iomem *bar0 = nic->bar0; in en_dis_err_alarms() local
1863 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask); in en_dis_err_alarms()
1870 TXDMA_SM_INT, flag, &bar0->txdma_int_mask); in en_dis_err_alarms()
1875 &bar0->pfc_err_mask); in en_dis_err_alarms()
1879 TDA_PCIX_ERR, flag, &bar0->tda_err_mask); in en_dis_err_alarms()
1887 flag, &bar0->pcc_err_mask); in en_dis_err_alarms()
1890 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask); in en_dis_err_alarms()
1895 flag, &bar0->lso_err_mask); in en_dis_err_alarms()
1898 flag, &bar0->tpa_err_mask); in en_dis_err_alarms()
1900 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask); in en_dis_err_alarms()
1906 &bar0->mac_int_mask); in en_dis_err_alarms()
1910 flag, &bar0->mac_tmac_err_mask); in en_dis_err_alarms()
1916 &bar0->xgxs_int_mask); in en_dis_err_alarms()
1919 flag, &bar0->xgxs_txgxs_err_mask); in en_dis_err_alarms()
1926 flag, &bar0->rxdma_int_mask); in en_dis_err_alarms()
1930 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask); in en_dis_err_alarms()
1934 &bar0->prc_pcix_err_mask); in en_dis_err_alarms()
1937 &bar0->rpa_err_mask); in en_dis_err_alarms()
1943 flag, &bar0->rda_err_mask); in en_dis_err_alarms()
1946 flag, &bar0->rti_err_mask); in en_dis_err_alarms()
1952 &bar0->mac_int_mask); in en_dis_err_alarms()
1959 flag, &bar0->mac_rmac_err_mask); in en_dis_err_alarms()
1965 &bar0->xgxs_int_mask); in en_dis_err_alarms()
1967 &bar0->xgxs_rxgxs_err_mask); in en_dis_err_alarms()
1973 flag, &bar0->mc_int_mask); in en_dis_err_alarms()
1976 &bar0->mc_err_mask); in en_dis_err_alarms()
1997 struct XENA_dev_config __iomem *bar0 = nic->bar0; in en_dis_able_nic_intrs() local
2017 &bar0->pic_int_mask); in en_dis_able_nic_intrs()
2019 &bar0->gpio_int_mask); in en_dis_able_nic_intrs()
2021 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); in en_dis_able_nic_intrs()
2027 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); in en_dis_able_nic_intrs()
2039 writeq(0x0, &bar0->tx_traffic_mask); in en_dis_able_nic_intrs()
2045 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask); in en_dis_able_nic_intrs()
2054 writeq(0x0, &bar0->rx_traffic_mask); in en_dis_able_nic_intrs()
2060 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask); in en_dis_able_nic_intrs()
2064 temp64 = readq(&bar0->general_int_mask); in en_dis_able_nic_intrs()
2069 writeq(temp64, &bar0->general_int_mask); in en_dis_able_nic_intrs()
2071 nic->general_int_mask = readq(&bar0->general_int_mask); in en_dis_able_nic_intrs()
2082 struct XENA_dev_config __iomem *bar0 = sp->bar0; in verify_pcc_quiescent() local
2083 u64 val64 = readq(&bar0->adapter_status); in verify_pcc_quiescent()
2122 struct XENA_dev_config __iomem *bar0 = sp->bar0; in verify_xena_quiescence() local
2123 u64 val64 = readq(&bar0->adapter_status); in verify_xena_quiescence()
2188 struct XENA_dev_config __iomem *bar0 = sp->bar0; in fix_mac_address() local
2192 writeq(fix_mac[i++], &bar0->gpio_control); in fix_mac_address()
2194 (void) readq(&bar0->gpio_control); in fix_mac_address()
2213 struct XENA_dev_config __iomem *bar0 = nic->bar0; in start_nic() local
2225 &bar0->prc_rxd0_n[i]); in start_nic()
2227 val64 = readq(&bar0->prc_ctrl_n[i]); in start_nic()
2236 writeq(val64, &bar0->prc_ctrl_n[i]); in start_nic()
2241 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2243 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2247 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2249 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2258 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2260 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in start_nic()
2261 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2266 val64 = readq(&bar0->adapter_control); in start_nic()
2268 writeq(val64, &bar0->adapter_control); in start_nic()
2274 val64 = readq(&bar0->adapter_status); in start_nic()
2291 val64 = readq(&bar0->adapter_control); in start_nic()
2293 writeq(val64, &bar0->adapter_control); in start_nic()
2306 val64 = readq(&bar0->gpio_control); in start_nic()
2308 writeq(val64, &bar0->gpio_control); in start_nic()
2310 writeq(val64, (void __iomem *)bar0 + 0x2700); in start_nic()
2412 struct XENA_dev_config __iomem *bar0 = nic->bar0; in stop_nic() local
2423 val64 = readq(&bar0->adapter_control); in stop_nic()
2425 writeq(val64, &bar0->adapter_control); in stop_nic()
2776 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_poll_msix() local
2788 addr = (u8 __iomem *)&bar0->xmsi_mask_reg; in s2io_poll_msix()
2802 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_poll_inta() local
2822 writeq(0, &bar0->rx_traffic_mask); in s2io_poll_inta()
2823 readl(&bar0->rx_traffic_mask); in s2io_poll_inta()
2842 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_netpoll() local
2853 writeq(val64, &bar0->rx_traffic_int); in s2io_netpoll()
2854 writeq(val64, &bar0->tx_traffic_int); in s2io_netpoll()
3100 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_mdio_write() local
3106 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3108 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3117 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3119 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3126 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3128 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3146 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_mdio_read() local
3152 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3154 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3162 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3164 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3168 rval64 = readq(&bar0->mdio_control); in s2io_mdio_read()
3407 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_reset() local
3424 writeq(val64, &bar0->sw_reset); in s2io_reset()
3464 writeq(s2BIT(62), &bar0->txpic_int_reg); in s2io_reset()
3499 val64 = readq(&bar0->gpio_control); in s2io_reset()
3501 writeq(val64, &bar0->gpio_control); in s2io_reset()
3503 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_reset()
3511 val64 = readq(&bar0->pcc_err_reg); in s2io_reset()
3512 writeq(val64, &bar0->pcc_err_reg); in s2io_reset()
3531 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_set_swapper() local
3539 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3550 writeq(value[i], &bar0->swapper_ctrl); in s2io_set_swapper()
3551 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3564 valr = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3568 writeq(valt, &bar0->xmsi_address); in s2io_set_swapper()
3569 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3581 writeq((value[i] | valr), &bar0->swapper_ctrl); in s2io_set_swapper()
3582 writeq(valt, &bar0->xmsi_address); in s2io_set_swapper()
3583 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3595 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3616 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3640 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3642 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3648 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3662 struct XENA_dev_config __iomem *bar0 = nic->bar0; in wait_for_msix_trans() local
3667 val64 = readq(&bar0->xmsi_access); in wait_for_msix_trans()
3683 struct XENA_dev_config __iomem *bar0 = nic->bar0; in restore_xmsi_data() local
3692 writeq(nic->msix_info[i].addr, &bar0->xmsi_address); in restore_xmsi_data()
3693 writeq(nic->msix_info[i].data, &bar0->xmsi_data); in restore_xmsi_data()
3695 writeq(val64, &bar0->xmsi_access); in restore_xmsi_data()
3706 struct XENA_dev_config __iomem *bar0 = nic->bar0; in store_xmsi_data() local
3717 writeq(val64, &bar0->xmsi_access); in store_xmsi_data()
3723 addr = readq(&bar0->xmsi_address); in store_xmsi_data()
3724 data = readq(&bar0->xmsi_data); in store_xmsi_data()
3734 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_enable_msi_x() local
3778 rx_mat = readq(&bar0->rx_mat); in s2io_enable_msi_x()
3786 writeq(rx_mat, &bar0->rx_mat); in s2io_enable_msi_x()
3787 readq(&bar0->rx_mat); in s2io_enable_msi_x()
3831 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_test_msi() local
3846 saved64 = val64 = readq(&bar0->scheduled_int_ctrl); in s2io_test_msi()
3850 writeq(val64, &bar0->scheduled_int_ctrl); in s2io_test_msi()
3865 writeq(saved64, &bar0->scheduled_int_ctrl); in s2io_test_msi()
4257 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_msix_ring_handle() local
4266 addr = (u8 __iomem *)&bar0->xmsi_mask_reg; in s2io_msix_ring_handle()
4285 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_msix_fifo_handle() local
4292 reason = readq(&bar0->general_int_status); in s2io_msix_fifo_handle()
4298 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); in s2io_msix_fifo_handle()
4304 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); in s2io_msix_fifo_handle()
4309 writeq(sp->general_int_mask, &bar0->general_int_mask); in s2io_msix_fifo_handle()
4310 readl(&bar0->general_int_status); in s2io_msix_fifo_handle()
4319 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_txpic_intr_handle() local
4322 val64 = readq(&bar0->pic_int_status); in s2io_txpic_intr_handle()
4324 val64 = readq(&bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4333 writeq(val64, &bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4334 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4337 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4339 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4341 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4343 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4345 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4354 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4357 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4360 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4363 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4366 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4369 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4371 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4374 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4413 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_handle_errors() local
4441 val64 = readq(&bar0->mac_rmac_err_reg); in s2io_handle_errors()
4442 writeq(val64, &bar0->mac_rmac_err_reg); in s2io_handle_errors()
4448 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source, in s2io_handle_errors()
4453 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg, in s2io_handle_errors()
4459 val64 = readq(&bar0->ring_bump_counter1); in s2io_handle_errors()
4466 val64 = readq(&bar0->ring_bump_counter2); in s2io_handle_errors()
4474 val64 = readq(&bar0->txdma_int_status); in s2io_handle_errors()
4480 &bar0->pfc_err_reg, in s2io_handle_errors()
4484 &bar0->pfc_err_reg, in s2io_handle_errors()
4493 &bar0->tda_err_reg, in s2io_handle_errors()
4497 &bar0->tda_err_reg, in s2io_handle_errors()
4507 &bar0->pcc_err_reg, in s2io_handle_errors()
4511 &bar0->pcc_err_reg, in s2io_handle_errors()
4518 &bar0->tti_err_reg, in s2io_handle_errors()
4522 &bar0->tti_err_reg, in s2io_handle_errors()
4530 &bar0->lso_err_reg, in s2io_handle_errors()
4534 &bar0->lso_err_reg, in s2io_handle_errors()
4541 &bar0->tpa_err_reg, in s2io_handle_errors()
4545 &bar0->tpa_err_reg, in s2io_handle_errors()
4552 &bar0->sm_err_reg, in s2io_handle_errors()
4557 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4560 &bar0->mac_tmac_err_reg, in s2io_handle_errors()
4566 &bar0->mac_tmac_err_reg, in s2io_handle_errors()
4570 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4573 &bar0->xgxs_txgxs_err_reg, in s2io_handle_errors()
4577 &bar0->xgxs_txgxs_err_reg, in s2io_handle_errors()
4581 val64 = readq(&bar0->rxdma_int_status); in s2io_handle_errors()
4587 &bar0->rc_err_reg, in s2io_handle_errors()
4592 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg, in s2io_handle_errors()
4597 &bar0->prc_pcix_err_reg, in s2io_handle_errors()
4603 &bar0->prc_pcix_err_reg, in s2io_handle_errors()
4609 &bar0->rpa_err_reg, in s2io_handle_errors()
4613 &bar0->rpa_err_reg, in s2io_handle_errors()
4623 &bar0->rda_err_reg, in s2io_handle_errors()
4630 &bar0->rda_err_reg, in s2io_handle_errors()
4636 &bar0->rti_err_reg, in s2io_handle_errors()
4640 &bar0->rti_err_reg, in s2io_handle_errors()
4644 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4647 &bar0->mac_rmac_err_reg, in s2io_handle_errors()
4653 &bar0->mac_rmac_err_reg, in s2io_handle_errors()
4657 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4660 &bar0->xgxs_rxgxs_err_reg, in s2io_handle_errors()
4665 val64 = readq(&bar0->mc_int_status); in s2io_handle_errors()
4668 &bar0->mc_err_reg, in s2io_handle_errors()
4674 writeq(val64, &bar0->mc_err_reg); in s2io_handle_errors()
4715 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_isr() local
4738 reason = readq(&bar0->general_int_status); in s2io_isr()
4745 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); in s2io_isr()
4750 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask); in s2io_isr()
4751 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); in s2io_isr()
4752 readl(&bar0->rx_traffic_int); in s2io_isr()
4761 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); in s2io_isr()
4776 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); in s2io_isr()
4794 writeq(sp->general_int_mask, &bar0->general_int_mask); in s2io_isr()
4795 readl(&bar0->general_int_status); in s2io_isr()
4812 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_updt_stats() local
4820 writeq(val64, &bar0->stat_cfg); in s2io_updt_stats()
4823 val64 = readq(&bar0->stat_cfg); in s2io_updt_stats()
4939 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_set_multicast() local
4949 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
4951 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
4955 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4957 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
4966 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
4968 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
4972 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4974 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
4984 add = &bar0->mac_cfg; in s2io_set_multicast()
4985 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4988 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4990 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4994 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
4996 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
5000 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
5006 add = &bar0->mac_cfg; in s2io_set_multicast()
5007 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
5010 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
5012 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
5016 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
5018 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
5022 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
5044 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
5046 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
5051 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5054 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
5074 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
5076 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
5081 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5084 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
5171 struct XENA_dev_config __iomem *bar0 = sp->bar0; in do_s2io_add_mac() local
5174 &bar0->rmac_addr_data0_mem); in do_s2io_add_mac()
5178 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_add_mac()
5181 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in do_s2io_add_mac()
5217 struct XENA_dev_config __iomem *bar0 = sp->bar0; in do_s2io_read_unicast_mc() local
5222 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_read_unicast_mc()
5225 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in do_s2io_read_unicast_mc()
5231 tmp64 = readq(&bar0->rmac_addr_data0_mem); in do_s2io_read_unicast_mc()
5420 reg = readq(sp->bar0 + i); in s2io_ethtool_gregs()
5430 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_set_led() local
5436 val64 = readq(&bar0->gpio_control); in s2io_set_led()
5442 writeq(val64, &bar0->gpio_control); in s2io_set_led()
5444 val64 = readq(&bar0->adapter_control); in s2io_set_led()
5450 writeq(val64, &bar0->adapter_control); in s2io_set_led()
5471 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_ethtool_set_led() local
5475 u64 val64 = readq(&bar0->adapter_control); in s2io_ethtool_set_led()
5484 sp->adapt_ctrl_org = readq(&bar0->gpio_control); in s2io_ethtool_set_led()
5497 writeq(sp->adapt_ctrl_org, &bar0->gpio_control); in s2io_ethtool_set_led()
5545 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_ethtool_getpause_data() local
5547 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_getpause_data()
5572 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_ethtool_setpause_data() local
5574 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5583 writeq(val64, &bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5609 struct XENA_dev_config __iomem *bar0 = sp->bar0; in read_eeprom() local
5617 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in read_eeprom()
5620 val64 = readq(&bar0->i2c_control); in read_eeprom()
5635 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5637 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5639 val64 = readq(&bar0->spi_control); in read_eeprom()
5644 *data = readq(&bar0->spi_data); in read_eeprom()
5675 struct XENA_dev_config __iomem *bar0 = sp->bar0; in write_eeprom() local
5683 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in write_eeprom()
5686 val64 = readq(&bar0->i2c_control); in write_eeprom()
5699 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data); in write_eeprom()
5704 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5706 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5708 val64 = readq(&bar0->spi_control); in write_eeprom()
5896 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_register_test() local
5900 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_register_test()
5906 val64 = readq(&bar0->rmac_pause_cfg); in s2io_register_test()
5912 val64 = readq(&bar0->rx_queue_cfg); in s2io_register_test()
5922 val64 = readq(&bar0->xgxs_efifo_cfg); in s2io_register_test()
5929 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5930 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
5937 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5938 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
6101 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_link_test() local
6104 val64 = readq(&bar0->adapter_status); in s2io_link_test()
6128 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_rldram_test() local
6132 val64 = readq(&bar0->adapter_control); in s2io_rldram_test()
6134 writeq(val64, &bar0->adapter_control); in s2io_rldram_test()
6136 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6138 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6140 val64 = readq(&bar0->mc_rldram_mrs); in s2io_rldram_test()
6142 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6145 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6151 writeq(val64, &bar0->mc_rldram_test_d0); in s2io_rldram_test()
6156 writeq(val64, &bar0->mc_rldram_test_d1); in s2io_rldram_test()
6161 writeq(val64, &bar0->mc_rldram_test_d2); in s2io_rldram_test()
6164 writeq(val64, &bar0->mc_rldram_test_add); in s2io_rldram_test()
6169 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6172 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6182 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6185 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6194 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6204 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6705 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_change_mtu() local
6708 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in s2io_change_mtu()
6725 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_set_link() local
6748 val64 = readq(&bar0->adapter_status); in s2io_set_link()
6750 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) { in s2io_set_link()
6752 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6754 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6757 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6759 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6760 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6763 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6773 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6775 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6780 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6782 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6783 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6786 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6788 writeq(val64, &bar0->adapter_control); in s2io_set_link()
7070 struct XENA_dev_config __iomem *bar0 = sp->bar0; in do_s2io_card_down() local
7115 val64 = readq(&bar0->adapter_status); in do_s2io_card_down()
7654 struct XENA_dev_config __iomem *bar0 = nic->bar0; in rts_ds_steer() local
7661 writeq(val64, &bar0->rts_ds_mem_data); in rts_ds_steer()
7667 writeq(val64, &bar0->rts_ds_mem_ctrl); in rts_ds_steer()
7669 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl, in rts_ds_steer()
7714 struct XENA_dev_config __iomem *bar0 = NULL; in s2io_init_nic() local
7894 sp->bar0 = pci_ioremap_bar(pdev, 0); in s2io_init_nic()
7895 if (!sp->bar0) { in s2io_init_nic()
7996 bar0 = sp->bar0; in s2io_init_nic()
7999 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_init_nic()
8000 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_init_nic()
8003 tmp64 = readq(&bar0->rmac_addr_data0_mem); in s2io_init_nic()
8061 val64 = readq(&bar0->gpio_control); in s2io_init_nic()
8063 writeq(val64, &bar0->gpio_control); in s2io_init_nic()
8065 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_init_nic()
8066 val64 = readq(&bar0->gpio_control); in s2io_init_nic()
8182 iounmap(sp->bar0); in s2io_init_nic()
8220 iounmap(sp->bar0); in s2io_rem_nic()