620 	cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;  in phy_intr()
624 		tbisr = readl(dev->base + TBISR);  in phy_intr()
625 		tanar = readl(dev->base + TANAR);  in phy_intr()
626 		tanlpar = readl(dev->base + TANLPAR);  in phy_intr()
634 			writel(readl(dev->base + TXCFG)  in phy_intr()
637 			writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,  in phy_intr()
640 			writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,  in phy_intr()
651 			writel((readl(dev->base + TXCFG)  in phy_intr()
654 			writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,  in phy_intr()
657 			writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,  in phy_intr()
677 			writel(readl(dev->base + TXCFG)  in phy_intr()
680 			writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,  in phy_intr()
683 			writel(readl(dev->base + TXCFG)  in phy_intr()
686 			writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),  in phy_intr()
795 	readl(dev->base + IMR);  in ns83820_cleanup_rx()
843 		readl(dev->base + RXDP),
1194 	ndev->stats.rx_errors		+= readl(base + 0x60) & 0xffff;
1195 	ndev->stats.rx_crc_errors	+= readl(base + 0x64) & 0xffff;
1196 	ndev->stats.rx_missed_errors	+= readl(base + 0x68) & 0xffff;
1197 	ndev->stats.rx_frame_errors	+= readl(base + 0x6c) & 0xffff;
1198 	/*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1199 	ndev->stats.rx_length_errors	+= readl(base + 0x74) & 0xffff;
1200 	ndev->stats.rx_length_errors	+= readl(base + 0x78) & 0xffff;
1201 	/*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1202 	/*ndev->stats.rx_pause_count += */  readl(base + 0x80);
1203 	/*ndev->stats.tx_pause_count += */  readl(base + 0x84);
1204 	ndev->stats.tx_carrier_errors	+= readl(base + 0x88) & 0xff;
1241 	cfg   = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1242 	tanar = readl(dev->base + TANAR);
1243 	tbicr = readl(dev->base + TBICR);
1292 	cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1293 	tanar = readl(dev->base + TANAR);
1314 				writel(readl(dev->base + TXCFG)
1317 				writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1320 				writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1373 	u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1388 	readl(dev->base + IER);
1410 	isr = readl(dev->base + ISR);
1463 		txdp = readl(dev->base + TXDP);
1532 	} while (readl(dev->base + CR) & which);
1581 		isr = readl(dev->base + ISR);
1675 		data = readl(dev->base + RFDR);
1709 	val = (readl(rfcr) & and_mask) | or_mask;
1731 		status = readl(dev->base + PTSCR);
1761 	readl(dev->base + MEAR);
1772 	readl(dev->base + MEAR);
1780 	readl(dev->base + MEAR);
1794 	readl(dev->base + MEAR);
1800 	bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
2029 		ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
2048 	dev->CFG_cache = readl(dev->base + CFG);
2084 		writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2087 		writel(readl(dev->base + TANAR)
2113 	if (readl(dev->base + SRR))
2114 		writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2206 		(unsigned)readl(dev->base + SRR) >> 8,
2207 		(unsigned)readl(dev->base + SRR) & 0xff,