550 	void __iomem *ioaddr;  member
599 static int eeprom_read(void __iomem *ioaddr, int location);
705 	return np->ioaddr;  in ns_ioaddr()
723 	void __iomem *ioaddr = ns_ioaddr(dev);  in move_int_phy()  local
740 	writew(target, ioaddr + PhyCtrl);  in move_int_phy()
741 	readw(ioaddr + PhyCtrl);  in move_int_phy()
808 	void __iomem *ioaddr;  in natsemi_probe1()  local
850 	ioaddr = ioremap(iostart, iosize);  in natsemi_probe1()
851 	if (!ioaddr) {  in natsemi_probe1()
857 	prev_eedata = eeprom_read(ioaddr, 6);  in natsemi_probe1()
859 		int eedata = eeprom_read(ioaddr, i + 7);  in natsemi_probe1()
866 	np->ioaddr = ioaddr;  in natsemi_probe1()
894 	if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)  in natsemi_probe1()
938 	np->srr = readl(ioaddr + SiliconRev);  in natsemi_probe1()
969 	iounmap(ioaddr);  in natsemi_probe1()
1043 #define mii_delay(ioaddr)  readl(ioaddr + EECtrl)  argument
1048 	void __iomem *ioaddr = ns_ioaddr(dev);  in mii_getbit()  local
1050 	writel(MII_ShiftClk, ioaddr + EECtrl);  in mii_getbit()
1051 	data = readl(ioaddr + EECtrl);  in mii_getbit()
1052 	writel(0, ioaddr + EECtrl);  in mii_getbit()
1053 	mii_delay(ioaddr);  in mii_getbit()
1060 	void __iomem *ioaddr = ns_ioaddr(dev);  in mii_send_bits()  local
1065 		writel(mdio_val, ioaddr + EECtrl);  in mii_send_bits()
1066 		mii_delay(ioaddr);  in mii_send_bits()
1067 		writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);  in mii_send_bits()
1068 		mii_delay(ioaddr);  in mii_send_bits()
1070 	writel(0, ioaddr + EECtrl);  in mii_send_bits()
1071 	mii_delay(ioaddr);  in mii_send_bits()
1116 	void __iomem *ioaddr = ns_ioaddr(dev);  in mdio_read()  local
1123 		return readw(ioaddr+BasicControl+(reg<<2));  in mdio_read()
1131 	void __iomem *ioaddr = ns_ioaddr(dev);  in mdio_write()  local
1135 		writew(data, ioaddr+BasicControl+(reg<<2));  in mdio_write()
1143 	void __iomem *ioaddr = ns_ioaddr(dev);  in init_phy_fixup()  local
1175 	readl(ioaddr + ChipConfig);  in init_phy_fixup()
1197 	cfg = readl(ioaddr + ChipConfig);  in init_phy_fixup()
1215 		writew(1, ioaddr + PGSEL);  in init_phy_fixup()
1216 		writew(PMDCSR_VAL, ioaddr + PMDCSR);  in init_phy_fixup()
1217 		writew(TSTDAT_VAL, ioaddr + TSTDAT);  in init_phy_fixup()
1219 			DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));  in init_phy_fixup()
1220 		writew(np->dspcfg, ioaddr + DSPCFG);  in init_phy_fixup()
1221 		writew(SDCFG_VAL, ioaddr + SDCFG);  in init_phy_fixup()
1222 		writew(0, ioaddr + PGSEL);  in init_phy_fixup()
1223 		readl(ioaddr + ChipConfig);  in init_phy_fixup()
1226 		writew(1, ioaddr + PGSEL);  in init_phy_fixup()
1227 		dspcfg = readw(ioaddr + DSPCFG);  in init_phy_fixup()
1228 		writew(0, ioaddr + PGSEL);  in init_phy_fixup()
1249 	readw(ioaddr + MIntrStatus);  in init_phy_fixup()
1250 	writew(MICRIntEn, ioaddr + MIntrCtrl);  in init_phy_fixup()
1256 	void __iomem *ioaddr = ns_ioaddr(dev);  in switch_port_external()  local
1259 	cfg = readl(ioaddr + ChipConfig);  in switch_port_external()
1269 	writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);  in switch_port_external()
1270 	readl(ioaddr + ChipConfig);  in switch_port_external()
1289 	void __iomem *ioaddr = ns_ioaddr(dev);  in switch_port_internal()  local
1294 	cfg = readl(ioaddr + ChipConfig);  in switch_port_internal()
1304 	writel(cfg, ioaddr + ChipConfig);  in switch_port_internal()
1305 	readl(ioaddr + ChipConfig);  in switch_port_internal()
1309 	bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));  in switch_port_internal()
1310 	writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));  in switch_port_internal()
1311 	readl(ioaddr + ChipConfig);  in switch_port_internal()
1314 		bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));  in switch_port_internal()
1390 	void __iomem *ioaddr = ns_ioaddr(dev);  in natsemi_reset()  local
1401 	cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;  in natsemi_reset()
1403 	wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;  in natsemi_reset()
1405 	rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;  in natsemi_reset()
1408 		writel(i*2, ioaddr + RxFilterAddr);  in natsemi_reset()
1409 		pmatch[i] = readw(ioaddr + RxFilterData);  in natsemi_reset()
1413 		writel(0xa+(i*2), ioaddr + RxFilterAddr);  in natsemi_reset()
1414 		sopass[i] = readw(ioaddr + RxFilterData);  in natsemi_reset()
1418 	writel(ChipReset, ioaddr + ChipCmd);  in natsemi_reset()
1420 		if (!(readl(ioaddr + ChipCmd) & ChipReset))  in natsemi_reset()
1433 	cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;  in natsemi_reset()
1439 	writel(cfg, ioaddr + ChipConfig);  in natsemi_reset()
1441 	wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;  in natsemi_reset()
1442 	writel(wcsr, ioaddr + WOLCmd);  in natsemi_reset()
1444 	rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;  in natsemi_reset()
1447 		writel(i*2, ioaddr + RxFilterAddr);  in natsemi_reset()
1448 		writew(pmatch[i], ioaddr + RxFilterData);  in natsemi_reset()
1451 		writel(0xa+(i*2), ioaddr + RxFilterAddr);  in natsemi_reset()
1452 		writew(sopass[i], ioaddr + RxFilterData);  in natsemi_reset()
1455 	writel(rfcr, ioaddr + RxFilterAddr);  in natsemi_reset()
1462 	void __iomem *ioaddr = ns_ioaddr(dev);  in reset_rx()  local
1466 	writel(RxReset, ioaddr + ChipCmd);  in reset_rx()
1469 		np->intr_status |= readl(ioaddr + IntrStatus);  in reset_rx()
1486 	void __iomem *ioaddr = ns_ioaddr(dev);  in natsemi_reload_eeprom()  local
1489 	writel(EepromReload, ioaddr + PCIBusCfg);  in natsemi_reload_eeprom()
1492 		if (!(readl(ioaddr + PCIBusCfg) & EepromReload))  in natsemi_reload_eeprom()
1506 	void __iomem * ioaddr = ns_ioaddr(dev);  in natsemi_stop_rxtx()  local
1510 	writel(RxOff | TxOff, ioaddr + ChipCmd);  in natsemi_stop_rxtx()
1512 		if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)  in natsemi_stop_rxtx()
1528 	void __iomem * ioaddr = ns_ioaddr(dev);  in netdev_open()  local
1555 		writel(i*2, ioaddr + RxFilterAddr);  in netdev_open()
1556 		writew(mac, ioaddr + RxFilterData);  in netdev_open()
1558 	writel(np->cur_rx_mode, ioaddr + RxFilterAddr);  in netdev_open()
1565 			dev->name, (int)readl(ioaddr + ChipCmd));  in netdev_open()
1580 	void __iomem *ioaddr = ns_ioaddr(dev);  in do_cable_magic()  local
1594 	if (readl(ioaddr + ChipConfig) & CfgSpeed100) {  in do_cable_magic()
1597 		writew(1, ioaddr + PGSEL);  in do_cable_magic()
1602 		data = readw(ioaddr + TSTDAT) & 0xff;  in do_cable_magic()
1611 			writew(TSTDAT_FIXED, ioaddr + TSTDAT);  in do_cable_magic()
1613 			data = readw(ioaddr + DSPCFG);  in do_cable_magic()
1615 			writew(np->dspcfg, ioaddr + DSPCFG);  in do_cable_magic()
1617 		writew(0, ioaddr + PGSEL);  in do_cable_magic()
1625 	void __iomem * ioaddr = ns_ioaddr(dev);  in undo_cable_magic()  local
1633 	writew(1, ioaddr + PGSEL);  in undo_cable_magic()
1635 	data = readw(ioaddr + DSPCFG);  in undo_cable_magic()
1637 	writew(np->dspcfg, ioaddr + DSPCFG);  in undo_cable_magic()
1638 	writew(0, ioaddr + PGSEL);  in undo_cable_magic()
1644 	void __iomem * ioaddr = ns_ioaddr(dev);  in check_link()  local
1702 		writel(np->tx_config, ioaddr + TxConfig);  in check_link()
1703 		writel(np->rx_config, ioaddr + RxConfig);  in check_link()
1710 	void __iomem * ioaddr = ns_ioaddr(dev);  in init_registers()  local
1715 	readl(ioaddr + IntrStatus);  in init_registers()
1717 	writel(np->ring_dma, ioaddr + RxRingPtr);  in init_registers()
1719 		ioaddr + TxRingPtr);  in init_registers()
1737 	writel(np->tx_config, ioaddr + TxConfig);  in init_registers()
1747 	writel(np->rx_config, ioaddr + RxConfig);  in init_registers()
1755 	np->SavedClkRun = readl(ioaddr + ClkRun);  in init_registers()
1756 	writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);  in init_registers()
1759 			dev->name, readl(ioaddr + WOLCmd));  in init_registers()
1766 	writel(DEFAULT_INTR, ioaddr + IntrMask);  in init_registers()
1769 	writel(RxOn | TxOn, ioaddr + ChipCmd);  in init_registers()
1770 	writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */  in init_registers()
1790 	void __iomem * ioaddr = ns_ioaddr(dev);  in netdev_timer()  local
1807 		writew(1, ioaddr+PGSEL);  in netdev_timer()
1808 		dspcfg = readw(ioaddr+DSPCFG);  in netdev_timer()
1809 		writew(0, ioaddr+PGSEL);  in netdev_timer()
1845 			writel(RxOn, ioaddr + ChipCmd);  in netdev_timer()
1883 	void __iomem * ioaddr = ns_ioaddr(dev);  in ns_tx_timeout()  local
1893 				dev->name, readl(ioaddr + IntrStatus));  in ns_tx_timeout()
2089 	void __iomem * ioaddr = ns_ioaddr(dev);  in start_tx()  local
2125 		writel(TxOn, ioaddr + ChipCmd);  in start_tx()
2188 	void __iomem * ioaddr = ns_ioaddr(dev);  in intr_handler()  local
2193 	if (np->hands_off || !readl(ioaddr + IntrEnable))  in intr_handler()
2196 	np->intr_status = readl(ioaddr + IntrStatus);  in intr_handler()
2205 		       readl(ioaddr + IntrMask));  in intr_handler()
2217 		       readl(ioaddr + IntrMask));  in intr_handler()
2229 	void __iomem * ioaddr = ns_ioaddr(dev);  in natsemi_poll()  local
2237 			       readl(ioaddr + IntrMask));  in natsemi_poll()
2261 		np->intr_status = readl(ioaddr + IntrStatus);  in natsemi_poll()
2285 	void __iomem * ioaddr = ns_ioaddr(dev);  in netdev_rx()  local
2324 				writel(np->ring_dma, ioaddr + RxRingPtr);  in netdev_rx()
2391 		writel(RxOn, ioaddr + ChipCmd);  in netdev_rx()
2397 	void __iomem * ioaddr = ns_ioaddr(dev);  in netdev_error()  local
2411 		readw(ioaddr + MIntrStatus);  in netdev_error()
2430 		writel(np->tx_config, ioaddr + TxConfig);  in netdev_error()
2433 		int wol_status = readl(ioaddr + WOLCmd);  in netdev_error()
2459 	void __iomem * ioaddr = ns_ioaddr(dev);  in __get_stats()  local
2462 	dev->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);  in __get_stats()
2463 	dev->stats.rx_missed_errors += readl(ioaddr + RxMissed);  in __get_stats()
2494 	void __iomem * ioaddr = ns_ioaddr(dev);  in __set_rx_mode()  local
2518 			writel(HASH_TABLE + i, ioaddr + RxFilterAddr);  in __set_rx_mode()
2520 			       ioaddr + RxFilterData);  in __set_rx_mode()
2523 	writel(rx_mode, ioaddr + RxFilterAddr);  in __set_rx_mode()
2537 		void __iomem * ioaddr = ns_ioaddr(dev);  in natsemi_change_mtu()  local
2549 		writel(np->ring_dma, ioaddr + RxRingPtr);  in natsemi_change_mtu()
2551 		writel(RxOn | TxOn, ioaddr + ChipCmd);  in natsemi_change_mtu()
2706 	void __iomem * ioaddr = ns_ioaddr(dev);  in netdev_set_wol()  local
2707 	u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;  in netdev_set_wol()
2728 	writel(data, ioaddr + WOLCmd);  in netdev_set_wol()
2736 	void __iomem * ioaddr = ns_ioaddr(dev);  in netdev_get_wol()  local
2737 	u32 regval = readl(ioaddr + WOLCmd);  in netdev_get_wol()
2772 	void __iomem * ioaddr = ns_ioaddr(dev);  in netdev_set_sopass()  local
2781 	addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;  in netdev_set_sopass()
2783 	writel(addr, ioaddr + RxFilterAddr);  in netdev_set_sopass()
2786 	writel(addr | 0xa, ioaddr + RxFilterAddr);  in netdev_set_sopass()
2787 	writew(sval[0], ioaddr + RxFilterData);  in netdev_set_sopass()
2789 	writel(addr | 0xc, ioaddr + RxFilterAddr);  in netdev_set_sopass()
2790 	writew(sval[1], ioaddr + RxFilterData);  in netdev_set_sopass()
2792 	writel(addr | 0xe, ioaddr + RxFilterAddr);  in netdev_set_sopass()
2793 	writew(sval[2], ioaddr + RxFilterData);  in netdev_set_sopass()
2796 	writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);  in netdev_set_sopass()
2804 	void __iomem * ioaddr = ns_ioaddr(dev);  in netdev_get_sopass()  local
2814 	addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;  in netdev_get_sopass()
2816 	writel(addr | 0xa, ioaddr + RxFilterAddr);  in netdev_get_sopass()
2817 	sval[0] = readw(ioaddr + RxFilterData);  in netdev_get_sopass()
2819 	writel(addr | 0xc, ioaddr + RxFilterAddr);  in netdev_get_sopass()
2820 	sval[1] = readw(ioaddr + RxFilterData);  in netdev_get_sopass()
2822 	writel(addr | 0xe, ioaddr + RxFilterAddr);  in netdev_get_sopass()
2823 	sval[2] = readw(ioaddr + RxFilterData);  in netdev_get_sopass()
2825 	writel(addr, ioaddr + RxFilterAddr);  in netdev_get_sopass()
2998 	void __iomem * ioaddr = ns_ioaddr(dev);  in netdev_get_regs()  local
3002 		rbuf[i] = readl(ioaddr + i*4);  in netdev_get_regs()
3010 	writew(1, ioaddr + PGSEL);  in netdev_get_regs()
3011 	rbuf[i++] = readw(ioaddr + PMDCSR);  in netdev_get_regs()
3012 	rbuf[i++] = readw(ioaddr + TSTDAT);  in netdev_get_regs()
3013 	rbuf[i++] = readw(ioaddr + DSPCFG);  in netdev_get_regs()
3014 	rbuf[i++] = readw(ioaddr + SDCFG);  in netdev_get_regs()
3015 	writew(0, ioaddr + PGSEL);  in netdev_get_regs()
3018 	rfcr = readl(ioaddr + RxFilterAddr);  in netdev_get_regs()
3020 		writel(j*2, ioaddr + RxFilterAddr);  in netdev_get_regs()
3021 		rbuf[i++] = readw(ioaddr + RxFilterData);  in netdev_get_regs()
3023 	writel(rfcr, ioaddr + RxFilterAddr);  in netdev_get_regs()
3048 	void __iomem * ioaddr = ns_ioaddr(dev);  in netdev_get_eeprom()  local
3053 		ebuf[i] = eeprom_read(ioaddr, i);  in netdev_get_eeprom()
3116 	void __iomem * ioaddr = ns_ioaddr(dev);  in enable_wol_mode()  local
3127 	writel(0, ioaddr + RxRingPtr);  in enable_wol_mode()
3130 	readl(ioaddr + WOLCmd);  in enable_wol_mode()
3133 	writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);  in enable_wol_mode()
3136 	writel(RxOn, ioaddr + ChipCmd);  in enable_wol_mode()
3142 		writel(WOLPkt | LinkChange, ioaddr + IntrMask);  in enable_wol_mode()
3149 	void __iomem * ioaddr = ns_ioaddr(dev);  in netdev_close()  local
3156 			dev->name, (int)readl(ioaddr + ChipCmd));  in netdev_close()
3188 	readl(ioaddr + IntrMask);  in netdev_close()
3189 	readw(ioaddr + MIntrStatus);  in netdev_close()
3192 	writel(StatsFreeze, ioaddr + StatsCtrl);  in netdev_close()
3209 		u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;  in netdev_close()
3217 			writel(np->SavedClkRun, ioaddr + ClkRun);  in netdev_close()
3227 	void __iomem * ioaddr = ns_ioaddr(dev);  in natsemi_remove1()  local
3232 	iounmap(ioaddr);  in natsemi_remove1()
3268 	void __iomem * ioaddr = ns_ioaddr(dev);  in natsemi_suspend()  local
3295 			u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;  in natsemi_suspend()
3305 				writel(np->SavedClkRun, ioaddr + ClkRun);  in natsemi_suspend()