Lines Matching refs:BIT
120 #define RPKT_FINISH BIT(0) /* DMA data received */
121 #define NORXBUF BIT(1) /* receive buffer unavailable */
122 #define XPKT_FINISH BIT(2) /* DMA moved data to TX FIFO */
123 #define NOTXBUF BIT(3) /* transmit buffer unavailable */
124 #define XPKT_OK_INT_STS BIT(4) /* transmit to ethernet success */
125 #define XPKT_LOST_INT_STS BIT(5) /* transmit ethernet lost (collision) */
126 #define RPKT_SAV BIT(6) /* FIFO receive success */
127 #define RPKT_LOST_INT_STS BIT(7) /* FIFO full, receive failed */
128 #define AHB_ERR BIT(8) /* AHB error */
129 #define PHYSTS_CHG BIT(9) /* PHY link status change */
132 #define RPKT_FINISH_M BIT(0)
133 #define NORXBUF_M BIT(1)
134 #define XPKT_FINISH_M BIT(2)
135 #define NOTXBUF_M BIT(3)
136 #define XPKT_OK_M BIT(4)
137 #define XPKT_LOST_M BIT(5)
138 #define RPKT_SAV_M BIT(6)
139 #define RPKT_LOST_M BIT(7)
140 #define AHB_ERR_M BIT(8)
141 #define PHYSTS_CHG_M BIT(9)
147 #define TXINT_TIME_SEL BIT(15) /* TX cycle time period */
150 #define RXINT_TIME_SEL BIT(7) /* RX cycle time period */
155 #define TXPOLL_TIME_SEL BIT(12) /* TX poll time period */
158 #define RXPOLL_TIME_SEL BIT(4) /* RX poll time period */
163 #define RX_THR_EN BIT(9) /* RX FIFO threshold arbitration */
166 #define INCR16_EN BIT(2) /* AHB bus INCR16 burst command */
167 #define INCR8_EN BIT(1) /* AHB bus INCR8 burst command */
168 #define INCR4_EN BIT(0) /* AHB bus INCR4 burst command */
171 #define RX_BROADPKT BIT(17) /* receive broadcast packets */
172 #define RX_MULTIPKT BIT(16) /* receive all multicast packets */
173 #define FULLDUP BIT(15) /* full duplex */
174 #define CRC_APD BIT(14) /* append CRC to transmitted packet */
175 #define RCV_ALL BIT(12) /* ignore incoming packet destination */
176 #define RX_FTL BIT(11) /* accept packets larger than 1518 B */
177 #define RX_RUNT BIT(10) /* accept packets smaller than 64 B */
178 #define HT_MULTI_EN BIT(9) /* accept on hash and mcast pass */
179 #define RCV_EN BIT(8) /* receiver enable */
180 #define ENRX_IN_HALFTX BIT(6) /* enable receive in half duplex mode */
181 #define XMT_EN BIT(5) /* transmit enable */
182 #define CRC_DIS BIT(4) /* disable CRC check when receiving */
183 #define LOOP_EN BIT(3) /* internal loop-back */
184 #define SW_RST BIT(2) /* software reset, last 64 AHB clocks */
185 #define RDMA_EN BIT(1) /* enable receive DMA chan */
186 #define XDMA_EN BIT(0) /* enable transmit DMA chan */
189 #define COL_EXCEED BIT(11) /* more than 16 collisions */
190 #define LATE_COL BIT(10) /* transmit late collision detected */
191 #define XPKT_LOST BIT(9) /* transmit to ethernet lost */
192 #define XPKT_OK BIT(8) /* transmit to ethernet success */
193 #define RUNT_MAC_STS BIT(7) /* receive runt detected */
194 #define FTL_MAC_STS BIT(6) /* receive frame too long detected */
195 #define CRC_ERR_MAC_STS BIT(5)
196 #define RPKT_LOST BIT(4) /* RX FIFO full, receive failed */
197 #define RPKT_SAVE BIT(3) /* RX FIFO receive success */
198 #define COL BIT(2) /* collision, incoming packet dropped */
199 #define MCPU_BROADCAST BIT(1)
200 #define MCPU_MULTICAST BIT(0)
203 #define MIIWR BIT(27) /* init write sequence (auto cleared)*/
204 #define MIIRD BIT(26)
216 #define RX_PAUSE BIT(4) /* receive pause frame */
217 #define TX_PAUSED BIT(3) /* transmit pause due to receive */
218 #define FCTHR_EN BIT(2) /* enable threshold mode. */
219 #define TX_PAUSE BIT(1) /* transmit pause frame */
220 #define FC_EN BIT(0) /* flow control mode enable */
225 #define BACKP_MODE BIT(1) /* address mode */
226 #define BACKP_ENABLE BIT(0)
232 #define TX_DMA_REQUEST BIT(31)
233 #define RX_DMA_REQUEST BIT(30)
234 #define TX_DMA_GRANT BIT(29)
235 #define RX_DMA_GRANT BIT(28)
236 #define TX_FIFO_EMPTY BIT(27)
237 #define RX_FIFO_EMPTY BIT(26)
244 #define SINGLE_PKT BIT(26) /* single packet mode */
245 #define PTIMER_TEST BIT(25) /* automatic polling timer test mode */
246 #define ITIMER_TEST BIT(24) /* interrupt timer test mode */
247 #define TEST_SEED_SELECT BIT(22)
248 #define SEED_SELECT BIT(21)
249 #define TEST_MODE BIT(20)