376 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_sdq_init()  argument
386 	mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);  in mlxsw_pci_sdq_init()
387 	mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 7);  in mlxsw_pci_sdq_init()
388 	mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */  in mlxsw_pci_sdq_init()
392 		mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);  in mlxsw_pci_sdq_init()
395 	err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);  in mlxsw_pci_sdq_init()
498 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_rdq_init()  argument
512 	mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);  in mlxsw_pci_rdq_init()
513 	mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */  in mlxsw_pci_rdq_init()
517 		mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);  in mlxsw_pci_rdq_init()
520 	err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);  in mlxsw_pci_rdq_init()
582 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_cq_init()  argument
596 	mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox, 0); /* CQE ver 0 */  in mlxsw_pci_cq_init()
597 	mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);  in mlxsw_pci_cq_init()
598 	mlxsw_cmd_mbox_sw2hw_cq_oi_set(mbox, 0);  in mlxsw_pci_cq_init()
599 	mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);  in mlxsw_pci_cq_init()
600 	mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));  in mlxsw_pci_cq_init()
604 		mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);  in mlxsw_pci_cq_init()
606 	err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);  in mlxsw_pci_cq_init()
759 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_eq_init()  argument
773 	mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */  in mlxsw_pci_eq_init()
774 	mlxsw_cmd_mbox_sw2hw_eq_oi_set(mbox, 0);  in mlxsw_pci_eq_init()
775 	mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */  in mlxsw_pci_eq_init()
776 	mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));  in mlxsw_pci_eq_init()
780 		mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);  in mlxsw_pci_eq_init()
782 	err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);  in mlxsw_pci_eq_init()
882 	int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
930 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_queue_init()  argument
973 	mlxsw_cmd_mbox_zero(mbox);  in mlxsw_pci_queue_init()
974 	err = q_ops->init(mlxsw_pci, mbox, q);  in mlxsw_pci_queue_init()
999 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_queue_group_init()  argument
1015 		err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,  in mlxsw_pci_queue_group_init()
1047 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)  in mlxsw_pci_aqs_init()  argument
1060 	mlxsw_cmd_mbox_zero(mbox);  in mlxsw_pci_aqs_init()
1061 	err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);  in mlxsw_pci_aqs_init()
1065 	num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);  in mlxsw_pci_aqs_init()
1066 	sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);  in mlxsw_pci_aqs_init()
1067 	num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);  in mlxsw_pci_aqs_init()
1068 	rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);  in mlxsw_pci_aqs_init()
1069 	num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);  in mlxsw_pci_aqs_init()
1070 	cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);  in mlxsw_pci_aqs_init()
1071 	num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);  in mlxsw_pci_aqs_init()
1072 	eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);  in mlxsw_pci_aqs_init()
1088 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,  in mlxsw_pci_aqs_init()
1095 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,  in mlxsw_pci_aqs_init()
1102 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,  in mlxsw_pci_aqs_init()
1109 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,  in mlxsw_pci_aqs_init()
1140 				     char *mbox, int index,  in mlxsw_pci_config_profile_swid_config()  argument
1147 			mbox, index, swid->type);  in mlxsw_pci_config_profile_swid_config()
1152 			mbox, index, swid->properties);  in mlxsw_pci_config_profile_swid_config()
1155 	mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);  in mlxsw_pci_config_profile_swid_config()
1158 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_config_profile()  argument
1163 	mlxsw_cmd_mbox_zero(mbox);  in mlxsw_pci_config_profile()
1167 			mbox, 1);  in mlxsw_pci_config_profile()
1169 			mbox, profile->max_vepa_channels);  in mlxsw_pci_config_profile()
1173 			mbox, 1);  in mlxsw_pci_config_profile()
1175 			mbox, profile->max_lag);  in mlxsw_pci_config_profile()
1179 			mbox, 1);  in mlxsw_pci_config_profile()
1181 			mbox, profile->max_port_per_lag);  in mlxsw_pci_config_profile()
1185 			mbox, 1);  in mlxsw_pci_config_profile()
1187 			mbox, profile->max_mid);  in mlxsw_pci_config_profile()
1191 			mbox, 1);  in mlxsw_pci_config_profile()
1193 			mbox, profile->max_pgt);  in mlxsw_pci_config_profile()
1197 			mbox, 1);  in mlxsw_pci_config_profile()
1199 			mbox, profile->max_system_port);  in mlxsw_pci_config_profile()
1203 			mbox, 1);  in mlxsw_pci_config_profile()
1205 			mbox, profile->max_vlan_groups);  in mlxsw_pci_config_profile()
1209 			mbox, 1);  in mlxsw_pci_config_profile()
1211 			mbox, profile->max_regions);  in mlxsw_pci_config_profile()
1215 			mbox, 1);  in mlxsw_pci_config_profile()
1217 			mbox, profile->max_flood_tables);  in mlxsw_pci_config_profile()
1219 			mbox, profile->max_vid_flood_tables);  in mlxsw_pci_config_profile()
1221 			mbox, profile->max_fid_offset_flood_tables);  in mlxsw_pci_config_profile()
1223 			mbox, profile->fid_offset_flood_table_size);  in mlxsw_pci_config_profile()
1225 			mbox, profile->max_fid_flood_tables);  in mlxsw_pci_config_profile()
1227 			mbox, profile->fid_flood_table_size);  in mlxsw_pci_config_profile()
1231 			mbox, 1);  in mlxsw_pci_config_profile()
1233 			mbox, profile->flood_mode);  in mlxsw_pci_config_profile()
1237 			mbox, 1);  in mlxsw_pci_config_profile()
1239 			mbox, profile->max_ib_mc);  in mlxsw_pci_config_profile()
1243 			mbox, 1);  in mlxsw_pci_config_profile()
1245 			mbox, profile->max_pkey);  in mlxsw_pci_config_profile()
1249 			mbox, 1);  in mlxsw_pci_config_profile()
1251 			mbox, profile->ar_sec);  in mlxsw_pci_config_profile()
1255 			mbox, 1);  in mlxsw_pci_config_profile()
1257 			mbox, profile->adaptive_routing_group_cap);  in mlxsw_pci_config_profile()
1261 		mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,  in mlxsw_pci_config_profile()
1264 	return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);  in mlxsw_pci_config_profile()
1267 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)  in mlxsw_pci_boardinfo()  argument
1272 	mlxsw_cmd_mbox_zero(mbox);  in mlxsw_pci_boardinfo()
1273 	err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);  in mlxsw_pci_boardinfo()
1276 	mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);  in mlxsw_pci_boardinfo()
1277 	mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);  in mlxsw_pci_boardinfo()
1281 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_fw_area_init()  argument
1295 	mlxsw_cmd_mbox_zero(mbox);  in mlxsw_pci_fw_area_init()
1307 		mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);  in mlxsw_pci_fw_area_init()
1308 		mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */  in mlxsw_pci_fw_area_init()
1310 			err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);  in mlxsw_pci_fw_area_init()
1314 			mlxsw_cmd_mbox_zero(mbox);  in mlxsw_pci_fw_area_init()
1319 		err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);  in mlxsw_pci_fw_area_init()
1368 				struct mlxsw_pci_mem_item *mbox)  in mlxsw_pci_mbox_alloc()  argument
1373 	mbox->size = MLXSW_CMD_MBOX_SIZE;  in mlxsw_pci_mbox_alloc()
1374 	mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE,  in mlxsw_pci_mbox_alloc()
1375 					 &mbox->mapaddr);  in mlxsw_pci_mbox_alloc()
1376 	if (!mbox->buf) {  in mlxsw_pci_mbox_alloc()
1385 				struct mlxsw_pci_mem_item *mbox)  in mlxsw_pci_mbox_free()  argument
1389 	pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf,  in mlxsw_pci_mbox_free()
1390 			    mbox->mapaddr);  in mlxsw_pci_mbox_free()
1398 	char *mbox;  in mlxsw_pci_init()  local
1407 	mbox = mlxsw_cmd_mbox_alloc();  in mlxsw_pci_init()
1408 	if (!mbox)  in mlxsw_pci_init()
1419 	err = mlxsw_cmd_query_fw(mlxsw_core, mbox);  in mlxsw_pci_init()
1424 		mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);  in mlxsw_pci_init()
1426 		mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);  in mlxsw_pci_init()
1428 		mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);  in mlxsw_pci_init()
1430 	if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {  in mlxsw_pci_init()
1435 	if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {  in mlxsw_pci_init()
1442 		mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);  in mlxsw_pci_init()
1444 	num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);  in mlxsw_pci_init()
1445 	err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);  in mlxsw_pci_init()
1449 	err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);  in mlxsw_pci_init()
1453 	err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile);  in mlxsw_pci_init()
1457 	err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);  in mlxsw_pci_init()
1485 	mlxsw_cmd_mbox_free(mbox);  in mlxsw_pci_init()