981 		err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);  in mlx4_QUERY_DEV_CAP()
1032 		 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,  in mlx4_dev_cap_dump()
1033 		 dev_cap->port_cap[1].max_port_width);  in mlx4_dev_cap_dump()
1058 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap)  in mlx4_QUERY_PORT()  argument
1080 		port_cap->max_vl	   = field >> 4;  in mlx4_QUERY_PORT()
1082 		port_cap->ib_mtu	   = field >> 4;  in mlx4_QUERY_PORT()
1083 		port_cap->max_port_width = field & 0xf;  in mlx4_QUERY_PORT()
1085 		port_cap->max_gids	   = 1 << (field & 0xf);  in mlx4_QUERY_PORT()
1087 		port_cap->max_pkeys	   = 1 << (field & 0xf);  in mlx4_QUERY_PORT()
1107 		port_cap->supported_port_types = field & 3;  in mlx4_QUERY_PORT()
1108 		port_cap->suggested_type = (field >> 3) & 1;  in mlx4_QUERY_PORT()
1109 		port_cap->default_sense = (field >> 4) & 1;  in mlx4_QUERY_PORT()
1110 		port_cap->dmfs_optimized_state = (field >> 5) & 1;  in mlx4_QUERY_PORT()
1112 		port_cap->ib_mtu	   = field & 0xf;  in mlx4_QUERY_PORT()
1114 		port_cap->max_port_width = field & 0xf;  in mlx4_QUERY_PORT()
1116 		port_cap->max_gids	   = 1 << (field >> 4);  in mlx4_QUERY_PORT()
1117 		port_cap->max_pkeys	   = 1 << (field & 0xf);  in mlx4_QUERY_PORT()
1119 		port_cap->max_vl	   = field & 0xf;  in mlx4_QUERY_PORT()
1121 		port_cap->log_max_macs  = field & 0xf;  in mlx4_QUERY_PORT()
1122 		port_cap->log_max_vlans = field >> 4;  in mlx4_QUERY_PORT()
1123 		MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET);  in mlx4_QUERY_PORT()
1124 		MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET);  in mlx4_QUERY_PORT()
1126 		port_cap->trans_type = field32 >> 24;  in mlx4_QUERY_PORT()
1127 		port_cap->vendor_oui = field32 & 0xffffff;  in mlx4_QUERY_PORT()
1128 		MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET);  in mlx4_QUERY_PORT()
1129 		MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET);  in mlx4_QUERY_PORT()