Lines Matching refs:inbox
171 u32 *inbox; in mlx4_MOD_STAT_CFG() local
182 inbox = mailbox->buf; in mlx4_MOD_STAT_CFG()
184 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); in mlx4_MOD_STAT_CFG()
185 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); in mlx4_MOD_STAT_CFG()
251 struct mlx4_cmd_mailbox *inbox, in mlx4_QUERY_FUNC_CAP_wrapper() argument
1144 struct mlx4_cmd_mailbox *inbox, in mlx4_QUERY_DEV_CAP_wrapper() argument
1262 struct mlx4_cmd_mailbox *inbox, in mlx4_QUERY_PORT_wrapper() argument
1590 struct mlx4_cmd_mailbox *inbox, in mlx4_QUERY_FW_wrapper() argument
1681 __be32 *inbox; in mlx4_INIT_HCA() local
1742 inbox = mailbox->buf; in mlx4_INIT_HCA()
1750 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); in mlx4_INIT_HCA()
1752 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); in mlx4_INIT_HCA()
1757 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); in mlx4_INIT_HCA()
1761 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); in mlx4_INIT_HCA()
1765 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); in mlx4_INIT_HCA()
1769 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); in mlx4_INIT_HCA()
1773 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13); in mlx4_INIT_HCA()
1777 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); in mlx4_INIT_HCA()
1786 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); in mlx4_INIT_HCA()
1799 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | in mlx4_INIT_HCA()
1808 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); in mlx4_INIT_HCA()
1812 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); in mlx4_INIT_HCA()
1813 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); in mlx4_INIT_HCA()
1814 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); in mlx4_INIT_HCA()
1815 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); in mlx4_INIT_HCA()
1816 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); in mlx4_INIT_HCA()
1817 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); in mlx4_INIT_HCA()
1818 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); in mlx4_INIT_HCA()
1819 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); in mlx4_INIT_HCA()
1820 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); in mlx4_INIT_HCA()
1821 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); in mlx4_INIT_HCA()
1822 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); in mlx4_INIT_HCA()
1823 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); in mlx4_INIT_HCA()
1824 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); in mlx4_INIT_HCA()
1829 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= in mlx4_INIT_HCA()
1833 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); in mlx4_INIT_HCA()
1834 MLX4_PUT(inbox, param->log_mc_entry_sz, in mlx4_INIT_HCA()
1836 MLX4_PUT(inbox, param->log_mc_table_sz, in mlx4_INIT_HCA()
1843 MLX4_PUT(inbox, in mlx4_INIT_HCA()
1846 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, in mlx4_INIT_HCA()
1851 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), in mlx4_INIT_HCA()
1853 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, in mlx4_INIT_HCA()
1858 MLX4_PUT(inbox, in mlx4_INIT_HCA()
1863 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); in mlx4_INIT_HCA()
1864 MLX4_PUT(inbox, param->log_mc_entry_sz, in mlx4_INIT_HCA()
1866 MLX4_PUT(inbox, param->log_mc_hash_sz, in mlx4_INIT_HCA()
1868 MLX4_PUT(inbox, param->log_mc_table_sz, in mlx4_INIT_HCA()
1871 MLX4_PUT(inbox, (u8) (1 << 3), in mlx4_INIT_HCA()
1877 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); in mlx4_INIT_HCA()
1878 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); in mlx4_INIT_HCA()
1879 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); in mlx4_INIT_HCA()
1880 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); in mlx4_INIT_HCA()
1881 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); in mlx4_INIT_HCA()
1885 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); in mlx4_INIT_HCA()
1886 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); in mlx4_INIT_HCA()
1891 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); in mlx4_INIT_HCA()
2074 struct mlx4_cmd_mailbox *inbox, in mlx4_INIT_PORT_wrapper() argument
2118 u32 *inbox; in mlx4_INIT_PORT() local
2141 inbox = mailbox->buf; in mlx4_INIT_PORT()
2146 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); in mlx4_INIT_PORT()
2149 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); in mlx4_INIT_PORT()
2151 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); in mlx4_INIT_PORT()
2153 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); in mlx4_INIT_PORT()
2172 struct mlx4_cmd_mailbox *inbox, in mlx4_CLOSE_PORT_wrapper() argument
2688 struct mlx4_cmd_mailbox *inbox, *outbox; in mlx4_ACCESS_REG() local
2692 inbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_ACCESS_REG()
2693 if (IS_ERR(inbox)) in mlx4_ACCESS_REG()
2694 return PTR_ERR(inbox); in mlx4_ACCESS_REG()
2698 mlx4_free_cmd_mailbox(dev, inbox); in mlx4_ACCESS_REG()
2702 inbuf = inbox->buf; in mlx4_ACCESS_REG()
2716 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0, in mlx4_ACCESS_REG()
2732 mlx4_free_cmd_mailbox(dev, inbox); in mlx4_ACCESS_REG()
2764 struct mlx4_cmd_mailbox *inbox, in mlx4_ACCESS_REG_wrapper() argument
2768 struct mlx4_access_reg *inbuf = inbox->buf; in mlx4_ACCESS_REG_wrapper()
2785 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier, in mlx4_ACCESS_REG_wrapper()