401 		if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||  in mlx4_QUERY_FUNC_CAP_wrapper()
730 	dev_cap->flags2 = 0;  in mlx4_QUERY_DEV_CAP()
784 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;  in mlx4_QUERY_DEV_CAP()
786 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;  in mlx4_QUERY_DEV_CAP()
789 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;  in mlx4_QUERY_DEV_CAP()
803 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN;  in mlx4_QUERY_DEV_CAP()
806 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;  in mlx4_QUERY_DEV_CAP()
810 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON;  in mlx4_QUERY_DEV_CAP()
813 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;  in mlx4_QUERY_DEV_CAP()
818 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN;  in mlx4_QUERY_DEV_CAP()
823 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;  in mlx4_QUERY_DEV_CAP()
899 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP;  in mlx4_QUERY_DEV_CAP()
901 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;  in mlx4_QUERY_DEV_CAP()
903 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;  in mlx4_QUERY_DEV_CAP()
905 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;  in mlx4_QUERY_DEV_CAP()
909 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;  in mlx4_QUERY_DEV_CAP()
912 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;  in mlx4_QUERY_DEV_CAP()
914 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS;  in mlx4_QUERY_DEV_CAP()
917 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN;  in mlx4_QUERY_DEV_CAP()
919 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN;  in mlx4_QUERY_DEV_CAP()
925 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;  in mlx4_QUERY_DEV_CAP()
927 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;  in mlx4_QUERY_DEV_CAP()
930 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;  in mlx4_QUERY_DEV_CAP()
933 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;  in mlx4_QUERY_DEV_CAP()
935 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;  in mlx4_QUERY_DEV_CAP()
945 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;  in mlx4_QUERY_DEV_CAP()
957 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT;  in mlx4_QUERY_DEV_CAP()
968 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;  in mlx4_QUERY_DEV_CAP()
970 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB;  in mlx4_QUERY_DEV_CAP()
972 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK;  in mlx4_QUERY_DEV_CAP()
974 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;  in mlx4_QUERY_DEV_CAP()
976 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;  in mlx4_QUERY_DEV_CAP()
978 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;  in mlx4_QUERY_DEV_CAP()
995 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;  in mlx4_QUERY_DEV_CAP()
1046 	if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) {  in mlx4_dev_cap_dump()
1055 	dump_dev_cap_flags2(dev, dev_cap->flags2);  in mlx4_dev_cap_dump()
1764 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos)  in mlx4_INIT_HCA()
1794 	if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&  in mlx4_INIT_HCA()
1795 	    (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {  in mlx4_INIT_HCA()
1807 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)  in mlx4_INIT_HCA()
1889 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {  in mlx4_INIT_HCA()
2305 	if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))  in mlx4_config_dev_retrieval()
2614 	if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))  in mlx4_config_mad_demux()
2838 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&  in set_phv_bit()
2839 	    !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {  in set_phv_bit()