Lines Matching refs:field
199 u8 field; in mlx4_QUERY_FUNC() local
225 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); in mlx4_QUERY_FUNC()
226 func->bus = field & 0xf; in mlx4_QUERY_FUNC()
227 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); in mlx4_QUERY_FUNC()
228 func->device = field & 0xf1; in mlx4_QUERY_FUNC()
229 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); in mlx4_QUERY_FUNC()
230 func->function = field & 0x7; in mlx4_QUERY_FUNC()
231 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); in mlx4_QUERY_FUNC()
232 func->physical_function = field & 0xf; in mlx4_QUERY_FUNC()
237 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); in mlx4_QUERY_FUNC()
238 func->rsvd_uars = field & 0x0f; in mlx4_QUERY_FUNC()
256 u8 field, port; in mlx4_QUERY_FUNC_CAP_wrapper() local
326 field = vhcr->in_modifier - in mlx4_QUERY_FUNC_CAP_wrapper()
328 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
334 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; in mlx4_QUERY_FUNC_CAP_wrapper()
338 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; in mlx4_QUERY_FUNC_CAP_wrapper()
342 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
359 field = QUERY_FUNC_CAP_PHV_BIT; in mlx4_QUERY_FUNC_CAP_wrapper()
360 MLX4_PUT(outbox->buf, field, in mlx4_QUERY_FUNC_CAP_wrapper()
370 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | in mlx4_QUERY_FUNC_CAP_wrapper()
373 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
375 field = min( in mlx4_QUERY_FUNC_CAP_wrapper()
378 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
383 field = 0; /* protected FMR support not available as yet */ in mlx4_QUERY_FUNC_CAP_wrapper()
384 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
451 u8 field, op_modifier; in mlx4_QUERY_FUNC_CAP() local
473 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); in mlx4_QUERY_FUNC_CAP()
474 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { in mlx4_QUERY_FUNC_CAP()
479 func_cap->flags = field; in mlx4_QUERY_FUNC_CAP()
482 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); in mlx4_QUERY_FUNC_CAP()
483 func_cap->num_ports = field; in mlx4_QUERY_FUNC_CAP()
575 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); in mlx4_QUERY_FUNC_CAP()
576 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { in mlx4_QUERY_FUNC_CAP()
583 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); in mlx4_QUERY_FUNC_CAP()
584 func_cap->physical_port = field; in mlx4_QUERY_FUNC_CAP()
613 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); in mlx4_QUERY_FUNC_CAP()
614 func_cap->flags |= (field & QUERY_FUNC_CAP_PHV_BIT); in mlx4_QUERY_FUNC_CAP()
633 u8 field; in mlx4_QUERY_DEV_CAP() local
741 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
742 dev_cap->reserved_qps = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
743 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
744 dev_cap->max_qps = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
745 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); in mlx4_QUERY_DEV_CAP()
746 dev_cap->reserved_srqs = 1 << (field >> 4); in mlx4_QUERY_DEV_CAP()
747 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); in mlx4_QUERY_DEV_CAP()
748 dev_cap->max_srqs = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
749 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
750 dev_cap->max_cq_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
751 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); in mlx4_QUERY_DEV_CAP()
752 dev_cap->reserved_cqs = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
753 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); in mlx4_QUERY_DEV_CAP()
754 dev_cap->max_cqs = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
755 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); in mlx4_QUERY_DEV_CAP()
756 dev_cap->max_mpts = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
757 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); in mlx4_QUERY_DEV_CAP()
758 dev_cap->reserved_eqs = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
759 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); in mlx4_QUERY_DEV_CAP()
760 dev_cap->max_eqs = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
761 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); in mlx4_QUERY_DEV_CAP()
762 dev_cap->reserved_mtts = 1 << (field >> 4); in mlx4_QUERY_DEV_CAP()
763 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
764 dev_cap->max_mrw_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
765 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); in mlx4_QUERY_DEV_CAP()
766 dev_cap->reserved_mrws = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
767 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); in mlx4_QUERY_DEV_CAP()
768 dev_cap->max_mtt_seg = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
771 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
772 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
773 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
774 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
775 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); in mlx4_QUERY_DEV_CAP()
776 field &= 0x1f; in mlx4_QUERY_DEV_CAP()
777 if (!field) in mlx4_QUERY_DEV_CAP()
780 dev_cap->max_gso_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
782 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); in mlx4_QUERY_DEV_CAP()
783 if (field & 0x20) in mlx4_QUERY_DEV_CAP()
785 if (field & 0x10) in mlx4_QUERY_DEV_CAP()
787 field &= 0xf; in mlx4_QUERY_DEV_CAP()
788 if (field) { in mlx4_QUERY_DEV_CAP()
790 dev_cap->max_rss_tbl_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
793 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); in mlx4_QUERY_DEV_CAP()
794 dev_cap->max_rdma_global = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
795 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); in mlx4_QUERY_DEV_CAP()
796 dev_cap->local_ca_ack_delay = field & 0x1f; in mlx4_QUERY_DEV_CAP()
797 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); in mlx4_QUERY_DEV_CAP()
798 dev_cap->num_ports = field & 0xf; in mlx4_QUERY_DEV_CAP()
799 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
800 dev_cap->max_msg_sz = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
801 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); in mlx4_QUERY_DEV_CAP()
802 if (field & 0x10) in mlx4_QUERY_DEV_CAP()
804 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); in mlx4_QUERY_DEV_CAP()
805 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
807 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; in mlx4_QUERY_DEV_CAP()
808 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); in mlx4_QUERY_DEV_CAP()
809 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
811 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); in mlx4_QUERY_DEV_CAP()
812 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
814 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
815 dev_cap->fs_max_num_qp_per_entry = field; in mlx4_QUERY_DEV_CAP()
816 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); in mlx4_QUERY_DEV_CAP()
817 if (field & 0x1) in mlx4_QUERY_DEV_CAP()
821 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); in mlx4_QUERY_DEV_CAP()
822 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
827 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); in mlx4_QUERY_DEV_CAP()
828 dev_cap->reserved_uars = field >> 4; in mlx4_QUERY_DEV_CAP()
829 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
830 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); in mlx4_QUERY_DEV_CAP()
831 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
832 dev_cap->min_page_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
834 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); in mlx4_QUERY_DEV_CAP()
835 if (field & 0x80) { in mlx4_QUERY_DEV_CAP()
836 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
837 dev_cap->bf_reg_size = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
838 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); in mlx4_QUERY_DEV_CAP()
839 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) in mlx4_QUERY_DEV_CAP()
840 field = 3; in mlx4_QUERY_DEV_CAP()
841 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
846 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); in mlx4_QUERY_DEV_CAP()
847 dev_cap->max_sq_sg = field; in mlx4_QUERY_DEV_CAP()
851 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); in mlx4_QUERY_DEV_CAP()
852 dev_cap->max_qp_per_mcg = 1 << field; in mlx4_QUERY_DEV_CAP()
853 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); in mlx4_QUERY_DEV_CAP()
854 dev_cap->reserved_mgms = field & 0xf; in mlx4_QUERY_DEV_CAP()
855 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); in mlx4_QUERY_DEV_CAP()
856 dev_cap->max_mcgs = 1 << field; in mlx4_QUERY_DEV_CAP()
857 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); in mlx4_QUERY_DEV_CAP()
858 dev_cap->reserved_pds = field >> 4; in mlx4_QUERY_DEV_CAP()
859 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); in mlx4_QUERY_DEV_CAP()
860 dev_cap->max_pds = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
861 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); in mlx4_QUERY_DEV_CAP()
862 dev_cap->reserved_xrcds = field >> 4; in mlx4_QUERY_DEV_CAP()
863 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); in mlx4_QUERY_DEV_CAP()
864 dev_cap->max_xrcds = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
887 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
888 dev_cap->max_srq_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
889 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
890 dev_cap->max_qp_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
891 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); in mlx4_QUERY_DEV_CAP()
892 dev_cap->resize_srq = field & 1; in mlx4_QUERY_DEV_CAP()
893 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); in mlx4_QUERY_DEV_CAP()
894 dev_cap->max_rq_sg = field; in mlx4_QUERY_DEV_CAP()
897 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); in mlx4_QUERY_DEV_CAP()
898 if (field & (1 << 4)) in mlx4_QUERY_DEV_CAP()
900 if (field & (1 << 5)) in mlx4_QUERY_DEV_CAP()
902 if (field & (1 << 6)) in mlx4_QUERY_DEV_CAP()
904 if (field & (1 << 7)) in mlx4_QUERY_DEV_CAP()
910 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); in mlx4_QUERY_DEV_CAP()
911 if (field & 0x20) in mlx4_QUERY_DEV_CAP()
913 if (field & (1 << 2)) in mlx4_QUERY_DEV_CAP()
915 MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET); in mlx4_QUERY_DEV_CAP()
916 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
918 if (field & 0x40) in mlx4_QUERY_DEV_CAP()
928 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); in mlx4_QUERY_DEV_CAP()
929 if (field & 1<<6) in mlx4_QUERY_DEV_CAP()
931 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); in mlx4_QUERY_DEV_CAP()
932 if (field & 1<<3) in mlx4_QUERY_DEV_CAP()
934 if (field & (1 << 5)) in mlx4_QUERY_DEV_CAP()
1062 u8 field; in mlx4_QUERY_PORT() local
1079 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); in mlx4_QUERY_PORT()
1080 port_cap->max_vl = field >> 4; in mlx4_QUERY_PORT()
1081 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); in mlx4_QUERY_PORT()
1082 port_cap->ib_mtu = field >> 4; in mlx4_QUERY_PORT()
1083 port_cap->max_port_width = field & 0xf; in mlx4_QUERY_PORT()
1084 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); in mlx4_QUERY_PORT()
1085 port_cap->max_gids = 1 << (field & 0xf); in mlx4_QUERY_PORT()
1086 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); in mlx4_QUERY_PORT()
1087 port_cap->max_pkeys = 1 << (field & 0xf); in mlx4_QUERY_PORT()
1106 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); in mlx4_QUERY_PORT()
1107 port_cap->supported_port_types = field & 3; in mlx4_QUERY_PORT()
1108 port_cap->suggested_type = (field >> 3) & 1; in mlx4_QUERY_PORT()
1109 port_cap->default_sense = (field >> 4) & 1; in mlx4_QUERY_PORT()
1110 port_cap->dmfs_optimized_state = (field >> 5) & 1; in mlx4_QUERY_PORT()
1111 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); in mlx4_QUERY_PORT()
1112 port_cap->ib_mtu = field & 0xf; in mlx4_QUERY_PORT()
1113 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); in mlx4_QUERY_PORT()
1114 port_cap->max_port_width = field & 0xf; in mlx4_QUERY_PORT()
1115 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); in mlx4_QUERY_PORT()
1116 port_cap->max_gids = 1 << (field >> 4); in mlx4_QUERY_PORT()
1117 port_cap->max_pkeys = 1 << (field & 0xf); in mlx4_QUERY_PORT()
1118 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); in mlx4_QUERY_PORT()
1119 port_cap->max_vl = field & 0xf; in mlx4_QUERY_PORT()
1120 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); in mlx4_QUERY_PORT()
1121 port_cap->log_max_macs = field & 0xf; in mlx4_QUERY_PORT()
1122 port_cap->log_max_vlans = field >> 4; in mlx4_QUERY_PORT()
1150 u8 field; in mlx4_QUERY_DEV_CAP_wrapper() local
1187 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1188 field &= ~0x0F; in mlx4_QUERY_DEV_CAP_wrapper()
1189 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; in mlx4_QUERY_DEV_CAP_wrapper()
1190 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1193 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1194 field &= 0x7f; in mlx4_QUERY_DEV_CAP_wrapper()
1195 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1198 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); in mlx4_QUERY_DEV_CAP_wrapper()
1199 field &= 0xd7; in mlx4_QUERY_DEV_CAP_wrapper()
1200 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); in mlx4_QUERY_DEV_CAP_wrapper()
1203 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1204 field &= 0x7f; in mlx4_QUERY_DEV_CAP_wrapper()
1205 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1208 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1209 field &= 0x7f; in mlx4_QUERY_DEV_CAP_wrapper()
1210 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1220 MLX4_GET(field, outbox->buf, in mlx4_QUERY_DEV_CAP_wrapper()
1222 field &= 0x7f; in mlx4_QUERY_DEV_CAP_wrapper()
1223 MLX4_PUT(outbox->buf, field, in mlx4_QUERY_DEV_CAP_wrapper()
1228 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1229 field &= ~0x80; in mlx4_QUERY_DEV_CAP_wrapper()
1230 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1239 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1240 field &= 0xfe; in mlx4_QUERY_DEV_CAP_wrapper()
1241 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1248 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); in mlx4_QUERY_DEV_CAP_wrapper()
1249 field &= 0xef; in mlx4_QUERY_DEV_CAP_wrapper()
1250 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); in mlx4_QUERY_DEV_CAP_wrapper()
1253 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1254 field &= 0xfb; in mlx4_QUERY_DEV_CAP_wrapper()
1255 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1337 u16 field; in mlx4_get_slave_pkey_gid_tbl_len() local
1352 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); in mlx4_get_slave_pkey_gid_tbl_len()
1353 *gid_tbl_len = field; in mlx4_get_slave_pkey_gid_tbl_len()
1355 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); in mlx4_get_slave_pkey_gid_tbl_len()
1356 *pkey_tbl_len = field; in mlx4_get_slave_pkey_gid_tbl_len()
2121 u16 field; in mlx4_INIT_PORT() local
2148 field = 128 << dev->caps.ib_mtu_cap[port]; in mlx4_INIT_PORT()
2149 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); in mlx4_INIT_PORT()
2150 field = dev->caps.gid_table_len[port]; in mlx4_INIT_PORT()
2151 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); in mlx4_INIT_PORT()
2152 field = dev->caps.pkey_table_len[port]; in mlx4_INIT_PORT()
2153 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); in mlx4_INIT_PORT()