Lines Matching refs:caps
327 find_first_bit(actv_ports.ports, dev->caps.num_ports); in mlx4_QUERY_FUNC_CAP_wrapper()
355 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], in mlx4_QUERY_FUNC_CAP_wrapper()
358 if (dev->caps.phv_bit[port]) { in mlx4_QUERY_FUNC_CAP_wrapper()
376 bitmap_weight(actv_ports.ports, dev->caps.num_ports), in mlx4_QUERY_FUNC_CAP_wrapper()
377 dev->caps.num_ports); in mlx4_QUERY_FUNC_CAP_wrapper()
380 size = dev->caps.function_caps; /* set PF behaviours */ in mlx4_QUERY_FUNC_CAP_wrapper()
388 size = dev->caps.num_qps; in mlx4_QUERY_FUNC_CAP_wrapper()
393 size = dev->caps.num_srqs; in mlx4_QUERY_FUNC_CAP_wrapper()
398 size = dev->caps.num_cqs; in mlx4_QUERY_FUNC_CAP_wrapper()
401 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || in mlx4_QUERY_FUNC_CAP_wrapper()
405 dev->caps.num_eqs : in mlx4_QUERY_FUNC_CAP_wrapper()
406 rounddown_pow_of_two(dev->caps.num_eqs); in mlx4_QUERY_FUNC_CAP_wrapper()
408 size = dev->caps.reserved_eqs; in mlx4_QUERY_FUNC_CAP_wrapper()
422 size = dev->caps.num_mpts; in mlx4_QUERY_FUNC_CAP_wrapper()
427 size = dev->caps.num_mtts; in mlx4_QUERY_FUNC_CAP_wrapper()
430 size = dev->caps.num_mgms + dev->caps.num_amgms; in mlx4_QUERY_FUNC_CAP_wrapper()
438 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00); in mlx4_QUERY_FUNC_CAP_wrapper()
556 if (gen_or_port > dev->caps.num_ports) { in mlx4_QUERY_FUNC_CAP()
562 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { in mlx4_QUERY_FUNC_CAP()
574 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { in mlx4_QUERY_FUNC_CAP()
1170 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); in mlx4_QUERY_DEV_CAP_wrapper()
1173 bitmap_weight(actv_ports.ports, dev->caps.num_ports); in mlx4_QUERY_DEV_CAP_wrapper()
1180 for (; slave_port < dev->caps.num_ports; ++slave_port) in mlx4_QUERY_DEV_CAP_wrapper()
1189 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; in mlx4_QUERY_DEV_CAP_wrapper()
1219 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { in mlx4_QUERY_DEV_CAP_wrapper()
1295 if (!err && dev->caps.function != slave) { in mlx4_QUERY_PORT_wrapper()
1306 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); in mlx4_QUERY_PORT_wrapper()
1317 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) in mlx4_QUERY_PORT_wrapper()
1324 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; in mlx4_QUERY_PORT_wrapper()
1508 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | in mlx4_QUERY_FW()
1513 dev->caps.function = lg; in mlx4_QUERY_FW()
1525 (int) (dev->caps.fw_ver >> 32), in mlx4_QUERY_FW()
1526 (int) (dev->caps.fw_ver >> 16) & 0xffff, in mlx4_QUERY_FW()
1527 (int) dev->caps.fw_ver & 0xffff); in mlx4_QUERY_FW()
1541 (int) (dev->caps.fw_ver >> 32), in mlx4_QUERY_FW()
1542 (int) (dev->caps.fw_ver >> 16) & 0xffff, in mlx4_QUERY_FW()
1543 (int) dev->caps.fw_ver & 0xffff, in mlx4_QUERY_FW()
1760 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) in mlx4_INIT_HCA()
1764 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos) in mlx4_INIT_HCA()
1768 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) in mlx4_INIT_HCA()
1772 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG) in mlx4_INIT_HCA()
1776 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { in mlx4_INIT_HCA()
1778 dev->caps.eqe_size = 64; in mlx4_INIT_HCA()
1779 dev->caps.eqe_factor = 1; in mlx4_INIT_HCA()
1781 dev->caps.eqe_size = 32; in mlx4_INIT_HCA()
1782 dev->caps.eqe_factor = 0; in mlx4_INIT_HCA()
1785 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { in mlx4_INIT_HCA()
1787 dev->caps.cqe_size = 64; in mlx4_INIT_HCA()
1788 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; in mlx4_INIT_HCA()
1790 dev->caps.cqe_size = 32; in mlx4_INIT_HCA()
1794 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && in mlx4_INIT_HCA()
1795 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { in mlx4_INIT_HCA()
1796 dev->caps.eqe_size = cache_line_size(); in mlx4_INIT_HCA()
1797 dev->caps.cqe_size = cache_line_size(); in mlx4_INIT_HCA()
1798 dev->caps.eqe_factor = 0; in mlx4_INIT_HCA()
1799 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | in mlx4_INIT_HCA()
1800 (ilog2(dev->caps.eqe_size) - 5)), in mlx4_INIT_HCA()
1804 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; in mlx4_INIT_HCA()
1807 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) in mlx4_INIT_HCA()
1827 if (dev->caps.steering_mode == in mlx4_INIT_HCA()
1841 if (dev->caps.dmfs_high_steer_mode != in mlx4_INIT_HCA()
1856 if (dev->caps.dmfs_high_steer_mode != in mlx4_INIT_HCA()
1859 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] in mlx4_INIT_HCA()
1870 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) in mlx4_INIT_HCA()
1889 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { in mlx4_INIT_HCA()
2051 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); in mlx4_hca_core_clock_update()
2088 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { in mlx4_INIT_PORT_wrapper()
2144 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; in mlx4_INIT_PORT()
2145 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; in mlx4_INIT_PORT()
2148 field = 128 << dev->caps.ib_mtu_cap[port]; in mlx4_INIT_PORT()
2150 field = dev->caps.gid_table_len[port]; in mlx4_INIT_PORT()
2152 field = dev->caps.pkey_table_len[port]; in mlx4_INIT_PORT()
2187 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { in mlx4_CLOSE_PORT_wrapper()
2305 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) in mlx4_config_dev_retrieval()
2426 for (port = 1; port <= dev->caps.num_ports; port++) { in mlx4_get_phys_port_id()
2438 dev->caps.phys_port_id[port] = (u64)guid_lo | in mlx4_get_phys_port_id()
2518 if (dev->caps.steering_mode == in mlx4_opreq_action()
2614 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) in mlx4_config_mad_demux()
2838 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN && in set_phv_bit()
2839 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) { in set_phv_bit()
2842 dev->caps.phv_bit[port] = new_val; in set_phv_bit()
2856 for (i = 1; i <= dev->caps.num_ports; ++i) in mlx4_replace_zero_macs()
2857 if (!dev->caps.def_mac[i] && in mlx4_replace_zero_macs()
2858 dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) { in mlx4_replace_zero_macs()
2861 dev->caps.def_mac[i] = mlx4_mac_to_u64(mac_addr); in mlx4_replace_zero_macs()