Lines Matching refs:mfunc
257 u32 status = readl(&priv->mfunc.comm->slave_read); in comm_pending()
282 &priv->mfunc.comm->slave_write); in mlx4_comm_cmd_post()
522 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr; in mlx4_slave_cmd()
957 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port]; in mlx4_MAD_IFC_wrapper()
1666 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr; in mlx4_master_process_vhcr()
1683 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave, in mlx4_master_process_vhcr()
1684 priv->mfunc.master.slave_state[slave].vhcr_dma, in mlx4_master_process_vhcr()
1812 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave, in mlx4_master_process_vhcr()
1813 priv->mfunc.master.slave_state[slave].vhcr_dma, in mlx4_master_process_vhcr()
1821 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe)) in mlx4_master_process_vhcr()
1843 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_master_immediate_activate_vlan_qos()
1844 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_master_immediate_activate_vlan_qos()
1852 if (!(priv->mfunc.master.slave_state[slave].active && in mlx4_master_immediate_activate_vlan_qos()
1921 queue_work(priv->mfunc.master.comm_wq, &work->work); in mlx4_master_immediate_activate_vlan_qos()
1931 port_qos_ctl = &priv->mfunc.master.qos_ctl[port]; in mlx4_set_default_port_qos()
1954 port_qos = &priv->mfunc.master.qos_ctl[port]; in mlx4_allocate_port_vpps()
1999 priv->mfunc.master.vf_oper[slave].smi_enabled[port] = in mlx4_master_activate_admin_state()
2000 priv->mfunc.master.vf_admin[slave].enable_smi[port]; in mlx4_master_activate_admin_state()
2001 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_master_activate_admin_state()
2002 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_master_activate_admin_state()
2052 priv->mfunc.master.vf_oper[slave].smi_enabled[port] = in mlx4_master_deactivate_admin_state()
2054 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_master_deactivate_admin_state()
2072 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; in mlx4_master_do_cmd()
2119 priv->mfunc.master.slave_state[slave].cookie = 0; in mlx4_master_do_cmd()
2161 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_do_cmd()
2166 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_do_cmd()
2173 &priv->mfunc.comm[slave].slave_read); in mlx4_master_do_cmd()
2192 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_do_cmd()
2195 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_do_cmd()
2201 &priv->mfunc.comm[slave].slave_read); in mlx4_master_do_cmd()
2212 struct mlx4_mfunc *mfunc = in mlx4_master_comm_channel() local
2215 container_of(mfunc, struct mlx4_priv, mfunc); in mlx4_master_comm_channel()
2235 &mfunc->comm[slave].slave_write)); in mlx4_master_comm_channel()
2236 slt = swab32(readl(&mfunc->comm[slave].slave_read)) in mlx4_master_comm_channel()
2271 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)); in sync_toggles()
2278 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)); in sync_toggles()
2282 wr_toggle = swab32(readl(&priv->mfunc.comm-> in sync_toggles()
2302 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read); in sync_toggles()
2303 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write); in sync_toggles()
2316 priv->mfunc.comm = in mlx4_multi_func_init()
2321 priv->mfunc.comm = in mlx4_multi_func_init()
2324 if (!priv->mfunc.comm) { in mlx4_multi_func_init()
2333 priv->mfunc.master.slave_state = in mlx4_multi_func_init()
2336 if (!priv->mfunc.master.slave_state) in mlx4_multi_func_init()
2339 priv->mfunc.master.vf_admin = in mlx4_multi_func_init()
2342 if (!priv->mfunc.master.vf_admin) in mlx4_multi_func_init()
2345 priv->mfunc.master.vf_oper = in mlx4_multi_func_init()
2348 if (!priv->mfunc.master.vf_oper) in mlx4_multi_func_init()
2352 vf_admin = &priv->mfunc.master.vf_admin[i]; in mlx4_multi_func_init()
2353 vf_oper = &priv->mfunc.master.vf_oper[i]; in mlx4_multi_func_init()
2354 s_state = &priv->mfunc.master.slave_state[i]; in mlx4_multi_func_init()
2356 mutex_init(&priv->mfunc.master.gen_eqe_mutex[i]); in mlx4_multi_func_init()
2360 &priv->mfunc.comm[i].slave_write); in mlx4_multi_func_init()
2362 &priv->mfunc.comm[i].slave_read); in mlx4_multi_func_init()
2401 memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe)); in mlx4_multi_func_init()
2402 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD; in mlx4_multi_func_init()
2403 INIT_WORK(&priv->mfunc.master.comm_work, in mlx4_multi_func_init()
2405 INIT_WORK(&priv->mfunc.master.slave_event_work, in mlx4_multi_func_init()
2407 INIT_WORK(&priv->mfunc.master.slave_flr_event_work, in mlx4_multi_func_init()
2409 spin_lock_init(&priv->mfunc.master.slave_state_lock); in mlx4_multi_func_init()
2410 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock); in mlx4_multi_func_init()
2411 priv->mfunc.master.comm_wq = in mlx4_multi_func_init()
2413 if (!priv->mfunc.master.comm_wq) in mlx4_multi_func_init()
2429 flush_workqueue(priv->mfunc.master.comm_wq); in mlx4_multi_func_init()
2430 destroy_workqueue(priv->mfunc.master.comm_wq); in mlx4_multi_func_init()
2434 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]); in mlx4_multi_func_init()
2436 kfree(priv->mfunc.master.vf_oper); in mlx4_multi_func_init()
2438 kfree(priv->mfunc.master.vf_admin); in mlx4_multi_func_init()
2440 kfree(priv->mfunc.master.slave_state); in mlx4_multi_func_init()
2442 iounmap(priv->mfunc.comm); in mlx4_multi_func_init()
2445 priv->mfunc.vhcr, in mlx4_multi_func_init()
2446 priv->mfunc.vhcr_dma); in mlx4_multi_func_init()
2447 priv->mfunc.vhcr = NULL; in mlx4_multi_func_init()
2475 if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) { in mlx4_cmd_init()
2476 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev, in mlx4_cmd_init()
2478 &priv->mfunc.vhcr_dma, in mlx4_cmd_init()
2480 if (!priv->mfunc.vhcr) in mlx4_cmd_init()
2514 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read)); in mlx4_report_internal_err_comm_event()
2517 &priv->mfunc.comm[slave].slave_read); in mlx4_report_internal_err_comm_event()
2531 flush_workqueue(priv->mfunc.master.comm_wq); in mlx4_multi_func_cleanup()
2532 destroy_workqueue(priv->mfunc.master.comm_wq); in mlx4_multi_func_cleanup()
2535 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]); in mlx4_multi_func_cleanup()
2537 kfree(priv->mfunc.master.slave_state); in mlx4_multi_func_cleanup()
2538 kfree(priv->mfunc.master.vf_admin); in mlx4_multi_func_cleanup()
2539 kfree(priv->mfunc.master.vf_oper); in mlx4_multi_func_cleanup()
2543 iounmap(priv->mfunc.comm); in mlx4_multi_func_cleanup()
2560 if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr && in mlx4_cmd_cleanup()
2563 priv->mfunc.vhcr, priv->mfunc.vhcr_dma); in mlx4_cmd_cleanup()
2564 priv->mfunc.vhcr = NULL; in mlx4_cmd_cleanup()
2830 port_qos = &priv->mfunc.master.qos_ctl[port]; in mlx4_set_vport_qos()
2877 info = &priv->mfunc.master.qos_ctl[port]; in mlx4_is_vf_vst_and_prio_qos()
2932 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_mac()
2959 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_vlan()
3007 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_rate()
3040 if (priv->mfunc.master.slave_state[slave].active && in mlx4_set_vf_rate()
3060 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_get_slave_default_vlan()
3088 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_spoofchk()
3108 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_get_vf_config()
3169 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_link_state()
3277 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] == in mlx4_vf_smi_enabled()
3293 return priv->mfunc.master.vf_admin[slave].enable_smi[port] == in mlx4_vf_get_enable_smi_admin()
3322 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled; in mlx4_vf_set_enable_smi_admin()