Lines Matching refs:wrl
292 static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data) in wrl() function
303 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT); in abort_dma()
571 wrl(pep, HTPR, pep->htpr_dma); in init_hash_table()
586 wrl(pep, PORT_CONFIG, val); in pxa168_eth_set_rx_mode()
632 wrl(pep, MAC_ADDR_HIGH, mac_h); in pxa168_eth_set_mac_address()
633 wrl(pep, MAC_ADDR_LOW, mac_l); in pxa168_eth_set_mac_address()
651 wrl(pep, ETH_C_TX_DESC_1, in eth_port_start()
656 wrl(pep, ETH_C_RX_DESC_0, in eth_port_start()
659 wrl(pep, ETH_F_RX_DESC_0, in eth_port_start()
663 wrl(pep, INT_CAUSE, 0); in eth_port_start()
666 wrl(pep, INT_MASK, ALL_INTS); in eth_port_start()
670 wrl(pep, PORT_CONFIG, val); in eth_port_start()
675 wrl(pep, SDMA_CMD, val); in eth_port_start()
684 wrl(pep, INT_MASK, 0); in eth_port_reset()
687 wrl(pep, INT_CAUSE, 0); in eth_port_reset()
701 wrl(pep, PORT_CONFIG, val); in eth_port_reset()
864 wrl(pep, INT_CAUSE, ~icr); in pxa168_eth_collect_events()
882 wrl(pep, INT_MASK, 0); in pxa168_eth_int_handler()
931 wrl(pep, PORT_CONFIG_EXT, in set_port_config_ext()
966 wrl(pep, PORT_CONFIG, cfg); in pxa168_eth_adjust_link()
967 wrl(pep, PORT_CONFIG_EXT, cfgext); in pxa168_eth_adjust_link()
1011 wrl(pep, INT_MASK, 0); in pxa168_init_hw()
1012 wrl(pep, INT_CAUSE, 0); in pxa168_init_hw()
1014 wrl(pep, INT_W_CLEAR, 0); in pxa168_init_hw()
1024 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */ in pxa168_init_hw()
1030 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */ in pxa168_init_hw()
1192 wrl(pep, INT_MASK, 0); in pxa168_eth_stop()
1193 wrl(pep, INT_CAUSE, 0); in pxa168_eth_stop()
1195 wrl(pep, INT_W_CLEAR, 0); in pxa168_eth_stop()
1267 wrl(pep, INT_MASK, ALL_INTS); in pxa168_rx_poll()
1294 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD); in pxa168_eth_start_xmit()
1331 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R); in pxa168_smi_read()
1355 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | in pxa168_smi_write()