Lines Matching refs:port
37 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) argument
38 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) argument
43 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) argument
62 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) argument
63 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) argument
64 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) argument
65 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) argument
66 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
67 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) argument
68 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) argument
69 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
82 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) argument
92 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) argument
95 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) argument
97 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) argument
158 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) argument
161 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) argument
170 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) argument
248 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) argument
255 #define MVPP2_MIB_COUNTERS_BASE(port) (0x1000 + ((port) >> 1) * \ argument
256 0x400 + (port) * 0x400)
609 #define MVPP2_BM_SWF_LONG_POOL(port) ((port > 2) ? 2 : port) argument
860 int port; member
994 static inline int mvpp2_egress_port(struct mvpp2_port *port) in mvpp2_egress_port() argument
996 return MVPP2_MAX_TCONT + port->id; in mvpp2_egress_port()
1000 static inline int mvpp2_txq_phys(int port, int txq) in mvpp2_txq_phys() argument
1002 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; in mvpp2_txq_phys()
1093 unsigned int port, bool add) in mvpp2_prs_tcam_port_set() argument
1098 pe->tcam.byte[enable_off] &= ~(1 << port); in mvpp2_prs_tcam_port_set()
1100 pe->tcam.byte[enable_off] |= 1 << port; in mvpp2_prs_tcam_port_set()
1406 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add) in mvpp2_prs_mac_drop_all_set() argument
1435 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
1441 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add) in mvpp2_prs_mac_promisc_set() argument
1476 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
1482 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index, in mvpp2_prs_mac_multi_set() argument
1525 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_multi_set()
1531 static void mvpp2_prs_dsa_tag_set(struct mvpp2 *priv, int port, bool add, in mvpp2_prs_dsa_tag_set() argument
1584 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_set()
1590 static void mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2 *priv, int port, in mvpp2_prs_dsa_tag_ethertype_set() argument
1653 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_ethertype_set()
2119 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first, in mvpp2_prs_hw_port_init() argument
2126 val &= ~MVPP2_PRS_PORT_LU_MASK(port); in mvpp2_prs_hw_port_init()
2127 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first); in mvpp2_prs_hw_port_init()
2131 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port)); in mvpp2_prs_hw_port_init()
2132 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port); in mvpp2_prs_hw_port_init()
2133 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max); in mvpp2_prs_hw_port_init()
2134 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); in mvpp2_prs_hw_port_init()
2139 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port)); in mvpp2_prs_hw_port_init()
2140 val &= ~MVPP2_PRS_INIT_OFF_MASK(port); in mvpp2_prs_hw_port_init()
2141 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset); in mvpp2_prs_hw_port_init()
2142 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); in mvpp2_prs_hw_port_init()
2149 int port; in mvpp2_prs_def_flow_init() local
2151 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_prs_def_flow_init()
2154 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
2160 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
3029 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port, in mvpp2_prs_mac_da_accept() argument
3038 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, in mvpp2_prs_mac_da_accept()
3073 mvpp2_prs_tcam_port_set(pe, port, add); in mvpp2_prs_mac_da_accept()
3125 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_prs_update_mac_da() local
3129 err = mvpp2_prs_mac_da_accept(port->priv, port->id, dev->dev_addr, in mvpp2_prs_update_mac_da()
3135 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true); in mvpp2_prs_update_mac_da()
3146 static void mvpp2_prs_mcast_del_all(struct mvpp2 *priv, int port) in mvpp2_prs_mcast_del_all() argument
3171 mvpp2_prs_mac_da_accept(priv, port, da, false); in mvpp2_prs_mcast_del_all()
3175 static int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type) in mvpp2_prs_tag_mode_set() argument
3180 mvpp2_prs_dsa_tag_set(priv, port, true, in mvpp2_prs_tag_mode_set()
3182 mvpp2_prs_dsa_tag_set(priv, port, true, in mvpp2_prs_tag_mode_set()
3185 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3187 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3193 mvpp2_prs_dsa_tag_set(priv, port, true, in mvpp2_prs_tag_mode_set()
3195 mvpp2_prs_dsa_tag_set(priv, port, true, in mvpp2_prs_tag_mode_set()
3198 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3200 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3207 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3209 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3211 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3213 mvpp2_prs_dsa_tag_set(priv, port, false, in mvpp2_prs_tag_mode_set()
3226 static int mvpp2_prs_def_flow(struct mvpp2_port *port) in mvpp2_prs_def_flow() argument
3231 pe = mvpp2_prs_flow_find(port->priv, port->id); in mvpp2_prs_def_flow()
3236 tid = mvpp2_prs_tcam_first_free(port->priv, in mvpp2_prs_def_flow()
3250 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
3254 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
3257 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); in mvpp2_prs_def_flow()
3258 mvpp2_prs_hw_write(port->priv, pe); in mvpp2_prs_def_flow()
3316 static void mvpp2_cls_port_config(struct mvpp2_port *port) in mvpp2_cls_port_config() argument
3322 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); in mvpp2_cls_port_config()
3323 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); in mvpp2_cls_port_config()
3324 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); in mvpp2_cls_port_config()
3329 le.lkpid = port->id; in mvpp2_cls_port_config()
3335 le.data |= port->first_rxq; in mvpp2_cls_port_config()
3341 mvpp2_cls_lookup_write(port->priv, &le); in mvpp2_cls_port_config()
3345 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port) in mvpp2_cls_oversize_rxq_set() argument
3349 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), in mvpp2_cls_oversize_rxq_set()
3350 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK); in mvpp2_cls_oversize_rxq_set()
3352 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), in mvpp2_cls_oversize_rxq_set()
3353 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS)); in mvpp2_cls_oversize_rxq_set()
3355 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set()
3356 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); in mvpp2_cls_oversize_rxq_set()
3357 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
3514 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, in mvpp2_rxq_long_pool_set() argument
3521 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_long_pool_set()
3523 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_long_pool_set()
3528 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
3532 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, in mvpp2_rxq_short_pool_set() argument
3539 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_short_pool_set()
3541 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_short_pool_set()
3546 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_short_pool_set()
3550 static struct sk_buff *mvpp2_skb_alloc(struct mvpp2_port *port, in mvpp2_skb_alloc() argument
3562 phys_addr = dma_map_single(port->dev->dev.parent, skb->head, in mvpp2_skb_alloc()
3565 if (unlikely(dma_mapping_error(port->dev->dev.parent, phys_addr))) { in mvpp2_skb_alloc()
3592 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, in mvpp2_bm_pool_put() argument
3595 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr); in mvpp2_bm_pool_put()
3596 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr); in mvpp2_bm_pool_put()
3600 static void mvpp2_bm_pool_mc_put(struct mvpp2_port *port, int pool, in mvpp2_bm_pool_mc_put() argument
3607 mvpp2_write(port->priv, MVPP2_BM_MC_RLS_REG, val); in mvpp2_bm_pool_mc_put()
3609 mvpp2_bm_pool_put(port, pool, in mvpp2_bm_pool_mc_put()
3615 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm, in mvpp2_pool_refill() argument
3620 mvpp2_bm_pool_put(port, pool, phys_addr, cookie); in mvpp2_pool_refill()
3624 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, in mvpp2_bm_bufs_add() argument
3637 netdev_err(port->dev, in mvpp2_bm_bufs_add()
3645 skb = mvpp2_skb_alloc(port, bm_pool, &phys_addr, GFP_KERNEL); in mvpp2_bm_bufs_add()
3649 mvpp2_pool_refill(port, bm, (u32)phys_addr, (u32)skb); in mvpp2_bm_bufs_add()
3656 netdev_dbg(port->dev, in mvpp2_bm_bufs_add()
3661 netdev_dbg(port->dev, in mvpp2_bm_bufs_add()
3672 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, in mvpp2_bm_pool_use() argument
3675 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; in mvpp2_bm_pool_use()
3679 netdev_err(port->dev, "mixing pool types is forbidden\n"); in mvpp2_bm_pool_use()
3702 mvpp2_bm_bufs_free(port->dev->dev.parent, in mvpp2_bm_pool_use()
3703 port->priv, new_pool); in mvpp2_bm_pool_use()
3708 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); in mvpp2_bm_pool_use()
3716 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, in mvpp2_bm_pool_use()
3723 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) in mvpp2_swf_bm_pool_init() argument
3727 if (!port->pool_long) { in mvpp2_swf_bm_pool_init()
3728 port->pool_long = in mvpp2_swf_bm_pool_init()
3729 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id), in mvpp2_swf_bm_pool_init()
3731 port->pkt_size); in mvpp2_swf_bm_pool_init()
3732 if (!port->pool_long) in mvpp2_swf_bm_pool_init()
3735 port->pool_long->port_map |= (1 << port->id); in mvpp2_swf_bm_pool_init()
3738 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); in mvpp2_swf_bm_pool_init()
3741 if (!port->pool_short) { in mvpp2_swf_bm_pool_init()
3742 port->pool_short = in mvpp2_swf_bm_pool_init()
3743 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_SHORT_POOL, in mvpp2_swf_bm_pool_init()
3746 if (!port->pool_short) in mvpp2_swf_bm_pool_init()
3749 port->pool_short->port_map |= (1 << port->id); in mvpp2_swf_bm_pool_init()
3752 mvpp2_rxq_short_pool_set(port, rxq, in mvpp2_swf_bm_pool_init()
3753 port->pool_short->id); in mvpp2_swf_bm_pool_init()
3761 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_bm_update_mtu() local
3762 struct mvpp2_bm_pool *port_pool = port->pool_long; in mvpp2_bm_update_mtu()
3767 mvpp2_bm_bufs_free(dev->dev.parent, port->priv, port_pool); in mvpp2_bm_update_mtu()
3774 num = mvpp2_bm_bufs_add(port, port_pool, pkts_num); in mvpp2_bm_update_mtu()
3781 mvpp2_bm_pool_bufsize_set(port->priv, port_pool, in mvpp2_bm_update_mtu()
3788 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) in mvpp2_interrupts_enable() argument
3794 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_enable()
3798 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) in mvpp2_interrupts_disable() argument
3804 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_disable()
3811 struct mvpp2_port *port = arg; in mvpp2_interrupts_mask() local
3813 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); in mvpp2_interrupts_mask()
3819 struct mvpp2_port *port = arg; in mvpp2_interrupts_unmask() local
3821 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_MASK_REG(port->id), in mvpp2_interrupts_unmask()
3828 static void mvpp2_port_mii_set(struct mvpp2_port *port) in mvpp2_port_mii_set() argument
3832 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_mii_set()
3834 switch (port->phy_interface) { in mvpp2_port_mii_set()
3844 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_mii_set()
3847 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port) in mvpp2_port_fc_adv_enable() argument
3851 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_fc_adv_enable()
3853 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_fc_adv_enable()
3856 static void mvpp2_port_enable(struct mvpp2_port *port) in mvpp2_port_enable() argument
3860 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
3863 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
3866 static void mvpp2_port_disable(struct mvpp2_port *port) in mvpp2_port_disable() argument
3870 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
3872 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
3876 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) in mvpp2_port_periodic_xon_disable() argument
3880 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & in mvpp2_port_periodic_xon_disable()
3882 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_periodic_xon_disable()
3886 static void mvpp2_port_loopback_set(struct mvpp2_port *port) in mvpp2_port_loopback_set() argument
3890 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
3892 if (port->speed == 1000) in mvpp2_port_loopback_set()
3897 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) in mvpp2_port_loopback_set()
3902 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
3905 static void mvpp2_port_reset(struct mvpp2_port *port) in mvpp2_port_reset() argument
3909 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_port_reset()
3911 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_reset()
3913 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_port_reset()
3919 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) in mvpp2_gmac_max_rx_size_set() argument
3923 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
3925 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << in mvpp2_gmac_max_rx_size_set()
3927 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
3931 static void mvpp2_defaults_set(struct mvpp2_port *port) in mvpp2_defaults_set() argument
3936 if (port->flags & MVPP2_F_LOOPBACK) in mvpp2_defaults_set()
3937 mvpp2_port_loopback_set(port); in mvpp2_defaults_set()
3940 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
3944 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
3947 tx_port_num = mvpp2_egress_port(port); in mvpp2_defaults_set()
3948 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set()
3950 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); in mvpp2_defaults_set()
3954 ptxq = mvpp2_txq_phys(port->id, queue); in mvpp2_defaults_set()
3955 mvpp2_write(port->priv, in mvpp2_defaults_set()
3962 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, in mvpp2_defaults_set()
3963 port->priv->tclk / USEC_PER_SEC); in mvpp2_defaults_set()
3964 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); in mvpp2_defaults_set()
3968 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); in mvpp2_defaults_set()
3970 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_defaults_set()
3973 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), in mvpp2_defaults_set()
3979 queue = port->rxqs[lrxq]->id; in mvpp2_defaults_set()
3980 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_defaults_set()
3983 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
3987 mvpp2_interrupts_disable(port); in mvpp2_defaults_set()
3991 static void mvpp2_ingress_enable(struct mvpp2_port *port) in mvpp2_ingress_enable() argument
3997 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_enable()
3998 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_enable()
4000 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
4004 static void mvpp2_ingress_disable(struct mvpp2_port *port) in mvpp2_ingress_disable() argument
4010 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_disable()
4011 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_disable()
4013 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
4020 static void mvpp2_egress_enable(struct mvpp2_port *port) in mvpp2_egress_enable() argument
4024 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_enable()
4029 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_egress_enable()
4035 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable()
4036 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); in mvpp2_egress_enable()
4042 static void mvpp2_egress_disable(struct mvpp2_port *port) in mvpp2_egress_disable() argument
4046 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_disable()
4049 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable()
4050 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & in mvpp2_egress_disable()
4053 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, in mvpp2_egress_disable()
4060 netdev_warn(port->dev, in mvpp2_egress_disable()
4071 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); in mvpp2_egress_disable()
4079 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) in mvpp2_rxq_received() argument
4081 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); in mvpp2_rxq_received()
4090 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, in mvpp2_rxq_status_update() argument
4098 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); in mvpp2_rxq_status_update()
4113 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, in mvpp2_rxq_offset_set() argument
4121 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_offset_set()
4128 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()
4145 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port, in mvpp2_txq_pend_desc_num_get() argument
4150 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_pend_desc_num_get()
4151 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_pend_desc_num_get()
4167 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) in mvpp2_aggr_txq_pend_desc_add() argument
4170 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending); in mvpp2_aggr_txq_pend_desc_add()
4298 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, in mvpp2_txq_sent_desc_proc() argument
4304 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id)); in mvpp2_txq_sent_desc_proc()
4312 struct mvpp2_port *port = arg; in mvpp2_txq_sent_counter_clear() local
4316 int id = port->txqs[queue]->id; in mvpp2_txq_sent_counter_clear()
4318 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id)); in mvpp2_txq_sent_counter_clear()
4323 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) in mvpp2_txp_max_tx_size_set() argument
4328 mtu = port->pkt_size * 8; in mvpp2_txp_max_tx_size_set()
4336 tx_port_num = mvpp2_egress_port(port); in mvpp2_txp_max_tx_size_set()
4337 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set()
4340 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); in mvpp2_txp_max_tx_size_set()
4343 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); in mvpp2_txp_max_tx_size_set()
4346 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); in mvpp2_txp_max_tx_size_set()
4352 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_txp_max_tx_size_set()
4356 val = mvpp2_read(port->priv, in mvpp2_txp_max_tx_size_set()
4364 mvpp2_write(port->priv, in mvpp2_txp_max_tx_size_set()
4374 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, in mvpp2_rx_pkts_coal_set() argument
4380 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rx_pkts_coal_set()
4381 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val); in mvpp2_rx_pkts_coal_set()
4387 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, in mvpp2_rx_time_coal_set() argument
4392 val = (port->priv->tclk / USEC_PER_SEC) * usec; in mvpp2_rx_time_coal_set()
4393 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); in mvpp2_rx_time_coal_set()
4399 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, in mvpp2_txq_bufs_free() argument
4412 dma_unmap_single(port->dev->dev.parent, buf_phys_addr, in mvpp2_txq_bufs_free()
4420 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, in mvpp2_get_rx_queue() argument
4425 return port->rxqs[queue]; in mvpp2_get_rx_queue()
4428 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, in mvpp2_get_tx_queue() argument
4433 return port->txqs[queue]; in mvpp2_get_tx_queue()
4437 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, in mvpp2_txq_done() argument
4440 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); in mvpp2_txq_done()
4444 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); in mvpp2_txq_done()
4446 tx_done = mvpp2_txq_sent_desc_proc(port, txq); in mvpp2_txq_done()
4449 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); in mvpp2_txq_done()
4458 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause) in mvpp2_tx_done() argument
4465 txq = mvpp2_get_tx_queue(port, cause); in mvpp2_tx_done()
4472 mvpp2_txq_done(port, txq, txq_pcpu); in mvpp2_tx_done()
4516 static int mvpp2_rxq_init(struct mvpp2_port *port, in mvpp2_rxq_init() argument
4520 rxq->size = port->rx_ring_size; in mvpp2_rxq_init()
4523 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, in mvpp2_rxq_init()
4535 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_init()
4538 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_init()
4539 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_phys); in mvpp2_rxq_init()
4540 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); in mvpp2_rxq_init()
4541 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0); in mvpp2_rxq_init()
4544 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); in mvpp2_rxq_init()
4547 mvpp2_rx_pkts_coal_set(port, rxq, rxq->pkts_coal); in mvpp2_rxq_init()
4548 mvpp2_rx_time_coal_set(port, rxq, rxq->time_coal); in mvpp2_rxq_init()
4551 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); in mvpp2_rxq_init()
4557 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, in mvpp2_rxq_drop_pkts() argument
4562 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rxq_drop_pkts()
4570 mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr, in mvpp2_rxq_drop_pkts()
4573 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); in mvpp2_rxq_drop_pkts()
4577 static void mvpp2_rxq_deinit(struct mvpp2_port *port, in mvpp2_rxq_deinit() argument
4580 mvpp2_rxq_drop_pkts(port, rxq); in mvpp2_rxq_deinit()
4583 dma_free_coherent(port->dev->dev.parent, in mvpp2_rxq_deinit()
4596 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_deinit()
4597 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_deinit()
4598 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0); in mvpp2_rxq_deinit()
4599 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0); in mvpp2_rxq_deinit()
4603 static int mvpp2_txq_init(struct mvpp2_port *port, in mvpp2_txq_init() argument
4610 txq->size = port->tx_ring_size; in mvpp2_txq_init()
4613 txq->descs = dma_alloc_coherent(port->dev->dev.parent, in mvpp2_txq_init()
4626 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_init()
4627 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_phys); in mvpp2_txq_init()
4628 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size & in mvpp2_txq_init()
4630 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0); in mvpp2_txq_init()
4631 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG, in mvpp2_txq_init()
4633 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_init()
4635 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val); in mvpp2_txq_init()
4643 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + in mvpp2_txq_init()
4646 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, in mvpp2_txq_init()
4651 tx_port_num = mvpp2_egress_port(port); in mvpp2_txq_init()
4652 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
4654 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); in mvpp2_txq_init()
4658 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); in mvpp2_txq_init()
4661 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), in mvpp2_txq_init()
4693 dma_free_coherent(port->dev->dev.parent, in mvpp2_txq_init()
4701 static void mvpp2_txq_deinit(struct mvpp2_port *port, in mvpp2_txq_deinit() argument
4714 dma_free_coherent(port->dev->dev.parent, in mvpp2_txq_deinit()
4724 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); in mvpp2_txq_deinit()
4727 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_deinit()
4728 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0); in mvpp2_txq_deinit()
4729 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0); in mvpp2_txq_deinit()
4733 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) in mvpp2_txq_clean() argument
4739 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_clean()
4740 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG); in mvpp2_txq_clean()
4742 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4750 netdev_warn(port->dev, in mvpp2_txq_clean()
4752 port->id, txq->log_id); in mvpp2_txq_clean()
4758 pending = mvpp2_txq_pend_desc_num_get(port, txq); in mvpp2_txq_clean()
4762 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4768 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); in mvpp2_txq_clean()
4778 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) in mvpp2_cleanup_txqs() argument
4784 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); in mvpp2_cleanup_txqs()
4787 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
4788 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4791 txq = port->txqs[queue]; in mvpp2_cleanup_txqs()
4792 mvpp2_txq_clean(port, txq); in mvpp2_cleanup_txqs()
4793 mvpp2_txq_deinit(port, txq); in mvpp2_cleanup_txqs()
4796 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); in mvpp2_cleanup_txqs()
4798 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
4799 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4803 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) in mvpp2_cleanup_rxqs() argument
4808 mvpp2_rxq_deinit(port, port->rxqs[queue]); in mvpp2_cleanup_rxqs()
4812 static int mvpp2_setup_rxqs(struct mvpp2_port *port) in mvpp2_setup_rxqs() argument
4817 err = mvpp2_rxq_init(port, port->rxqs[queue]); in mvpp2_setup_rxqs()
4824 mvpp2_cleanup_rxqs(port); in mvpp2_setup_rxqs()
4829 static int mvpp2_setup_txqs(struct mvpp2_port *port) in mvpp2_setup_txqs() argument
4835 txq = port->txqs[queue]; in mvpp2_setup_txqs()
4836 err = mvpp2_txq_init(port, txq); in mvpp2_setup_txqs()
4841 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); in mvpp2_setup_txqs()
4845 mvpp2_cleanup_txqs(port); in mvpp2_setup_txqs()
4852 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; in mvpp2_isr() local
4854 mvpp2_interrupts_disable(port); in mvpp2_isr()
4856 napi_schedule(&port->napi); in mvpp2_isr()
4864 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_link_event() local
4865 struct phy_device *phydev = port->phy_dev; in mvpp2_link_event()
4870 if ((port->speed != phydev->speed) || in mvpp2_link_event()
4871 (port->duplex != phydev->duplex)) { in mvpp2_link_event()
4874 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4889 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4891 port->duplex = phydev->duplex; in mvpp2_link_event()
4892 port->speed = phydev->speed; in mvpp2_link_event()
4896 if (phydev->link != port->link) { in mvpp2_link_event()
4898 port->duplex = -1; in mvpp2_link_event()
4899 port->speed = 0; in mvpp2_link_event()
4902 port->link = phydev->link; in mvpp2_link_event()
4908 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4911 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4912 mvpp2_egress_enable(port); in mvpp2_link_event()
4913 mvpp2_ingress_enable(port); in mvpp2_link_event()
4915 mvpp2_ingress_disable(port); in mvpp2_link_event()
4916 mvpp2_egress_disable(port); in mvpp2_link_event()
4937 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_tx_proc_cb() local
4938 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); in mvpp2_tx_proc_cb()
4947 tx_todo = mvpp2_tx_done(port, cause); in mvpp2_tx_proc_cb()
4968 static void mvpp2_rx_error(struct mvpp2_port *port, in mvpp2_rx_error() argument
4975 netdev_err(port->dev, "bad rx status %08x (crc error), size=%d\n", in mvpp2_rx_error()
4979 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%d\n", in mvpp2_rx_error()
4983 netdev_err(port->dev, "bad rx status %08x (resource error), size=%d\n", in mvpp2_rx_error()
4990 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, in mvpp2_rx_csum() argument
5008 static int mvpp2_rx_refill(struct mvpp2_port *port, in mvpp2_rx_refill() argument
5020 skb = mvpp2_skb_alloc(port, bm_pool, &phys_addr, GFP_ATOMIC); in mvpp2_rx_refill()
5024 mvpp2_pool_refill(port, bm, (u32)phys_addr, (u32)skb); in mvpp2_rx_refill()
5030 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) in mvpp2_skb_tx_csum() argument
5060 static void mvpp2_buff_hdr_rx(struct mvpp2_port *port, in mvpp2_buff_hdr_rx() argument
5088 mvpp2_bm_pool_mc_put(port, pool_id, buff_phys_addr, in mvpp2_buff_hdr_rx()
5098 static int mvpp2_rx(struct mvpp2_port *port, int rx_todo, in mvpp2_rx() argument
5101 struct net_device *dev = port->dev; in mvpp2_rx()
5108 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rx()
5127 bm_pool = &port->priv->bm_pools[pool]; in mvpp2_rx()
5130 mvpp2_buff_hdr_rx(port, rx_desc); in mvpp2_rx()
5142 mvpp2_rx_error(port, rx_desc); in mvpp2_rx()
5144 mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr, in mvpp2_rx()
5151 err = mvpp2_rx_refill(port, bm_pool, bm, 0); in mvpp2_rx()
5153 netdev_err(port->dev, "failed to refill BM pools\n"); in mvpp2_rx()
5167 mvpp2_rx_csum(port, rx_status, skb); in mvpp2_rx()
5169 napi_gro_receive(&port->napi, skb); in mvpp2_rx()
5173 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); in mvpp2_rx()
5183 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); in mvpp2_rx()
5198 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, in mvpp2_tx_frag_process() argument
5215 buf_phys_addr = dma_map_single(port->dev->dev.parent, addr, in mvpp2_tx_frag_process()
5218 if (dma_mapping_error(port->dev->dev.parent, buf_phys_addr)) { in mvpp2_tx_frag_process()
5245 tx_desc_unmap_put(port->dev->dev.parent, txq, tx_desc); in mvpp2_tx_frag_process()
5254 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_tx() local
5264 txq = port->txqs[txq_id]; in mvpp2_tx()
5266 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; in mvpp2_tx()
5271 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) || in mvpp2_tx()
5272 mvpp2_txq_reserved_desc_num_proc(port->priv, txq, in mvpp2_tx()
5293 tx_cmd = mvpp2_skb_tx_csum(port, skb); in mvpp2_tx()
5307 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { in mvpp2_tx()
5308 tx_desc_unmap_put(port->dev->dev.parent, txq, tx_desc); in mvpp2_tx()
5320 mvpp2_aggr_txq_pend_desc_add(port, frags); in mvpp2_tx()
5329 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); in mvpp2_tx()
5342 mvpp2_txq_done(port, txq, txq_pcpu); in mvpp2_tx()
5346 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); in mvpp2_tx()
5368 struct mvpp2_port *port = netdev_priv(napi->dev); in mvpp2_poll() local
5380 cause_rx_tx = mvpp2_read(port->priv, in mvpp2_poll()
5381 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); in mvpp2_poll()
5386 mvpp2_cause_error(port->dev, cause_misc); in mvpp2_poll()
5389 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); in mvpp2_poll()
5390 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_CAUSE_REG(port->id), in mvpp2_poll()
5397 cause_rx |= port->pending_cause_rx; in mvpp2_poll()
5402 rxq = mvpp2_get_rx_queue(port, cause_rx); in mvpp2_poll()
5406 count = mvpp2_rx(port, budget, rxq); in mvpp2_poll()
5422 mvpp2_interrupts_enable(port); in mvpp2_poll()
5424 port->pending_cause_rx = cause_rx; in mvpp2_poll()
5429 static void mvpp2_start_dev(struct mvpp2_port *port) in mvpp2_start_dev() argument
5431 mvpp2_gmac_max_rx_size_set(port); in mvpp2_start_dev()
5432 mvpp2_txp_max_tx_size_set(port); in mvpp2_start_dev()
5434 napi_enable(&port->napi); in mvpp2_start_dev()
5437 mvpp2_interrupts_enable(port); in mvpp2_start_dev()
5439 mvpp2_port_enable(port); in mvpp2_start_dev()
5440 phy_start(port->phy_dev); in mvpp2_start_dev()
5441 netif_tx_start_all_queues(port->dev); in mvpp2_start_dev()
5445 static void mvpp2_stop_dev(struct mvpp2_port *port) in mvpp2_stop_dev() argument
5448 mvpp2_ingress_disable(port); in mvpp2_stop_dev()
5453 mvpp2_interrupts_disable(port); in mvpp2_stop_dev()
5455 napi_disable(&port->napi); in mvpp2_stop_dev()
5457 netif_carrier_off(port->dev); in mvpp2_stop_dev()
5458 netif_tx_stop_all_queues(port->dev); in mvpp2_stop_dev()
5460 mvpp2_egress_disable(port); in mvpp2_stop_dev()
5461 mvpp2_port_disable(port); in mvpp2_stop_dev()
5462 phy_stop(port->phy_dev); in mvpp2_stop_dev()
5522 static void mvpp2_get_mac_address(struct mvpp2_port *port, unsigned char *addr) in mvpp2_get_mac_address() argument
5526 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_get_mac_address()
5527 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); in mvpp2_get_mac_address()
5528 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); in mvpp2_get_mac_address()
5537 static int mvpp2_phy_connect(struct mvpp2_port *port) in mvpp2_phy_connect() argument
5541 phy_dev = of_phy_connect(port->dev, port->phy_node, mvpp2_link_event, 0, in mvpp2_phy_connect()
5542 port->phy_interface); in mvpp2_phy_connect()
5544 netdev_err(port->dev, "cannot connect to phy\n"); in mvpp2_phy_connect()
5550 port->phy_dev = phy_dev; in mvpp2_phy_connect()
5551 port->link = 0; in mvpp2_phy_connect()
5552 port->duplex = 0; in mvpp2_phy_connect()
5553 port->speed = 0; in mvpp2_phy_connect()
5558 static void mvpp2_phy_disconnect(struct mvpp2_port *port) in mvpp2_phy_disconnect() argument
5560 phy_disconnect(port->phy_dev); in mvpp2_phy_disconnect()
5561 port->phy_dev = NULL; in mvpp2_phy_disconnect()
5566 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_open() local
5571 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true); in mvpp2_open()
5576 err = mvpp2_prs_mac_da_accept(port->priv, port->id, in mvpp2_open()
5582 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); in mvpp2_open()
5587 err = mvpp2_prs_def_flow(port); in mvpp2_open()
5594 err = mvpp2_setup_rxqs(port); in mvpp2_open()
5596 netdev_err(port->dev, "cannot allocate Rx queues\n"); in mvpp2_open()
5600 err = mvpp2_setup_txqs(port); in mvpp2_open()
5602 netdev_err(port->dev, "cannot allocate Tx queues\n"); in mvpp2_open()
5606 err = request_irq(port->irq, mvpp2_isr, 0, dev->name, port); in mvpp2_open()
5608 netdev_err(port->dev, "cannot request IRQ %d\n", port->irq); in mvpp2_open()
5613 netif_carrier_off(port->dev); in mvpp2_open()
5615 err = mvpp2_phy_connect(port); in mvpp2_open()
5620 on_each_cpu(mvpp2_interrupts_unmask, port, 1); in mvpp2_open()
5622 mvpp2_start_dev(port); in mvpp2_open()
5627 free_irq(port->irq, port); in mvpp2_open()
5629 mvpp2_cleanup_txqs(port); in mvpp2_open()
5631 mvpp2_cleanup_rxqs(port); in mvpp2_open()
5637 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_stop() local
5641 mvpp2_stop_dev(port); in mvpp2_stop()
5642 mvpp2_phy_disconnect(port); in mvpp2_stop()
5645 on_each_cpu(mvpp2_interrupts_mask, port, 1); in mvpp2_stop()
5647 free_irq(port->irq, port); in mvpp2_stop()
5649 port_pcpu = per_cpu_ptr(port->pcpu, cpu); in mvpp2_stop()
5655 mvpp2_cleanup_rxqs(port); in mvpp2_stop()
5656 mvpp2_cleanup_txqs(port); in mvpp2_stop()
5663 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_set_rx_mode() local
5664 struct mvpp2 *priv = port->priv; in mvpp2_set_rx_mode()
5666 int id = port->id; in mvpp2_set_rx_mode()
5684 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_set_mac_address() local
5703 mvpp2_stop_dev(port); in mvpp2_set_mac_address()
5714 mvpp2_start_dev(port); in mvpp2_set_mac_address()
5715 mvpp2_egress_enable(port); in mvpp2_set_mac_address()
5716 mvpp2_ingress_enable(port); in mvpp2_set_mac_address()
5726 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_change_mtu() local
5738 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); in mvpp2_change_mtu()
5748 mvpp2_stop_dev(port); in mvpp2_change_mtu()
5752 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); in mvpp2_change_mtu()
5762 mvpp2_start_dev(port); in mvpp2_change_mtu()
5763 mvpp2_egress_enable(port); in mvpp2_change_mtu()
5764 mvpp2_ingress_enable(port); in mvpp2_change_mtu()
5776 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_get_stats64() local
5787 cpu_stats = per_cpu_ptr(port->stats, cpu); in mvpp2_get_stats64()
5811 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ioctl() local
5814 if (!port->phy_dev) in mvpp2_ioctl()
5817 ret = phy_mii_ioctl(port->phy_dev, ifr, cmd); in mvpp2_ioctl()
5830 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_settings() local
5832 if (!port->phy_dev) in mvpp2_ethtool_get_settings()
5834 return phy_ethtool_gset(port->phy_dev, cmd); in mvpp2_ethtool_get_settings()
5841 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_settings() local
5843 if (!port->phy_dev) in mvpp2_ethtool_set_settings()
5845 return phy_ethtool_sset(port->phy_dev, cmd); in mvpp2_ethtool_set_settings()
5852 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_coalesce() local
5856 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_ethtool_set_coalesce()
5860 mvpp2_rx_pkts_coal_set(port, rxq, rxq->pkts_coal); in mvpp2_ethtool_set_coalesce()
5861 mvpp2_rx_time_coal_set(port, rxq, rxq->time_coal); in mvpp2_ethtool_set_coalesce()
5865 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_ethtool_set_coalesce()
5877 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_coalesce() local
5879 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; in mvpp2_ethtool_get_coalesce()
5880 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; in mvpp2_ethtool_get_coalesce()
5881 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; in mvpp2_ethtool_get_coalesce()
5899 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_ringparam() local
5903 ring->rx_pending = port->rx_ring_size; in mvpp2_ethtool_get_ringparam()
5904 ring->tx_pending = port->tx_ring_size; in mvpp2_ethtool_get_ringparam()
5910 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_ringparam() local
5911 u16 prev_rx_ring_size = port->rx_ring_size; in mvpp2_ethtool_set_ringparam()
5912 u16 prev_tx_ring_size = port->tx_ring_size; in mvpp2_ethtool_set_ringparam()
5920 port->rx_ring_size = ring->rx_pending; in mvpp2_ethtool_set_ringparam()
5921 port->tx_ring_size = ring->tx_pending; in mvpp2_ethtool_set_ringparam()
5928 mvpp2_stop_dev(port); in mvpp2_ethtool_set_ringparam()
5929 mvpp2_cleanup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5930 mvpp2_cleanup_txqs(port); in mvpp2_ethtool_set_ringparam()
5932 port->rx_ring_size = ring->rx_pending; in mvpp2_ethtool_set_ringparam()
5933 port->tx_ring_size = ring->tx_pending; in mvpp2_ethtool_set_ringparam()
5935 err = mvpp2_setup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5938 port->rx_ring_size = prev_rx_ring_size; in mvpp2_ethtool_set_ringparam()
5940 err = mvpp2_setup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5944 err = mvpp2_setup_txqs(port); in mvpp2_ethtool_set_ringparam()
5947 port->tx_ring_size = prev_tx_ring_size; in mvpp2_ethtool_set_ringparam()
5949 err = mvpp2_setup_txqs(port); in mvpp2_ethtool_set_ringparam()
5954 mvpp2_start_dev(port); in mvpp2_ethtool_set_ringparam()
5955 mvpp2_egress_enable(port); in mvpp2_ethtool_set_ringparam()
5956 mvpp2_ingress_enable(port); in mvpp2_ethtool_set_ringparam()
5961 mvpp2_cleanup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5993 static void mvpp2_port_power_up(struct mvpp2_port *port) in mvpp2_port_power_up() argument
5995 mvpp2_port_mii_set(port); in mvpp2_port_power_up()
5996 mvpp2_port_periodic_xon_disable(port); in mvpp2_port_power_up()
5997 mvpp2_port_fc_adv_enable(port); in mvpp2_port_power_up()
5998 mvpp2_port_reset(port); in mvpp2_port_power_up()
6002 static int mvpp2_port_init(struct mvpp2_port *port) in mvpp2_port_init() argument
6004 struct device *dev = port->dev->dev.parent; in mvpp2_port_init()
6005 struct mvpp2 *priv = port->priv; in mvpp2_port_init()
6009 if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM) in mvpp2_port_init()
6013 mvpp2_egress_disable(port); in mvpp2_port_init()
6014 mvpp2_port_disable(port); in mvpp2_port_init()
6016 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs), in mvpp2_port_init()
6018 if (!port->txqs) in mvpp2_port_init()
6025 int queue_phy_id = mvpp2_txq_phys(port->id, queue); in mvpp2_port_init()
6046 port->txqs[queue] = txq; in mvpp2_port_init()
6049 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs), in mvpp2_port_init()
6051 if (!port->rxqs) { in mvpp2_port_init()
6065 rxq->id = port->first_rxq + queue; in mvpp2_port_init()
6066 rxq->port = port->id; in mvpp2_port_init()
6069 port->rxqs[queue] = rxq; in mvpp2_port_init()
6073 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), rxq_number); in mvpp2_port_init()
6077 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_port_init()
6079 rxq->size = port->rx_ring_size; in mvpp2_port_init()
6084 mvpp2_ingress_disable(port); in mvpp2_port_init()
6087 mvpp2_defaults_set(port); in mvpp2_port_init()
6090 mvpp2_cls_oversize_rxq_set(port); in mvpp2_port_init()
6091 mvpp2_cls_port_config(port); in mvpp2_port_init()
6094 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); in mvpp2_port_init()
6097 err = mvpp2_swf_bm_pool_init(port); in mvpp2_port_init()
6105 if (!port->txqs[queue]) in mvpp2_port_init()
6107 free_percpu(port->txqs[queue]->pcpu); in mvpp2_port_init()
6119 struct mvpp2_port *port; in mvpp2_port_probe() local
6162 port = netdev_priv(dev); in mvpp2_port_probe()
6164 port->irq = irq_of_parse_and_map(port_node, 0); in mvpp2_port_probe()
6165 if (port->irq <= 0) { in mvpp2_port_probe()
6171 port->flags |= MVPP2_F_LOOPBACK; in mvpp2_port_probe()
6173 port->priv = priv; in mvpp2_port_probe()
6174 port->id = id; in mvpp2_port_probe()
6175 port->first_rxq = *next_first_rxq; in mvpp2_port_probe()
6176 port->phy_node = phy_node; in mvpp2_port_probe()
6177 port->phy_interface = phy_mode; in mvpp2_port_probe()
6181 port->base = devm_ioremap_resource(&pdev->dev, res); in mvpp2_port_probe()
6182 if (IS_ERR(port->base)) { in mvpp2_port_probe()
6183 err = PTR_ERR(port->base); in mvpp2_port_probe()
6188 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); in mvpp2_port_probe()
6189 if (!port->stats) { in mvpp2_port_probe()
6199 mvpp2_get_mac_address(port, hw_mac_addr); in mvpp2_port_probe()
6209 port->tx_ring_size = MVPP2_MAX_TXD; in mvpp2_port_probe()
6210 port->rx_ring_size = MVPP2_MAX_RXD; in mvpp2_port_probe()
6211 port->dev = dev; in mvpp2_port_probe()
6214 err = mvpp2_port_init(port); in mvpp2_port_probe()
6219 mvpp2_port_power_up(port); in mvpp2_port_probe()
6221 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); in mvpp2_port_probe()
6222 if (!port->pcpu) { in mvpp2_port_probe()
6228 port_pcpu = per_cpu_ptr(port->pcpu, cpu); in mvpp2_port_probe()
6239 netif_napi_add(dev, &port->napi, mvpp2_poll, NAPI_POLL_WEIGHT); in mvpp2_port_probe()
6254 priv->port_list[id] = port; in mvpp2_port_probe()
6258 free_percpu(port->pcpu); in mvpp2_port_probe()
6261 free_percpu(port->txqs[i]->pcpu); in mvpp2_port_probe()
6263 free_percpu(port->stats); in mvpp2_port_probe()
6265 irq_dispose_mapping(port->irq); in mvpp2_port_probe()
6272 static void mvpp2_port_remove(struct mvpp2_port *port) in mvpp2_port_remove() argument
6276 unregister_netdev(port->dev); in mvpp2_port_remove()
6277 free_percpu(port->pcpu); in mvpp2_port_remove()
6278 free_percpu(port->stats); in mvpp2_port_remove()
6280 free_percpu(port->txqs[i]->pcpu); in mvpp2_port_remove()
6281 irq_dispose_mapping(port->irq); in mvpp2_port_remove()
6282 free_netdev(port->dev); in mvpp2_port_remove()
6321 int port; in mvpp2_rx_fifo_init() local
6323 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_rx_fifo_init()
6324 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
6326 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()