Lines Matching refs:pe
1008 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_write() argument
1012 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
1016 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; in mvpp2_prs_hw_write()
1019 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1021 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); in mvpp2_prs_hw_write()
1024 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1026 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1032 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_read() argument
1036 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_read()
1040 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1042 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, in mvpp2_prs_hw_read()
1044 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) in mvpp2_prs_hw_read()
1048 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1051 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1053 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1083 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) in mvpp2_prs_tcam_lu_set() argument
1087 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu; in mvpp2_prs_tcam_lu_set()
1088 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK; in mvpp2_prs_tcam_lu_set()
1092 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_set() argument
1098 pe->tcam.byte[enable_off] &= ~(1 << port); in mvpp2_prs_tcam_port_set()
1100 pe->tcam.byte[enable_off] |= 1 << port; in mvpp2_prs_tcam_port_set()
1104 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_map_set() argument
1110 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0; in mvpp2_prs_tcam_port_map_set()
1111 pe->tcam.byte[enable_off] &= ~port_mask; in mvpp2_prs_tcam_port_map_set()
1112 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_set()
1116 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_port_map_get() argument
1120 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_get()
1124 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_set() argument
1128 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte; in mvpp2_prs_tcam_data_byte_set()
1129 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable; in mvpp2_prs_tcam_data_byte_set()
1133 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_get() argument
1137 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)]; in mvpp2_prs_tcam_data_byte_get()
1138 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)]; in mvpp2_prs_tcam_data_byte_get()
1142 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs, in mvpp2_prs_tcam_data_cmp() argument
1148 tcam_data = (8 << pe->tcam.byte[off + 1]) | pe->tcam.byte[off]; in mvpp2_prs_tcam_data_cmp()
1155 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_ai_update() argument
1166 pe->tcam.byte[ai_idx] |= 1 << i; in mvpp2_prs_tcam_ai_update()
1168 pe->tcam.byte[ai_idx] &= ~(1 << i); in mvpp2_prs_tcam_ai_update()
1171 pe->tcam.byte[MVPP2_PRS_TCAM_EN_OFFS(ai_idx)] |= enable; in mvpp2_prs_tcam_ai_update()
1175 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_ai_get() argument
1177 return pe->tcam.byte[MVPP2_PRS_TCAM_AI_BYTE]; in mvpp2_prs_tcam_ai_get()
1181 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_etype() argument
1184 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); in mvpp2_prs_match_etype()
1185 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); in mvpp2_prs_match_etype()
1189 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_set() argument
1192 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8)); in mvpp2_prs_sram_bits_set()
1196 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_clear() argument
1199 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8)); in mvpp2_prs_sram_bits_clear()
1203 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ri_update() argument
1215 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1); in mvpp2_prs_sram_ri_update()
1217 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1); in mvpp2_prs_sram_ri_update()
1219 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ri_update()
1224 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ri_get() argument
1226 return pe->sram.word[MVPP2_PRS_SRAM_RI_WORD]; in mvpp2_prs_sram_ri_get()
1230 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ai_update() argument
1242 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1); in mvpp2_prs_sram_ai_update()
1244 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1); in mvpp2_prs_sram_ai_update()
1246 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ai_update()
1251 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ai_get() argument
1258 bits = (pe->sram.byte[ai_off] >> ai_shift) | in mvpp2_prs_sram_ai_get()
1259 (pe->sram.byte[ai_en_off] << (8 - ai_shift)); in mvpp2_prs_sram_ai_get()
1267 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_next_lu_set() argument
1272 mvpp2_prs_sram_bits_clear(pe, sram_next_off, in mvpp2_prs_sram_next_lu_set()
1274 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); in mvpp2_prs_sram_next_lu_set()
1280 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, in mvpp2_prs_sram_shift_set() argument
1285 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
1288 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
1292 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = in mvpp2_prs_sram_shift_set()
1296 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, in mvpp2_prs_sram_shift_set()
1298 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); in mvpp2_prs_sram_shift_set()
1301 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_shift_set()
1307 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_offset_set() argument
1313 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
1316 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
1320 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
1322 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset); in mvpp2_prs_sram_offset_set()
1323 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1326 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1331 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, in mvpp2_prs_sram_offset_set()
1333 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); in mvpp2_prs_sram_offset_set()
1336 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
1338 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op); in mvpp2_prs_sram_offset_set()
1340 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1345 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1350 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_offset_set()
1356 struct mvpp2_prs_entry *pe; in mvpp2_prs_flow_find() local
1359 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_flow_find()
1360 if (!pe) in mvpp2_prs_flow_find()
1362 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_flow_find()
1372 pe->index = tid; in mvpp2_prs_flow_find()
1373 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_flow_find()
1374 bits = mvpp2_prs_sram_ai_get(pe); in mvpp2_prs_flow_find()
1378 return pe; in mvpp2_prs_flow_find()
1380 kfree(pe); in mvpp2_prs_flow_find()
1408 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_drop_all_set() local
1412 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
1413 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_drop_all_set()
1416 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_drop_all_set()
1417 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
1418 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
1421 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_drop_all_set()
1424 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_drop_all_set()
1425 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_drop_all_set()
1428 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
1431 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_drop_all_set()
1435 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
1437 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_drop_all_set()
1443 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_promisc_set() local
1449 pe.index = MVPP2_PE_MAC_PROMISCUOUS; in mvpp2_prs_mac_promisc_set()
1450 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_promisc_set()
1453 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_promisc_set()
1454 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
1455 pe.index = MVPP2_PE_MAC_PROMISCUOUS; in mvpp2_prs_mac_promisc_set()
1458 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_promisc_set()
1461 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST, in mvpp2_prs_mac_promisc_set()
1465 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_promisc_set()
1469 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_promisc_set()
1472 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
1476 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
1478 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_promisc_set()
1485 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_multi_set() local
1495 pe.index = index; in mvpp2_prs_mac_multi_set()
1496 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_multi_set()
1499 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_multi_set()
1500 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_multi_set()
1501 pe.index = index; in mvpp2_prs_mac_multi_set()
1504 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_multi_set()
1507 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST, in mvpp2_prs_mac_multi_set()
1511 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff); in mvpp2_prs_mac_multi_set()
1514 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_multi_set()
1518 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_multi_set()
1521 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_multi_set()
1525 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_multi_set()
1527 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_multi_set()
1534 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_set() local
1547 pe.index = tid; in mvpp2_prs_dsa_tag_set()
1548 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_dsa_tag_set()
1551 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_dsa_tag_set()
1552 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
1553 pe.index = tid; in mvpp2_prs_dsa_tag_set()
1556 mvpp2_prs_sram_shift_set(&pe, shift, in mvpp2_prs_dsa_tag_set()
1560 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
1564 mvpp2_prs_tcam_data_byte_set(&pe, 0, in mvpp2_prs_dsa_tag_set()
1568 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_set()
1571 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_tag_set()
1574 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_set()
1576 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_set()
1580 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_dsa_tag_set()
1584 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_set()
1586 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_set()
1593 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_ethertype_set() local
1610 pe.index = tid; in mvpp2_prs_dsa_tag_ethertype_set()
1611 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_dsa_tag_ethertype_set()
1614 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_dsa_tag_ethertype_set()
1615 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
1616 pe.index = tid; in mvpp2_prs_dsa_tag_ethertype_set()
1619 mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA); in mvpp2_prs_dsa_tag_ethertype_set()
1620 mvpp2_prs_match_etype(&pe, 2, 0); in mvpp2_prs_dsa_tag_ethertype_set()
1622 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK, in mvpp2_prs_dsa_tag_ethertype_set()
1625 mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift, in mvpp2_prs_dsa_tag_ethertype_set()
1629 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
1633 mvpp2_prs_tcam_data_byte_set(&pe, in mvpp2_prs_dsa_tag_ethertype_set()
1638 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_ethertype_set()
1641 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_tag_ethertype_set()
1644 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_ethertype_set()
1646 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_ethertype_set()
1649 mvpp2_prs_tcam_port_map_set(&pe, port_mask); in mvpp2_prs_dsa_tag_ethertype_set()
1653 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_ethertype_set()
1655 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_ethertype_set()
1662 struct mvpp2_prs_entry *pe; in mvpp2_prs_vlan_find() local
1665 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_vlan_find()
1666 if (!pe) in mvpp2_prs_vlan_find()
1668 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_find()
1680 pe->index = tid; in mvpp2_prs_vlan_find()
1682 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_vlan_find()
1683 match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid)); in mvpp2_prs_vlan_find()
1688 ri_bits = mvpp2_prs_sram_ri_get(pe); in mvpp2_prs_vlan_find()
1692 ai_bits = mvpp2_prs_tcam_ai_get(pe); in mvpp2_prs_vlan_find()
1701 return pe; in mvpp2_prs_vlan_find()
1703 kfree(pe); in mvpp2_prs_vlan_find()
1712 struct mvpp2_prs_entry *pe; in mvpp2_prs_vlan_add() local
1716 pe = mvpp2_prs_vlan_find(priv, tpid, ai); in mvpp2_prs_vlan_add()
1718 if (!pe) { in mvpp2_prs_vlan_add()
1725 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_vlan_add()
1726 if (!pe) in mvpp2_prs_vlan_add()
1738 pe->index = tid_aux; in mvpp2_prs_vlan_add()
1739 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_vlan_add()
1740 ri_bits = mvpp2_prs_sram_ri_get(pe); in mvpp2_prs_vlan_add()
1751 memset(pe, 0 , sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_vlan_add()
1752 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
1753 pe->index = tid; in mvpp2_prs_vlan_add()
1755 mvpp2_prs_match_etype(pe, 0, tpid); in mvpp2_prs_vlan_add()
1757 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_add()
1759 mvpp2_prs_sram_shift_set(pe, MVPP2_VLAN_TAG_LEN, in mvpp2_prs_vlan_add()
1762 mvpp2_prs_sram_ai_update(pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
1765 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_SINGLE, in mvpp2_prs_vlan_add()
1769 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_TRIPLE, in mvpp2_prs_vlan_add()
1772 mvpp2_prs_tcam_ai_update(pe, ai, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
1774 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
1777 mvpp2_prs_tcam_port_map_set(pe, port_map); in mvpp2_prs_vlan_add()
1779 mvpp2_prs_hw_write(priv, pe); in mvpp2_prs_vlan_add()
1782 kfree(pe); in mvpp2_prs_vlan_add()
1805 struct mvpp2_prs_entry *pe; in mvpp2_prs_double_vlan_find() local
1808 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_double_vlan_find()
1809 if (!pe) in mvpp2_prs_double_vlan_find()
1811 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_find()
1823 pe->index = tid; in mvpp2_prs_double_vlan_find()
1824 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_double_vlan_find()
1826 match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid1)) in mvpp2_prs_double_vlan_find()
1827 && mvpp2_prs_tcam_data_cmp(pe, 4, swab16(tpid2)); in mvpp2_prs_double_vlan_find()
1832 ri_mask = mvpp2_prs_sram_ri_get(pe) & MVPP2_PRS_RI_VLAN_MASK; in mvpp2_prs_double_vlan_find()
1834 return pe; in mvpp2_prs_double_vlan_find()
1836 kfree(pe); in mvpp2_prs_double_vlan_find()
1846 struct mvpp2_prs_entry *pe; in mvpp2_prs_double_vlan_add() local
1849 pe = mvpp2_prs_double_vlan_find(priv, tpid1, tpid2); in mvpp2_prs_double_vlan_add()
1851 if (!pe) { in mvpp2_prs_double_vlan_add()
1858 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_double_vlan_add()
1859 if (!pe) in mvpp2_prs_double_vlan_add()
1878 pe->index = tid_aux; in mvpp2_prs_double_vlan_add()
1879 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_double_vlan_add()
1880 ri_bits = mvpp2_prs_sram_ri_get(pe); in mvpp2_prs_double_vlan_add()
1892 memset(pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_double_vlan_add()
1893 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
1894 pe->index = tid; in mvpp2_prs_double_vlan_add()
1898 mvpp2_prs_match_etype(pe, 0, tpid1); in mvpp2_prs_double_vlan_add()
1899 mvpp2_prs_match_etype(pe, 4, tpid2); in mvpp2_prs_double_vlan_add()
1901 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
1903 mvpp2_prs_sram_shift_set(pe, 2 * MVPP2_VLAN_TAG_LEN, in mvpp2_prs_double_vlan_add()
1905 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_double_vlan_add()
1907 mvpp2_prs_sram_ai_update(pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_double_vlan_add()
1910 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
1914 mvpp2_prs_tcam_port_map_set(pe, port_map); in mvpp2_prs_double_vlan_add()
1915 mvpp2_prs_hw_write(priv, pe); in mvpp2_prs_double_vlan_add()
1918 kfree(pe); in mvpp2_prs_double_vlan_add()
1926 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_proto() local
1939 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip4_proto()
1940 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
1941 pe.index = tid; in mvpp2_prs_ip4_proto()
1944 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
1945 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_proto()
1947 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip4_proto()
1950 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_proto()
1952 mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_MASK, in mvpp2_prs_ip4_proto()
1955 mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip4_proto()
1956 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_proto()
1958 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_proto()
1961 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
1962 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
1970 pe.index = tid; in mvpp2_prs_ip4_proto()
1972 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_ip4_proto()
1973 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_ip4_proto()
1974 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip4_proto()
1976 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, MVPP2_PRS_TCAM_PROTO_MASK_L); in mvpp2_prs_ip4_proto()
1977 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip4_proto()
1980 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
1981 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
1989 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_cast() local
1997 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip4_cast()
1998 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
1999 pe.index = tid; in mvpp2_prs_ip4_cast()
2003 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC, in mvpp2_prs_ip4_cast()
2005 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip4_cast()
2010 mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask); in mvpp2_prs_ip4_cast()
2011 mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask); in mvpp2_prs_ip4_cast()
2012 mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask); in mvpp2_prs_ip4_cast()
2013 mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask); in mvpp2_prs_ip4_cast()
2014 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST, in mvpp2_prs_ip4_cast()
2022 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_cast()
2023 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_cast()
2025 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_cast()
2028 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_cast()
2031 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
2032 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_cast()
2041 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_proto() local
2053 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_proto()
2054 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
2055 pe.index = tid; in mvpp2_prs_ip6_proto()
2058 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_proto()
2059 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_proto()
2060 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip6_proto()
2061 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_proto()
2065 mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip6_proto()
2066 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_proto()
2069 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_proto()
2072 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
2073 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_proto()
2081 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_cast() local
2092 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_cast()
2093 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
2094 pe.index = tid; in mvpp2_prs_ip6_cast()
2097 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
2098 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip6_cast()
2100 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_cast()
2103 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_cast()
2105 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC, in mvpp2_prs_ip6_cast()
2107 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_cast()
2109 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_cast()
2112 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
2113 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_cast()
2148 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow_init() local
2152 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_def_flow_init()
2153 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
2154 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
2157 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_def_flow_init()
2160 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
2161 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow_init()
2164 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
2165 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_def_flow_init()
2172 struct mvpp2_prs_entry pe; in mvpp2_prs_mh_init() local
2174 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mh_init()
2176 pe.index = MVPP2_PE_MH_DEFAULT; in mvpp2_prs_mh_init()
2177 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
2178 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, in mvpp2_prs_mh_init()
2180 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mh_init()
2183 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mh_init()
2186 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
2187 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mh_init()
2195 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_init() local
2197 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_init()
2200 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; in mvpp2_prs_mac_init()
2201 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
2203 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_init()
2205 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_init()
2206 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_init()
2209 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mac_init()
2212 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
2213 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_init()
2225 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_init() local
2258 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_dsa_init()
2259 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_init()
2260 pe.index = MVPP2_PE_DSA_DEFAULT; in mvpp2_prs_dsa_init()
2261 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_init()
2264 mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_dsa_init()
2265 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_dsa_init()
2268 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_dsa_init()
2271 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_dsa_init()
2273 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_init()
2279 struct mvpp2_prs_entry pe; in mvpp2_prs_etype_init() local
2288 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2289 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2290 pe.index = tid; in mvpp2_prs_etype_init()
2292 mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES); in mvpp2_prs_etype_init()
2294 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, in mvpp2_prs_etype_init()
2296 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_etype_init()
2297 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
2301 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2302 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2303 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2304 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
2306 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2314 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2315 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2316 pe.index = tid; in mvpp2_prs_etype_init()
2318 mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP); in mvpp2_prs_etype_init()
2321 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2322 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2323 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
2326 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2331 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2332 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2333 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2334 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
2336 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2344 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2345 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2346 pe.index = tid; in mvpp2_prs_etype_init()
2348 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); in mvpp2_prs_etype_init()
2351 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2352 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2353 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2358 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2363 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2364 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2365 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2366 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2370 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2378 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2379 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2380 pe.index = tid; in mvpp2_prs_etype_init()
2382 mvpp2_prs_match_etype(&pe, 0, ETH_P_IP); in mvpp2_prs_etype_init()
2383 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
2388 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_etype_init()
2389 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
2392 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_etype_init()
2395 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2400 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2401 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2402 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2403 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
2405 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2413 pe.index = tid; in mvpp2_prs_etype_init()
2416 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0; in mvpp2_prs_etype_init()
2417 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0; in mvpp2_prs_etype_init()
2419 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
2424 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_etype_init()
2425 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_etype_init()
2426 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
2430 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2431 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2432 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2433 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
2435 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2443 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2444 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2445 pe.index = tid; in mvpp2_prs_etype_init()
2447 mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6); in mvpp2_prs_etype_init()
2450 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + in mvpp2_prs_etype_init()
2453 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_etype_init()
2454 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
2457 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2461 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2462 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2463 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2464 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
2466 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2469 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2470 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2471 pe.index = MVPP2_PE_ETH_TYPE_UN; in mvpp2_prs_etype_init()
2474 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_etype_init()
2477 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2478 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2479 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
2482 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2487 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2488 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2489 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2490 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
2492 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2506 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_init() local
2540 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_vlan_init()
2541 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
2542 pe.index = MVPP2_PE_VLAN_DBL; in mvpp2_prs_vlan_init()
2544 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_init()
2546 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_init()
2547 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_vlan_init()
2550 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_vlan_init()
2553 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
2556 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
2557 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
2560 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_vlan_init()
2561 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
2562 pe.index = MVPP2_PE_VLAN_NONE; in mvpp2_prs_vlan_init()
2564 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_init()
2565 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_vlan_init()
2569 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
2572 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
2573 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
2581 struct mvpp2_prs_entry pe; in mvpp2_prs_pppoe_init() local
2590 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_pppoe_init()
2591 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2592 pe.index = tid; in mvpp2_prs_pppoe_init()
2594 mvpp2_prs_match_etype(&pe, 0, PPP_IP); in mvpp2_prs_pppoe_init()
2596 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_pppoe_init()
2597 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_pppoe_init()
2600 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_pppoe_init()
2603 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
2608 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2609 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
2617 pe.index = tid; in mvpp2_prs_pppoe_init()
2619 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_pppoe_init()
2625 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_pppoe_init()
2626 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_pppoe_init()
2627 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_pppoe_init()
2631 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2632 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
2640 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_pppoe_init()
2641 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2642 pe.index = tid; in mvpp2_prs_pppoe_init()
2644 mvpp2_prs_match_etype(&pe, 0, PPP_IPV6); in mvpp2_prs_pppoe_init()
2646 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_pppoe_init()
2647 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_pppoe_init()
2650 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_pppoe_init()
2653 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
2658 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2659 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
2667 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_pppoe_init()
2668 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2669 pe.index = tid; in mvpp2_prs_pppoe_init()
2671 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_pppoe_init()
2675 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_pppoe_init()
2676 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_pppoe_init()
2678 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
2683 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2684 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
2692 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_init() local
2725 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip4_init()
2726 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2727 pe.index = MVPP2_PE_IP4_PROTO_UN; in mvpp2_prs_ip4_init()
2730 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2731 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_init()
2733 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip4_init()
2736 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
2738 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip4_init()
2741 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_init()
2743 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
2746 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2747 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
2750 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip4_init()
2751 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2752 pe.index = MVPP2_PE_IP4_ADDR_UN; in mvpp2_prs_ip4_init()
2755 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_init()
2756 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_init()
2757 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip4_init()
2760 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
2763 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
2766 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2767 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
2775 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_init() local
2818 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
2819 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2820 pe.index = tid; in mvpp2_prs_ip6_init()
2823 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
2824 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
2825 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN | in mvpp2_prs_ip6_init()
2830 mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK); in mvpp2_prs_ip6_init()
2831 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
2835 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
2836 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
2839 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
2840 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2841 pe.index = MVPP2_PE_IP6_PROTO_UN; in mvpp2_prs_ip6_init()
2844 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
2845 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
2846 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
2849 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_init()
2853 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
2856 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
2859 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
2860 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
2863 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
2864 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2865 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN; in mvpp2_prs_ip6_init()
2868 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
2869 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
2870 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
2873 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT, in mvpp2_prs_ip6_init()
2876 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
2879 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
2880 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
2883 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
2884 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2885 pe.index = MVPP2_PE_IP6_ADDR_UN; in mvpp2_prs_ip6_init()
2888 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2889 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip6_init()
2891 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
2894 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_init()
2896 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_init()
2898 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
2901 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2902 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
2974 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, in mvpp2_prs_mac_range_equals() argument
2981 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); in mvpp2_prs_mac_range_equals()
2997 struct mvpp2_prs_entry *pe; in mvpp2_prs_mac_da_range_find() local
3000 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_mac_da_range_find()
3001 if (!pe) in mvpp2_prs_mac_da_range_find()
3003 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_range_find()
3015 pe->index = tid; in mvpp2_prs_mac_da_range_find()
3016 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_mac_da_range_find()
3017 entry_pmap = mvpp2_prs_tcam_port_map_get(pe); in mvpp2_prs_mac_da_range_find()
3019 if (mvpp2_prs_mac_range_equals(pe, da, mask) && in mvpp2_prs_mac_da_range_find()
3021 return pe; in mvpp2_prs_mac_da_range_find()
3023 kfree(pe); in mvpp2_prs_mac_da_range_find()
3032 struct mvpp2_prs_entry *pe; in mvpp2_prs_mac_da_accept() local
3038 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, in mvpp2_prs_mac_da_accept()
3042 if (!pe) { in mvpp2_prs_mac_da_accept()
3062 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_mac_da_accept()
3063 if (!pe) in mvpp2_prs_mac_da_accept()
3065 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
3066 pe->index = tid; in mvpp2_prs_mac_da_accept()
3069 mvpp2_prs_tcam_port_map_set(pe, 0); in mvpp2_prs_mac_da_accept()
3073 mvpp2_prs_tcam_port_set(pe, port, add); in mvpp2_prs_mac_da_accept()
3076 pmap = mvpp2_prs_tcam_port_map_get(pe); in mvpp2_prs_mac_da_accept()
3079 kfree(pe); in mvpp2_prs_mac_da_accept()
3082 mvpp2_prs_hw_inv(priv, pe->index); in mvpp2_prs_mac_da_accept()
3083 priv->prs_shadow[pe->index].valid = false; in mvpp2_prs_mac_da_accept()
3084 kfree(pe); in mvpp2_prs_mac_da_accept()
3089 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_da_accept()
3094 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff); in mvpp2_prs_mac_da_accept()
3104 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
3106 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
3110 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN, in mvpp2_prs_mac_da_accept()
3114 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF; in mvpp2_prs_mac_da_accept()
3115 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
3116 mvpp2_prs_hw_write(priv, pe); in mvpp2_prs_mac_da_accept()
3118 kfree(pe); in mvpp2_prs_mac_da_accept()
3148 struct mvpp2_prs_entry pe; in mvpp2_prs_mcast_del_all() local
3161 pe.index = tid; in mvpp2_prs_mcast_del_all()
3162 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mcast_del_all()
3166 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index], in mvpp2_prs_mcast_del_all()
3228 struct mvpp2_prs_entry *pe; in mvpp2_prs_def_flow() local
3231 pe = mvpp2_prs_flow_find(port->priv, port->id); in mvpp2_prs_def_flow()
3234 if (!pe) { in mvpp2_prs_def_flow()
3242 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_def_flow()
3243 if (!pe) in mvpp2_prs_def_flow()
3246 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
3247 pe->index = tid; in mvpp2_prs_def_flow()
3250 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
3251 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow()
3254 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
3257 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); in mvpp2_prs_def_flow()
3258 mvpp2_prs_hw_write(port->priv, pe); in mvpp2_prs_def_flow()
3259 kfree(pe); in mvpp2_prs_def_flow()