Lines Matching refs:JME_MISC
488 JME_MISC = 0x0800, enumerator
534 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
535 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
536 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
537 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
538 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
539 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
540 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
541 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
542 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
543 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
544 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
545 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
546 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
547 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
548 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
549 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */