228 	u32 head = IXGBE_READ_REG(hw, IXGBE_VFTDH(ring->reg_idx));  in ixgbevf_get_tx_pending()
229 	u32 tail = IXGBE_READ_REG(hw, IXGBE_VFTDT(ring->reg_idx));  in ixgbevf_get_tx_pending()
405 		       IXGBE_READ_REG(hw, IXGBE_VFTDH(tx_ring->reg_idx)),  in ixgbevf_clean_tx_irq()
406 		       IXGBE_READ_REG(hw, IXGBE_VFTDT(tx_ring->reg_idx)),  in ixgbevf_clean_tx_irq()
1133 			ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx);  in ixgbevf_configure_msix()
1136 			ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx);  in ixgbevf_configure_msix()
1551 	u8 reg_idx = ring->reg_idx;  in ixgbevf_configure_tx_ring()  local
1554 	IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);  in ixgbevf_configure_tx_ring()
1557 	IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(reg_idx), tdba & DMA_BIT_MASK(32));  in ixgbevf_configure_tx_ring()
1558 	IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(reg_idx), tdba >> 32);  in ixgbevf_configure_tx_ring()
1559 	IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(reg_idx),  in ixgbevf_configure_tx_ring()
1563 	IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(reg_idx), 0);  in ixgbevf_configure_tx_ring()
1564 	IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(reg_idx), 0);  in ixgbevf_configure_tx_ring()
1567 	IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(reg_idx),  in ixgbevf_configure_tx_ring()
1572 	IXGBE_WRITE_REG(hw, IXGBE_VFTDH(reg_idx), 0);  in ixgbevf_configure_tx_ring()
1573 	IXGBE_WRITE_REG(hw, IXGBE_VFTDT(reg_idx), 0);  in ixgbevf_configure_tx_ring()
1574 	ring->tail = adapter->io_addr + IXGBE_VFTDT(reg_idx);  in ixgbevf_configure_tx_ring()
1592 	IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), txdctl);  in ixgbevf_configure_tx_ring()
1597 		txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(reg_idx));  in ixgbevf_configure_tx_ring()
1600 		pr_err("Could not enable Tx Queue %d\n", reg_idx);  in ixgbevf_configure_tx_ring()
1656 	u8 reg_idx = ring->reg_idx;  in ixgbevf_disable_rx_queue()  local
1660 	rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx));  in ixgbevf_disable_rx_queue()
1664 	IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(reg_idx), rxdctl);  in ixgbevf_disable_rx_queue()
1669 		rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx));  in ixgbevf_disable_rx_queue()
1674 		       reg_idx);  in ixgbevf_disable_rx_queue()
1683 	u8 reg_idx = ring->reg_idx;  in ixgbevf_rx_desc_queue_enable()  local
1689 		rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx));  in ixgbevf_rx_desc_queue_enable()
1694 		       reg_idx);  in ixgbevf_rx_desc_queue_enable()
1739 	u8 reg_idx = ring->reg_idx;  in ixgbevf_configure_rx_ring()  local
1742 	rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx));  in ixgbevf_configure_rx_ring()
1745 	IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(reg_idx), rdba & DMA_BIT_MASK(32));  in ixgbevf_configure_rx_ring()
1746 	IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(reg_idx), rdba >> 32);  in ixgbevf_configure_rx_ring()
1747 	IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(reg_idx),  in ixgbevf_configure_rx_ring()
1751 	IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(reg_idx),  in ixgbevf_configure_rx_ring()
1755 	IXGBE_WRITE_REG(hw, IXGBE_VFRDH(reg_idx), 0);  in ixgbevf_configure_rx_ring()
1756 	IXGBE_WRITE_REG(hw, IXGBE_VFRDT(reg_idx), 0);  in ixgbevf_configure_rx_ring()
1757 	ring->tail = adapter->io_addr + IXGBE_VFRDT(reg_idx);  in ixgbevf_configure_rx_ring()
1764 	ixgbevf_configure_srrctl(adapter, reg_idx);  in ixgbevf_configure_rx_ring()
1770 	IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(reg_idx), rxdctl);  in ixgbevf_configure_rx_ring()
1973 		adapter->tx_ring[0]->reg_idx = def_q;  in ixgbevf_configure_dcb()
2224 		u8 reg_idx = adapter->tx_ring[i]->reg_idx;  in ixgbevf_down()  local
2226 		IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx),  in ixgbevf_down()
2379 		ring->reg_idx = tx;  in ixgbevf_alloc_queues()
2394 		ring->reg_idx = rx;  in ixgbevf_alloc_queues()