49 	u8     i             = 0;  in ixgbe_dcb_config_rx_arbiter_82598()  local
65 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {  in ixgbe_dcb_config_rx_arbiter_82598()
66 		credit_refill = refill[i];  in ixgbe_dcb_config_rx_arbiter_82598()
67 		credit_max    = max[i];  in ixgbe_dcb_config_rx_arbiter_82598()
71 		if (prio_type[i] == prio_link)  in ixgbe_dcb_config_rx_arbiter_82598()
74 		IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);  in ixgbe_dcb_config_rx_arbiter_82598()
105 	u8     i;  in ixgbe_dcb_config_tx_desc_arbiter_82598()  local
119 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {  in ixgbe_dcb_config_tx_desc_arbiter_82598()
120 		max_credits = max[i];  in ixgbe_dcb_config_tx_desc_arbiter_82598()
122 		reg |= refill[i];  in ixgbe_dcb_config_tx_desc_arbiter_82598()
123 		reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;  in ixgbe_dcb_config_tx_desc_arbiter_82598()
125 		if (prio_type[i] == prio_group)  in ixgbe_dcb_config_tx_desc_arbiter_82598()
128 		if (prio_type[i] == prio_link)  in ixgbe_dcb_config_tx_desc_arbiter_82598()
131 		IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);  in ixgbe_dcb_config_tx_desc_arbiter_82598()
151 	u8 i;  in ixgbe_dcb_config_tx_data_arbiter_82598()  local
162 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {  in ixgbe_dcb_config_tx_data_arbiter_82598()
163 		reg = refill[i];  in ixgbe_dcb_config_tx_data_arbiter_82598()
164 		reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;  in ixgbe_dcb_config_tx_data_arbiter_82598()
165 		reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;  in ixgbe_dcb_config_tx_data_arbiter_82598()
167 		if (prio_type[i] == prio_group)  in ixgbe_dcb_config_tx_data_arbiter_82598()
170 		if (prio_type[i] == prio_link)  in ixgbe_dcb_config_tx_data_arbiter_82598()
173 		IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);  in ixgbe_dcb_config_tx_data_arbiter_82598()
194 	u8  i;  in ixgbe_dcb_config_pfc_82598()  local
212 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {  in ixgbe_dcb_config_pfc_82598()
213 		if (!(pfc_en & (1 << i))) {  in ixgbe_dcb_config_pfc_82598()
214 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);  in ixgbe_dcb_config_pfc_82598()
215 			IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);  in ixgbe_dcb_config_pfc_82598()
219 		fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;  in ixgbe_dcb_config_pfc_82598()
220 		reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;  in ixgbe_dcb_config_pfc_82598()
221 		IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);  in ixgbe_dcb_config_pfc_82598()
222 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);  in ixgbe_dcb_config_pfc_82598()
227 	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)  in ixgbe_dcb_config_pfc_82598()
228 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);  in ixgbe_dcb_config_pfc_82598()
247 	u8  i   = 0;  in ixgbe_dcb_config_tc_stats_82598()  local
251 	for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {  in ixgbe_dcb_config_tc_stats_82598()
252 		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));  in ixgbe_dcb_config_tc_stats_82598()
254 		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);  in ixgbe_dcb_config_tc_stats_82598()
255 		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));  in ixgbe_dcb_config_tc_stats_82598()
257 		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);  in ixgbe_dcb_config_tc_stats_82598()
260 	for (i = 0; i < 8; i++) {  in ixgbe_dcb_config_tc_stats_82598()
261 		reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));  in ixgbe_dcb_config_tc_stats_82598()
262 		reg |= ((0x1010101) * i);  in ixgbe_dcb_config_tc_stats_82598()
263 		IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);  in ixgbe_dcb_config_tc_stats_82598()