726 				adapter->rx_ring[i]->reg_idx = rbase_offset +  in igb_cache_ring_register()
739 			adapter->rx_ring[i]->reg_idx = rbase_offset + i;  in igb_cache_ring_register()
741 			adapter->tx_ring[j]->reg_idx = rbase_offset + j;  in igb_cache_ring_register()
804 		rx_queue = q_vector->rx.ring->reg_idx;  in igb_assign_vector()
806 		tx_queue = q_vector->tx.ring->reg_idx;  in igb_assign_vector()
3272 	int reg_idx = ring->reg_idx;  in igb_configure_tx_ring()  local
3275 	wr32(E1000_TXDCTL(reg_idx), 0);  in igb_configure_tx_ring()
3279 	wr32(E1000_TDLEN(reg_idx),  in igb_configure_tx_ring()
3281 	wr32(E1000_TDBAL(reg_idx),  in igb_configure_tx_ring()
3283 	wr32(E1000_TDBAH(reg_idx), tdba >> 32);  in igb_configure_tx_ring()
3285 	ring->tail = hw->hw_addr + E1000_TDT(reg_idx);  in igb_configure_tx_ring()
3286 	wr32(E1000_TDH(reg_idx), 0);  in igb_configure_tx_ring()
3294 	wr32(E1000_TXDCTL(reg_idx), txdctl);  in igb_configure_tx_ring()
3627 	int reg_idx = ring->reg_idx;  in igb_configure_rx_ring()  local
3631 	wr32(E1000_RXDCTL(reg_idx), 0);  in igb_configure_rx_ring()
3634 	wr32(E1000_RDBAL(reg_idx),  in igb_configure_rx_ring()
3636 	wr32(E1000_RDBAH(reg_idx), rdba >> 32);  in igb_configure_rx_ring()
3637 	wr32(E1000_RDLEN(reg_idx),  in igb_configure_rx_ring()
3641 	ring->tail = hw->hw_addr + E1000_RDT(reg_idx);  in igb_configure_rx_ring()
3642 	wr32(E1000_RDH(reg_idx), 0);  in igb_configure_rx_ring()
3655 	wr32(E1000_SRRCTL(reg_idx), srrctl);  in igb_configure_rx_ring()
3658 	igb_set_vmolr(adapter, reg_idx & 0x7, true);  in igb_configure_rx_ring()
3666 	wr32(E1000_RXDCTL(reg_idx), rxdctl);  in igb_configure_rx_ring()
4635 		mss_l4len_idx |= tx_ring->reg_idx << 4;  in igb_tx_ctxtdesc()
4812 		olinfo_status |= tx_ring->reg_idx << 4;  in igb_tx_olinfo_status()
5556 	wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);  in igb_update_tx_dca()
5576 	wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);  in igb_update_rx_dca()
6526 				rd32(E1000_TDH(tx_ring->reg_idx)),  in igb_clean_tx_irq()