318 	struct e1000_nvm_info *nvm = &hw->nvm;  in igb_init_nvm_params_82575()  local
336 	nvm->word_size = 1 << size;  in igb_init_nvm_params_82575()
337 	nvm->opcode_bits = 8;  in igb_init_nvm_params_82575()
338 	nvm->delay_usec = 1;  in igb_init_nvm_params_82575()
340 	switch (nvm->override) {  in igb_init_nvm_params_82575()
342 		nvm->page_size = 32;  in igb_init_nvm_params_82575()
343 		nvm->address_bits = 16;  in igb_init_nvm_params_82575()
346 		nvm->page_size = 8;  in igb_init_nvm_params_82575()
347 		nvm->address_bits = 8;  in igb_init_nvm_params_82575()
350 		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;  in igb_init_nvm_params_82575()
351 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?  in igb_init_nvm_params_82575()
355 	if (nvm->word_size == (1 << 15))  in igb_init_nvm_params_82575()
356 		nvm->page_size = 128;  in igb_init_nvm_params_82575()
358 	nvm->type = e1000_nvm_eeprom_spi;  in igb_init_nvm_params_82575()
361 	nvm->ops.acquire = igb_acquire_nvm_82575;  in igb_init_nvm_params_82575()
362 	nvm->ops.release = igb_release_nvm_82575;  in igb_init_nvm_params_82575()
363 	nvm->ops.write = igb_write_nvm_spi;  in igb_init_nvm_params_82575()
364 	nvm->ops.validate = igb_validate_nvm_checksum;  in igb_init_nvm_params_82575()
365 	nvm->ops.update = igb_update_nvm_checksum;  in igb_init_nvm_params_82575()
366 	if (nvm->word_size < (1 << 15))  in igb_init_nvm_params_82575()
367 		nvm->ops.read = igb_read_nvm_eerd;  in igb_init_nvm_params_82575()
369 		nvm->ops.read = igb_read_nvm_spi;  in igb_init_nvm_params_82575()
374 		nvm->ops.validate = igb_validate_nvm_checksum_82580;  in igb_init_nvm_params_82575()
375 		nvm->ops.update = igb_update_nvm_checksum_82580;  in igb_init_nvm_params_82575()
379 		nvm->ops.validate = igb_validate_nvm_checksum_i350;  in igb_init_nvm_params_82575()
380 		nvm->ops.update = igb_update_nvm_checksum_i350;  in igb_init_nvm_params_82575()
1694 			ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);  in igb_setup_serdes_link_82575()
2208 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +  in igb_reset_mdicnfg_82580()
2352 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);  in igb_validate_nvm_checksum_with_offset()
2387 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);  in igb_update_nvm_checksum_with_offset()
2395 	ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,  in igb_update_nvm_checksum_with_offset()
2419 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);  in igb_validate_nvm_checksum_82580()
2458 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);  in igb_update_nvm_checksum_82580()
2467 		ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,  in igb_update_nvm_checksum_82580()
2779 	hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);  in igb_get_thermal_sensor_data_generic()
2783 	hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);  in igb_get_thermal_sensor_data_generic()
2793 		hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);  in igb_get_thermal_sensor_data_generic()
2840 	hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);  in igb_init_thermal_sensor_thresh_generic()
2844 	hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);  in igb_init_thermal_sensor_thresh_generic()
2854 		hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);  in igb_init_thermal_sensor_thresh_generic()