53 		hw->aq.asq.tail = I40E_VF_ATQT1;  in i40e_adminq_init_regs()
54 		hw->aq.asq.head = I40E_VF_ATQH1;  in i40e_adminq_init_regs()
55 		hw->aq.asq.len  = I40E_VF_ATQLEN1;  in i40e_adminq_init_regs()
56 		hw->aq.asq.bal  = I40E_VF_ATQBAL1;  in i40e_adminq_init_regs()
57 		hw->aq.asq.bah  = I40E_VF_ATQBAH1;  in i40e_adminq_init_regs()
58 		hw->aq.arq.tail = I40E_VF_ARQT1;  in i40e_adminq_init_regs()
59 		hw->aq.arq.head = I40E_VF_ARQH1;  in i40e_adminq_init_regs()
60 		hw->aq.arq.len  = I40E_VF_ARQLEN1;  in i40e_adminq_init_regs()
61 		hw->aq.arq.bal  = I40E_VF_ARQBAL1;  in i40e_adminq_init_regs()
62 		hw->aq.arq.bah  = I40E_VF_ARQBAH1;  in i40e_adminq_init_regs()
74 	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,  in i40e_alloc_adminq_asq_ring()
76 					 (hw->aq.num_asq_entries *  in i40e_alloc_adminq_asq_ring()
82 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,  in i40e_alloc_adminq_asq_ring()
83 					  (hw->aq.num_asq_entries *  in i40e_alloc_adminq_asq_ring()
86 		i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);  in i40e_alloc_adminq_asq_ring()
101 	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,  in i40e_alloc_adminq_arq_ring()
103 					 (hw->aq.num_arq_entries *  in i40e_alloc_adminq_arq_ring()
119 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);  in i40e_free_adminq_asq()
131 	i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);  in i40e_free_adminq_arq()
150 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,  in i40e_alloc_arq_bufs()
151 		(hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));  in i40e_alloc_arq_bufs()
154 	hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;  in i40e_alloc_arq_bufs()
157 	for (i = 0; i < hw->aq.num_arq_entries; i++) {  in i40e_alloc_arq_bufs()
158 		bi = &hw->aq.arq.r.arq_bi[i];  in i40e_alloc_arq_bufs()
161 						 hw->aq.arq_buf_size,  in i40e_alloc_arq_bufs()
167 		desc = I40E_ADMINQ_DESC(hw->aq.arq, i);  in i40e_alloc_arq_bufs()
170 		if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)  in i40e_alloc_arq_bufs()
195 		i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);  in i40e_alloc_arq_bufs()
196 	i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);  in i40e_alloc_arq_bufs()
212 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,  in i40e_alloc_asq_bufs()
213 		(hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));  in i40e_alloc_asq_bufs()
216 	hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;  in i40e_alloc_asq_bufs()
219 	for (i = 0; i < hw->aq.num_asq_entries; i++) {  in i40e_alloc_asq_bufs()
220 		bi = &hw->aq.asq.r.asq_bi[i];  in i40e_alloc_asq_bufs()
223 						 hw->aq.asq_buf_size,  in i40e_alloc_asq_bufs()
235 		i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);  in i40e_alloc_asq_bufs()
236 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);  in i40e_alloc_asq_bufs()
250 	for (i = 0; i < hw->aq.num_arq_entries; i++)  in i40e_free_arq_bufs()
251 		i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);  in i40e_free_arq_bufs()
254 	i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);  in i40e_free_arq_bufs()
257 	i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);  in i40e_free_arq_bufs()
269 	for (i = 0; i < hw->aq.num_asq_entries; i++)  in i40e_free_asq_bufs()
270 		if (hw->aq.asq.r.asq_bi[i].pa)  in i40e_free_asq_bufs()
271 			i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);  in i40e_free_asq_bufs()
274 	i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);  in i40e_free_asq_bufs()
277 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);  in i40e_free_asq_bufs()
280 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);  in i40e_free_asq_bufs()
295 	wr32(hw, hw->aq.asq.head, 0);  in i40e_config_asq_regs()
296 	wr32(hw, hw->aq.asq.tail, 0);  in i40e_config_asq_regs()
299 	wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |  in i40e_config_asq_regs()
301 	wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));  in i40e_config_asq_regs()
302 	wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));  in i40e_config_asq_regs()
305 	reg = rd32(hw, hw->aq.asq.bal);  in i40e_config_asq_regs()
306 	if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))  in i40e_config_asq_regs()
324 	wr32(hw, hw->aq.arq.head, 0);  in i40e_config_arq_regs()
325 	wr32(hw, hw->aq.arq.tail, 0);  in i40e_config_arq_regs()
328 	wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |  in i40e_config_arq_regs()
330 	wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));  in i40e_config_arq_regs()
331 	wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));  in i40e_config_arq_regs()
334 	wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);  in i40e_config_arq_regs()
337 	reg = rd32(hw, hw->aq.arq.bal);  in i40e_config_arq_regs()
338 	if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))  in i40e_config_arq_regs()
361 	if (hw->aq.asq.count > 0) {  in i40e_init_asq()
368 	if ((hw->aq.num_asq_entries == 0) ||  in i40e_init_asq()
369 	    (hw->aq.asq_buf_size == 0)) {  in i40e_init_asq()
374 	hw->aq.asq.next_to_use = 0;  in i40e_init_asq()
375 	hw->aq.asq.next_to_clean = 0;  in i40e_init_asq()
393 	hw->aq.asq.count = hw->aq.num_asq_entries;  in i40e_init_asq()
420 	if (hw->aq.arq.count > 0) {  in i40e_init_arq()
427 	if ((hw->aq.num_arq_entries == 0) ||  in i40e_init_arq()
428 	    (hw->aq.arq_buf_size == 0)) {  in i40e_init_arq()
433 	hw->aq.arq.next_to_use = 0;  in i40e_init_arq()
434 	hw->aq.arq.next_to_clean = 0;  in i40e_init_arq()
452 	hw->aq.arq.count = hw->aq.num_arq_entries;  in i40e_init_arq()
472 	mutex_lock(&hw->aq.asq_mutex);  in i40e_shutdown_asq()
474 	if (hw->aq.asq.count == 0) {  in i40e_shutdown_asq()
480 	wr32(hw, hw->aq.asq.head, 0);  in i40e_shutdown_asq()
481 	wr32(hw, hw->aq.asq.tail, 0);  in i40e_shutdown_asq()
482 	wr32(hw, hw->aq.asq.len, 0);  in i40e_shutdown_asq()
483 	wr32(hw, hw->aq.asq.bal, 0);  in i40e_shutdown_asq()
484 	wr32(hw, hw->aq.asq.bah, 0);  in i40e_shutdown_asq()
486 	hw->aq.asq.count = 0; /* to indicate uninitialized queue */  in i40e_shutdown_asq()
492 	mutex_unlock(&hw->aq.asq_mutex);  in i40e_shutdown_asq()
506 	mutex_lock(&hw->aq.arq_mutex);  in i40e_shutdown_arq()
508 	if (hw->aq.arq.count == 0) {  in i40e_shutdown_arq()
514 	wr32(hw, hw->aq.arq.head, 0);  in i40e_shutdown_arq()
515 	wr32(hw, hw->aq.arq.tail, 0);  in i40e_shutdown_arq()
516 	wr32(hw, hw->aq.arq.len, 0);  in i40e_shutdown_arq()
517 	wr32(hw, hw->aq.arq.bal, 0);  in i40e_shutdown_arq()
518 	wr32(hw, hw->aq.arq.bah, 0);  in i40e_shutdown_arq()
520 	hw->aq.arq.count = 0; /* to indicate uninitialized queue */  in i40e_shutdown_arq()
526 	mutex_unlock(&hw->aq.arq_mutex);  in i40e_shutdown_arq()
546 	if ((hw->aq.num_arq_entries == 0) ||  in i40evf_init_adminq()
547 	    (hw->aq.num_asq_entries == 0) ||  in i40evf_init_adminq()
548 	    (hw->aq.arq_buf_size == 0) ||  in i40evf_init_adminq()
549 	    (hw->aq.asq_buf_size == 0)) {  in i40evf_init_adminq()
558 	hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;  in i40evf_init_adminq()
609 	struct i40e_adminq_ring *asq = &(hw->aq.asq);  in i40e_clean_asq()
617 	while (rd32(hw, hw->aq.asq.head) != ntc) {  in i40e_clean_asq()
619 			   "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));  in i40e_clean_asq()
654 	return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;  in i40evf_asq_done()
683 	mutex_lock(&hw->aq.asq_mutex);  in i40evf_asq_send_command()
685 	if (hw->aq.asq.count == 0) {  in i40evf_asq_send_command()
692 	hw->aq.asq_last_status = I40E_AQ_RC_OK;  in i40evf_asq_send_command()
694 	val = rd32(hw, hw->aq.asq.head);  in i40evf_asq_send_command()
695 	if (val >= hw->aq.num_asq_entries) {  in i40evf_asq_send_command()
702 	details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);  in i40evf_asq_send_command()
724 	if (buff_size > hw->aq.asq_buf_size) {  in i40evf_asq_send_command()
757 	desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);  in i40evf_asq_send_command()
764 		dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);  in i40evf_asq_send_command()
782 	(hw->aq.asq.next_to_use)++;  in i40evf_asq_send_command()
783 	if (hw->aq.asq.next_to_use == hw->aq.asq.count)  in i40evf_asq_send_command()
784 		hw->aq.asq.next_to_use = 0;  in i40evf_asq_send_command()
786 		wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);  in i40evf_asq_send_command()
802 		} while (total_delay < hw->aq.asq_cmd_timeout);  in i40evf_asq_send_command()
825 		hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;  in i40evf_asq_send_command()
847 	mutex_unlock(&hw->aq.asq_mutex);  in i40evf_asq_send_command()
882 	u16 ntc = hw->aq.arq.next_to_clean;  in i40evf_clean_arq_element()
891 	mutex_lock(&hw->aq.arq_mutex);  in i40evf_clean_arq_element()
893 	if (hw->aq.arq.count == 0) {  in i40evf_clean_arq_element()
901 	ntu = (rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK);  in i40evf_clean_arq_element()
909 	desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);  in i40evf_clean_arq_element()
915 		hw->aq.arq_last_status =  in i40evf_clean_arq_element()
920 			   hw->aq.arq_last_status);  in i40evf_clean_arq_element()
927 		memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,  in i40evf_clean_arq_element()
932 			hw->aq.arq_buf_size);  in i40evf_clean_arq_element()
938 	bi = &hw->aq.arq.r.arq_bi[ntc];  in i40evf_clean_arq_element()
942 	if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)  in i40evf_clean_arq_element()
949 	wr32(hw, hw->aq.arq.tail, ntc);  in i40evf_clean_arq_element()
952 	if (ntc == hw->aq.num_arq_entries)  in i40evf_clean_arq_element()
954 	hw->aq.arq.next_to_clean = ntc;  in i40evf_clean_arq_element()
955 	hw->aq.arq.next_to_use = ntu;  in i40evf_clean_arq_element()
960 		*pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);  in i40evf_clean_arq_element()
963 	mutex_unlock(&hw->aq.arq_mutex);  in i40evf_clean_arq_element()
971 	hw->aq.asq.next_to_use = 0;  in i40evf_resume_aq()
972 	hw->aq.asq.next_to_clean = 0;  in i40evf_resume_aq()
976 	hw->aq.arq.next_to_use = 0;  in i40evf_resume_aq()
977 	hw->aq.arq.next_to_clean = 0;  in i40evf_resume_aq()