Lines Matching refs:u32
59 u32 vm_def_vlan_id;
60 u32 vm_def_vlan_cfi;
61 u32 vm_def_vlan_pri;
65 u32 tbl_tcam_data_high;
66 u32 tbl_tcam_data_low;
74 u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM];
78 u32 tbl_ucast_old_en;
79 u32 tbl_ucast_item_vld;
80 u32 tbl_ucast_mac_discard;
81 u32 tbl_ucast_dvc;
82 u32 tbl_ucast_out_port;
86 u32 tbl_line_mac_discard;
87 u32 tbl_line_dvc;
88 u32 tbl_line_out_port;
158 u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT];
191 u32 xid_xge_ecc_err_int_src;
192 u32 xid_xge_fsm_timout_int_src;
193 u32 sbm_xge_lnk_fsm_timout_int_src;
194 u32 sbm_xge_lnk_ecc_2bit_int_src;
195 u32 sbm_xge_mib_req_failed_int_src;
196 u32 sbm_xge_mib_req_fsm_timout_int_src;
197 u32 sbm_xge_mib_rels_fsm_timout_int_src;
198 u32 sbm_xge_sram_ecc_2bit_int_src;
199 u32 sbm_xge_mib_buf_sum_err_int_src;
200 u32 sbm_xge_mib_req_extra_int_src;
201 u32 sbm_xge_mib_rels_extra_int_src;
202 u32 voq_xge_start_to_over_0_int_src;
203 u32 voq_xge_start_to_over_1_int_src;
204 u32 voq_xge_ecc_err_int_src;
208 u32 xid_ppe_fsm_timout_int_src;
209 u32 sbm_ppe_lnk_fsm_timout_int_src;
210 u32 sbm_ppe_lnk_ecc_2bit_int_src;
211 u32 sbm_ppe_mib_req_failed_int_src;
212 u32 sbm_ppe_mib_req_fsm_timout_int_src;
213 u32 sbm_ppe_mib_rels_fsm_timout_int_src;
214 u32 sbm_ppe_sram_ecc_2bit_int_src;
215 u32 sbm_ppe_mib_buf_sum_err_int_src;
216 u32 sbm_ppe_mib_req_extra_int_src;
217 u32 sbm_ppe_mib_rels_extra_int_src;
218 u32 voq_ppe_start_to_over_0_int_src;
219 u32 voq_ppe_ecc_err_int_src;
220 u32 xod_ppe_fifo_rd_empty_int_src;
221 u32 xod_ppe_fifo_wr_full_int_src;
225 u32 xid_rocee_fsm_timout_int_src;
226 u32 sbm_rocee_lnk_fsm_timout_int_src;
227 u32 sbm_rocee_lnk_ecc_2bit_int_src;
228 u32 sbm_rocee_mib_req_failed_int_src;
229 u32 sbm_rocee_mib_req_fsm_timout_int_src;
230 u32 sbm_rocee_mib_rels_fsm_timout_int_src;
231 u32 sbm_rocee_sram_ecc_2bit_int_src;
232 u32 sbm_rocee_mib_buf_sum_err_int_src;
233 u32 sbm_rocee_mib_req_extra_int_src;
234 u32 sbm_rocee_mib_rels_extra_int_src;
235 u32 voq_rocee_start_to_over_0_int_src;
236 u32 voq_rocee_ecc_err_int_src;
240 u32 tbl_da0_mis_src;
241 u32 tbl_da1_mis_src;
242 u32 tbl_da2_mis_src;
243 u32 tbl_da3_mis_src;
244 u32 tbl_da4_mis_src;
245 u32 tbl_da5_mis_src;
246 u32 tbl_da6_mis_src;
247 u32 tbl_da7_mis_src;
248 u32 tbl_sa_mis_src;
249 u32 tbl_old_sech_end_src;
250 u32 lram_ecc_err1_src;
251 u32 lram_ecc_err2_src;
252 u32 tram_ecc_err1_src;
253 u32 tram_ecc_err2_src;
254 u32 tbl_ucast_bcast_xge0_src;
255 u32 tbl_ucast_bcast_xge1_src;
256 u32 tbl_ucast_bcast_xge2_src;
257 u32 tbl_ucast_bcast_xge3_src;
258 u32 tbl_ucast_bcast_xge4_src;
259 u32 tbl_ucast_bcast_xge5_src;
260 u32 tbl_ucast_bcast_ppe_src;
261 u32 tbl_ucast_bcast_rocee_src;
287 u32 desc_num; /* desc num per queue*/
288 u32 buf_size; /* ring buffer size */
293 u32 dsaf_ver;
317 u32 val;
321 u32 port:4; /* port id, */
323 u32 vlan:12; /* vlan id */
324 u32 mac_5:8;
325 u32 mac_4:8;
328 u32 val;
343 u32 tab_tcam_addr) in hns_dsaf_tbl_tcam_addr_cfg()
352 u32 o_tbl_pul; in hns_dsaf_tbl_tcam_load_pul()
362 u32 tab_line_addr) in hns_dsaf_tbl_line_addr_cfg()
402 void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val);
404 void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val);
406 void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val);
413 void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val);
414 void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val);
416 u32 port, u32 val);
418 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 inode_num);
424 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data);
426 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en);