219 	writel_relaxed(val, priv->base + GE_PORT_MODE);  in hip04_config_port()
222 	writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);  in hip04_config_port()
225 	writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG);  in hip04_config_port()
246 	writel_relaxed(val, priv->base + PPE_CFG_STS_MODE);  in hip04_config_fifo()
253 	writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN);  in hip04_config_fifo()
264 	writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);  in hip04_config_fifo()
267 	writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);  in hip04_config_fifo()
270 	writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);  in hip04_config_fifo()
273 	writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);  in hip04_config_fifo()
276 	writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);  in hip04_config_fifo()
279 	writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);  in hip04_config_fifo()
283 	writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);  in hip04_config_fifo()
286 	writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);  in hip04_config_fifo()
290 	writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);  in hip04_config_fifo()
293 	writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);  in hip04_config_fifo()
304 	writel_relaxed(val, priv->base + GE_PORT_EN);  in hip04_mac_enable()
308 	writel_relaxed(val, priv->base + PPE_RINT);  in hip04_mac_enable()
312 	writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT);  in hip04_mac_enable()
316 	writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);  in hip04_mac_enable()
326 	writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);  in hip04_mac_disable()
331 	writel_relaxed(val, priv->base + GE_PORT_EN);  in hip04_mac_disable()
353 	writel_relaxed(((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])),  in hip04_update_mac_address()
355 	writel_relaxed(((ndev->dev_addr[2] << 24) | (ndev->dev_addr[3] << 16) |  in hip04_update_mac_address()
471 			writel_relaxed(DEF_INT_MASK & ~RCV_INT,  in hip04_mac_start_xmit()
553 		writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);  in hip04_rx_poll()
575 	writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT);  in hip04_mac_interrupt()
592 		writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);  in hip04_mac_interrupt()
609 		writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);  in tx_done()