193 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_config_port()  local
196 	priv->speed = speed;  in hip04_config_port()
197 	priv->duplex = duplex;  in hip04_config_port()
199 	switch (priv->phy_mode) {  in hip04_config_port()
219 	writel_relaxed(val, priv->base + GE_PORT_MODE);  in hip04_config_port()
222 	writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);  in hip04_config_port()
225 	writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG);  in hip04_config_port()
228 static void hip04_reset_ppe(struct hip04_priv *priv)  in hip04_reset_ppe()  argument
233 		regmap_read(priv->map, priv->port * 4 + PPE_CURR_BUF_CNT, &val);  in hip04_reset_ppe()
234 		regmap_read(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, &tmp);  in hip04_reset_ppe()
240 static void hip04_config_fifo(struct hip04_priv *priv)  in hip04_config_fifo()  argument
244 	val = readl_relaxed(priv->base + PPE_CFG_STS_MODE);  in hip04_config_fifo()
246 	writel_relaxed(val, priv->base + PPE_CFG_STS_MODE);  in hip04_config_fifo()
248 	val = BIT(priv->port);  in hip04_config_fifo()
249 	regmap_write(priv->map, priv->port * 4 + PPE_CFG_POOL_GRP, val);  in hip04_config_fifo()
251 	val = priv->port << PPE_CFG_QOS_VMID_GRP_SHIFT;  in hip04_config_fifo()
253 	writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN);  in hip04_config_fifo()
256 	regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_BUF_SIZE, val);  in hip04_config_fifo()
260 	val |= priv->chan << PPE_CFG_RX_START_SHIFT;  in hip04_config_fifo()
261 	regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_FIFO_SIZE, val);  in hip04_config_fifo()
264 	writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);  in hip04_config_fifo()
267 	writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);  in hip04_config_fifo()
270 	writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);  in hip04_config_fifo()
273 	writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);  in hip04_config_fifo()
276 	writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);  in hip04_config_fifo()
279 	writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);  in hip04_config_fifo()
281 	val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG);  in hip04_config_fifo()
283 	writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);  in hip04_config_fifo()
286 	writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);  in hip04_config_fifo()
288 	val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG);  in hip04_config_fifo()
290 	writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);  in hip04_config_fifo()
293 	writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);  in hip04_config_fifo()
298 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_mac_enable()  local
302 	val = readl_relaxed(priv->base + GE_PORT_EN);  in hip04_mac_enable()
304 	writel_relaxed(val, priv->base + GE_PORT_EN);  in hip04_mac_enable()
308 	writel_relaxed(val, priv->base + PPE_RINT);  in hip04_mac_enable()
312 	writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT);  in hip04_mac_enable()
315 	priv->reg_inten = DEF_INT_MASK;  in hip04_mac_enable()
316 	writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);  in hip04_mac_enable()
321 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_mac_disable()  local
325 	priv->reg_inten &= ~(DEF_INT_MASK);  in hip04_mac_disable()
326 	writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);  in hip04_mac_disable()
329 	val = readl_relaxed(priv->base + GE_PORT_EN);  in hip04_mac_disable()
331 	writel_relaxed(val, priv->base + GE_PORT_EN);  in hip04_mac_disable()
334 static void hip04_set_xmit_desc(struct hip04_priv *priv, dma_addr_t phys)  in hip04_set_xmit_desc()  argument
336 	writel(phys, priv->base + PPE_CFG_CPU_ADD_ADDR);  in hip04_set_xmit_desc()
339 static void hip04_set_recv_desc(struct hip04_priv *priv, dma_addr_t phys)  in hip04_set_recv_desc()  argument
341 	regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, phys);  in hip04_set_recv_desc()
344 static u32 hip04_recv_cnt(struct hip04_priv *priv)  in hip04_recv_cnt()  argument
346 	return readl(priv->base + PPE_HIS_RX_PKT_CNT);  in hip04_recv_cnt()
351 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_update_mac_address()  local
354 		       priv->base + GE_STATION_MAC_ADDRESS);  in hip04_update_mac_address()
357 		       priv->base + GE_STATION_MAC_ADDRESS + 4);  in hip04_update_mac_address()
369 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_tx_reclaim()  local
370 	unsigned tx_tail = priv->tx_tail;  in hip04_tx_reclaim()
376 	count = tx_count(ACCESS_ONCE(priv->tx_head), tx_tail);  in hip04_tx_reclaim()
381 		desc = &priv->tx_desc[tx_tail];  in hip04_tx_reclaim()
389 		if (priv->tx_phys[tx_tail]) {  in hip04_tx_reclaim()
390 			dma_unmap_single(&ndev->dev, priv->tx_phys[tx_tail],  in hip04_tx_reclaim()
391 					 priv->tx_skb[tx_tail]->len,  in hip04_tx_reclaim()
393 			priv->tx_phys[tx_tail] = 0;  in hip04_tx_reclaim()
396 		bytes_compl += priv->tx_skb[tx_tail]->len;  in hip04_tx_reclaim()
397 		dev_kfree_skb(priv->tx_skb[tx_tail]);  in hip04_tx_reclaim()
398 		priv->tx_skb[tx_tail] = NULL;  in hip04_tx_reclaim()
403 	priv->tx_tail = tx_tail;  in hip04_tx_reclaim()
416 static void hip04_start_tx_timer(struct hip04_priv *priv)  in hip04_start_tx_timer()  argument
418 	unsigned long ns = priv->tx_coalesce_usecs * NSEC_PER_USEC / 2;  in hip04_start_tx_timer()
421 	hrtimer_start_range_ns(&priv->tx_coalesce_timer, ns_to_ktime(ns),  in hip04_start_tx_timer()
427 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_mac_start_xmit()  local
429 	unsigned int tx_head = priv->tx_head, count;  in hip04_mac_start_xmit()
430 	struct tx_desc *desc = &priv->tx_desc[tx_head];  in hip04_mac_start_xmit()
434 	count = tx_count(tx_head, ACCESS_ONCE(priv->tx_tail));  in hip04_mac_start_xmit()
446 	priv->tx_skb[tx_head] = skb;  in hip04_mac_start_xmit()
447 	priv->tx_phys[tx_head] = phys;  in hip04_mac_start_xmit()
451 	phys = priv->tx_desc_dma + tx_head * sizeof(struct tx_desc);  in hip04_mac_start_xmit()
455 	hip04_set_xmit_desc(priv, phys);  in hip04_mac_start_xmit()
456 	priv->tx_head = TX_NEXT(tx_head);  in hip04_mac_start_xmit()
467 	if (count >= priv->tx_coalesce_frames) {  in hip04_mac_start_xmit()
468 		if (napi_schedule_prep(&priv->napi)) {  in hip04_mac_start_xmit()
470 			priv->reg_inten &= ~(RCV_INT);  in hip04_mac_start_xmit()
472 				       priv->base + PPE_INTEN);  in hip04_mac_start_xmit()
473 			hrtimer_cancel(&priv->tx_coalesce_timer);  in hip04_mac_start_xmit()
474 			__napi_schedule(&priv->napi);  in hip04_mac_start_xmit()
476 	} else if (!hrtimer_is_queued(&priv->tx_coalesce_timer)) {  in hip04_mac_start_xmit()
478 		hip04_start_tx_timer(priv);  in hip04_mac_start_xmit()
486 	struct hip04_priv *priv = container_of(napi, struct hip04_priv, napi);  in hip04_rx_poll()  local
487 	struct net_device *ndev = priv->ndev;  in hip04_rx_poll()
489 	unsigned int cnt = hip04_recv_cnt(priv);  in hip04_rx_poll()
501 		buf = priv->rx_buf[priv->rx_head];  in hip04_rx_poll()
502 		skb = build_skb(buf, priv->rx_buf_size);  in hip04_rx_poll()
506 		dma_unmap_single(&ndev->dev, priv->rx_phys[priv->rx_head],  in hip04_rx_poll()
508 		priv->rx_phys[priv->rx_head] = 0;  in hip04_rx_poll()
525 			napi_gro_receive(&priv->napi, skb);  in hip04_rx_poll()
531 		buf = netdev_alloc_frag(priv->rx_buf_size);  in hip04_rx_poll()
538 		priv->rx_buf[priv->rx_head] = buf;  in hip04_rx_poll()
539 		priv->rx_phys[priv->rx_head] = phys;  in hip04_rx_poll()
540 		hip04_set_recv_desc(priv, phys);  in hip04_rx_poll()
542 		priv->rx_head = RX_NEXT(priv->rx_head);  in hip04_rx_poll()
547 			cnt = hip04_recv_cnt(priv);  in hip04_rx_poll()
550 	if (!(priv->reg_inten & RCV_INT)) {  in hip04_rx_poll()
552 		priv->reg_inten |= RCV_INT;  in hip04_rx_poll()
553 		writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);  in hip04_rx_poll()
560 		hip04_start_tx_timer(priv);  in hip04_rx_poll()
568 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_mac_interrupt()  local
570 	u32 ists = readl_relaxed(priv->base + PPE_INTSTS);  in hip04_mac_interrupt()
575 	writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT);  in hip04_mac_interrupt()
589 	if (ists & RCV_INT && napi_schedule_prep(&priv->napi)) {  in hip04_mac_interrupt()
591 		priv->reg_inten &= ~(RCV_INT);  in hip04_mac_interrupt()
592 		writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);  in hip04_mac_interrupt()
593 		hrtimer_cancel(&priv->tx_coalesce_timer);  in hip04_mac_interrupt()
594 		__napi_schedule(&priv->napi);  in hip04_mac_interrupt()
602 	struct hip04_priv *priv;  in tx_done()  local
604 	priv = container_of(hrtimer, struct hip04_priv, tx_coalesce_timer);  in tx_done()
606 	if (napi_schedule_prep(&priv->napi)) {  in tx_done()
608 		priv->reg_inten &= ~(RCV_INT);  in tx_done()
609 		writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);  in tx_done()
610 		__napi_schedule(&priv->napi);  in tx_done()
618 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_adjust_link()  local
619 	struct phy_device *phy = priv->phy;  in hip04_adjust_link()
621 	if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) {  in hip04_adjust_link()
629 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_mac_open()  local
632 	priv->rx_head = 0;  in hip04_mac_open()
633 	priv->tx_head = 0;  in hip04_mac_open()
634 	priv->tx_tail = 0;  in hip04_mac_open()
635 	hip04_reset_ppe(priv);  in hip04_mac_open()
640 		phys = dma_map_single(&ndev->dev, priv->rx_buf[i],  in hip04_mac_open()
645 		priv->rx_phys[i] = phys;  in hip04_mac_open()
646 		hip04_set_recv_desc(priv, phys);  in hip04_mac_open()
649 	if (priv->phy)  in hip04_mac_open()
650 		phy_start(priv->phy);  in hip04_mac_open()
655 	napi_enable(&priv->napi);  in hip04_mac_open()
662 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_mac_stop()  local
665 	napi_disable(&priv->napi);  in hip04_mac_stop()
669 	hip04_reset_ppe(priv);  in hip04_mac_stop()
671 	if (priv->phy)  in hip04_mac_stop()
672 		phy_stop(priv->phy);  in hip04_mac_stop()
675 		if (priv->rx_phys[i]) {  in hip04_mac_stop()
676 			dma_unmap_single(&ndev->dev, priv->rx_phys[i],  in hip04_mac_stop()
678 			priv->rx_phys[i] = 0;  in hip04_mac_stop()
687 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_timeout()  local
689 	schedule_work(&priv->tx_timeout_task);  in hip04_timeout()
694 	struct hip04_priv *priv;  in hip04_tx_timeout_task()  local
696 	priv = container_of(work, struct hip04_priv, tx_timeout_task);  in hip04_tx_timeout_task()
697 	hip04_mac_stop(priv->ndev);  in hip04_tx_timeout_task()
698 	hip04_mac_open(priv->ndev);  in hip04_tx_timeout_task()
709 	struct hip04_priv *priv = netdev_priv(netdev);  in hip04_get_coalesce()  local
711 	ec->tx_coalesce_usecs = priv->tx_coalesce_usecs;  in hip04_get_coalesce()
712 	ec->tx_max_coalesced_frames = priv->tx_coalesce_frames;  in hip04_get_coalesce()
720 	struct hip04_priv *priv = netdev_priv(netdev);  in hip04_set_coalesce()  local
742 	priv->tx_coalesce_usecs = ec->tx_coalesce_usecs;  in hip04_set_coalesce()
743 	priv->tx_coalesce_frames = ec->tx_max_coalesced_frames;  in hip04_set_coalesce()
774 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_alloc_ring()  local
777 	priv->tx_desc = dma_alloc_coherent(d,  in hip04_alloc_ring()
779 					   &priv->tx_desc_dma, GFP_KERNEL);  in hip04_alloc_ring()
780 	if (!priv->tx_desc)  in hip04_alloc_ring()
783 	priv->rx_buf_size = RX_BUF_SIZE +  in hip04_alloc_ring()
786 		priv->rx_buf[i] = netdev_alloc_frag(priv->rx_buf_size);  in hip04_alloc_ring()
787 		if (!priv->rx_buf[i])  in hip04_alloc_ring()
796 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_free_ring()  local
800 		if (priv->rx_buf[i])  in hip04_free_ring()
801 			skb_free_frag(priv->rx_buf[i]);  in hip04_free_ring()
804 		if (priv->tx_skb[i])  in hip04_free_ring()
805 			dev_kfree_skb_any(priv->tx_skb[i]);  in hip04_free_ring()
808 			  priv->tx_desc, priv->tx_desc_dma);  in hip04_free_ring()
817 	struct hip04_priv *priv;  in hip04_mac_probe()  local
826 	priv = netdev_priv(ndev);  in hip04_mac_probe()
827 	priv->ndev = ndev;  in hip04_mac_probe()
831 	priv->base = devm_ioremap_resource(d, res);  in hip04_mac_probe()
832 	if (IS_ERR(priv->base)) {  in hip04_mac_probe()
833 		ret = PTR_ERR(priv->base);  in hip04_mac_probe()
843 	priv->port = arg.args[0];  in hip04_mac_probe()
844 	priv->chan = arg.args[1] * RX_DESC_NUM;  in hip04_mac_probe()
846 	hrtimer_init(&priv->tx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);  in hip04_mac_probe()
854 	priv->tx_coalesce_frames = TX_DESC_NUM * 3 / 4;  in hip04_mac_probe()
855 	priv->tx_coalesce_usecs = 200;  in hip04_mac_probe()
856 	priv->tx_coalesce_timer.function = tx_done;  in hip04_mac_probe()
858 	priv->map = syscon_node_to_regmap(arg.np);  in hip04_mac_probe()
859 	if (IS_ERR(priv->map)) {  in hip04_mac_probe()
861 		ret = PTR_ERR(priv->map);  in hip04_mac_probe()
865 	priv->phy_mode = of_get_phy_mode(node);  in hip04_mac_probe()
866 	if (priv->phy_mode < 0) {  in hip04_mac_probe()
885 	priv->phy_node = of_parse_phandle(node, "phy-handle", 0);  in hip04_mac_probe()
886 	if (priv->phy_node) {  in hip04_mac_probe()
887 		priv->phy = of_phy_connect(ndev, priv->phy_node,  in hip04_mac_probe()
889 					   0, priv->phy_mode);  in hip04_mac_probe()
890 		if (!priv->phy) {  in hip04_mac_probe()
896 	INIT_WORK(&priv->tx_timeout_task, hip04_tx_timeout_task);  in hip04_mac_probe()
904 	netif_napi_add(ndev, &priv->napi, hip04_rx_poll, NAPI_POLL_WEIGHT);  in hip04_mac_probe()
907 	hip04_reset_ppe(priv);  in hip04_mac_probe()
908 	if (priv->phy_mode == PHY_INTERFACE_MODE_MII)  in hip04_mac_probe()
911 	hip04_config_fifo(priv);  in hip04_mac_probe()
932 	of_node_put(priv->phy_node);  in hip04_mac_probe()
940 	struct hip04_priv *priv = netdev_priv(ndev);  in hip04_remove()  local
943 	if (priv->phy)  in hip04_remove()
944 		phy_disconnect(priv->phy);  in hip04_remove()
949 	of_node_put(priv->phy_node);  in hip04_remove()
950 	cancel_work_sync(&priv->tx_timeout_task);  in hip04_remove()