Lines Matching refs:u16
60 u16 uescr; /* UCC Ethernet statistics control reg */
86 u16 txcf; /* Total number of PAUSE control frames
455 u16 cpucount0; /* CPU packet counter */
456 u16 cpucount1; /* CPU packet counter */
457 u16 cecount0; /* QE packet counter */
458 u16 cecount1; /* QE packet counter */
459 u16 cpucount2; /* CPU packet counter */
460 u16 cpucount3; /* CPU packet counter */
461 u16 cecount2; /* QE packet counter */
462 u16 cecount3; /* QE packet counter */
463 u16 cpucount4; /* CPU packet counter */
464 u16 cpucount5; /* CPU packet counter */
465 u16 cecount4; /* QE packet counter */
466 u16 cecount5; /* QE packet counter */
467 u16 cpucount6; /* CPU packet counter */
468 u16 cpucount7; /* CPU packet counter */
469 u16 cecount6; /* QE packet counter */
470 u16 cecount7; /* QE packet counter */
476 u16 nortsrbytetime; /* normalized value of byte time in tsr units */
571 u16 temoder;
597 u16 typeorlen; /* cutoff point less than which, type/len field
608 u16 mrblr; /* max receive buffer length reg. */
611 u16 mflr; /* max frame length reg. */
612 u16 minflr; /* min frame length reg. */
613 u16 maxd1; /* max dma1 length reg. */
614 u16 maxd2; /* max dma2 length reg. */
618 u16 vlantype; /* vlan type */
619 u16 vlantci; /* default vlan tci */
634 u16 resinit5;
662 u16 h; /* address (MSB) */
663 u16 m; /* address */
664 u16 l; /* address (LSB) */
765 u16 txcf; /* Total number of PAUSE control frames
1072 u16 vid;
1084 u16 typeorlen;
1094 u16 nortsrbytetime;
1119 u16 maxFrameLength;
1120 u16 minFrameLength;
1121 u16 maxD1Length;
1122 u16 maxD2Length;
1123 u16 vlantype;
1124 u16 vlantci;
1127 u16 pausePeriod;
1128 u16 extensionField;
1137 u16 bdRingLenTx[NUM_TX_QUEUES];
1138 u16 bdRingLenRx[NUM_RX_QUEUES];
1194 u16 cpucount[NUM_TX_QUEUES];
1195 u16 __iomem *p_cpucount[NUM_TX_QUEUES];
1212 u16 skb_curtx[NUM_TX_QUEUES];
1213 u16 skb_currx[NUM_RX_QUEUES];
1215 u16 skb_dirtytx[NUM_TX_QUEUES];
1233 u16 pause_period, u16 extension_field,