659 #define DE4X5_ALIGN4      ((u_long)4 - 1)     /* 1 longword align */
660 #define DE4X5_ALIGN8      ((u_long)8 - 1)     /* 2 longword align */
661 #define DE4X5_ALIGN16     ((u_long)16 - 1)    /* 4 longword align */
662 #define DE4X5_ALIGN32     ((u_long)32 - 1)    /* 8 longword align */
663 #define DE4X5_ALIGN64     ((u_long)64 - 1)    /* 16 longword align */
664 #define DE4X5_ALIGN128    ((u_long)128 - 1)   /* 32 longword align */
789     u_long interrupt;                       /* Aligned ISR flag             */
826 	u_long lock;                        /* Lock the cache accesses      */
910 static int     de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
955 static void    DevicePresent(struct net_device *dev, u_long iobase);
956 static void    enet_addr_rst(u_long aprom_addr);
958 static short   srom_rd(u_long address, u_char offset);
959 static void    srom_latch(u_int command, u_long address);
960 static void    srom_command(u_int command, u_long address);
961 static void    srom_address(u_int command, u_long address, u_char offset);
962 static short   srom_data(u_int command, u_long address);
964 static void    sendto_srom(u_int command, u_long addr);
965 static int     getfrom_srom(u_long addr);
970 static int     mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971 static void    mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972 static int     mii_rdata(u_long ioaddr);
973 static void    mii_wdata(int data, int len, u_long ioaddr);
974 static void    mii_ta(u_long rw, u_long ioaddr);
976 static void    mii_address(u_char addr, u_long ioaddr);
977 static void    sendto_mii(u32 command, int data, u_long ioaddr);
978 static int     getfrom_mii(u32 command, u_long ioaddr);
979 static int     mii_get_oui(u_char phyaddr, u_long ioaddr);
1095 de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)  in de4x5_hw_init()
1295     u_long iobase = dev->base_addr;  in de4x5_open()
1385     u_long iobase = dev->base_addr;  in de4x5_sw_reset()
1463     u_long iobase = dev->base_addr;  in de4x5_queue_pkt()
1464     u_long flags = 0;  in de4x5_queue_pkt()
1484     if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {  in de4x5_queue_pkt()
1491 …(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx…  in de4x5_queue_pkt()
1501 	       (u_long) lp->tx_skb[lp->tx_new] <= 1) {  in de4x5_queue_pkt()
1541     u_long iobase;  in de4x5_interrupt()
1604     u_long iobase = dev->base_addr;  in de4x5_rx()
1682     if ((u_long) lp->tx_skb[entry] > 1)  in de4x5_free_tx_buff()
1694     u_long iobase = dev->base_addr;  in de4x5_tx()
1771     u_long iobase = dev->base_addr;  in de4x5_txur()
1794     u_long iobase = dev->base_addr;  in de4x5_rx_ovfc()
1815     u_long iobase = dev->base_addr;  in de4x5_close()
1851     u_long iobase = dev->base_addr;  in de4x5_get_stats()
1919     u_long iobase = dev->base_addr;  in set_multicast_list()
1950     u_long iobase = dev->base_addr;  in SetMulticastFilter()
1996 	u_long iobase;  in de4x5_eisa_probe()
2082 	u_long iobase;  in de4x5_eisa_remove()
2126     u_long iobase = 0;                     /* Clear upper 32 bits in Alphas */  in srom_search()
2200 	u_long iobase = 0;	/* Clear upper 32 bits in Alphas */  in de4x5_pci_probe()
2319 	u_long iobase;  in de4x5_pci_remove()
2362 	u_long iobase = dev->base_addr;  in autoconf_media()
2392     u_long iobase = dev->base_addr;  in dc21040_autoconf()
2546     u_long iobase = dev->base_addr;  in dc21041_autoconf()
2750     u_long imr, omr, iobase = dev->base_addr;  in dc21140m_autoconf()
2932     u_long iobase = dev->base_addr;  in dc2114x_autoconf()
3261     u_long iobase = dev->base_addr;  in de4x5_init_connection()
3262     u_long flags = 0;  in de4x5_init_connection()
3288     u_long iobase = dev->base_addr;  in de4x5_reset_phy()
3322     u_long iobase = dev->base_addr;  in test_media()
3360     u_long iobase = dev->base_addr;  in test_tp()
3443     u_long iobase = dev->base_addr;  in test_mii_reg()
3465     u_long iobase = dev->base_addr;  in is_spd_100()
3489     u_long iobase = dev->base_addr;  in is_100_up()
3510     u_long iobase = dev->base_addr;  in is_10_up()
3533     u_long iobase = dev->base_addr;  in is_anc_capable()
3552     u_long iobase = dev->base_addr;  in ping_media()
3597     u_long i=0, tmp;  in de4x5_alloc_rx_buff()
3610     if ((u_long) ret > 1) {  in de4x5_alloc_rx_buff()
3642 	if ((u_long) lp->rx_skb[i] > 1) {  in de4x5_free_rx_buffs()
3677     u_long iobase = dev->base_addr;  in de4x5_save_skbs()
3696     u_long iobase = dev->base_addr;  in de4x5_rst_desc_ring()
3727     u_long iobase = dev->base_addr;  in de4x5_cache_state()
3783     u_long iobase = dev->base_addr;  in test_ans()
3811     u_long iobase = dev->base_addr;  in de4x5_setup_intr()
3830     u_long iobase = dev->base_addr;  in reset_init_sia()
3945 DevicePresent(struct net_device *dev, u_long aprom_addr)  in DevicePresent()
3984 enet_addr_rst(u_long aprom_addr)  in enet_addr_rst()
4024     u_long iobase = dev->base_addr;  in get_hw_addr()
4195 srom_rd(u_long addr, u_char offset)  in srom_rd()
4207 srom_latch(u_int command, u_long addr)  in srom_latch()
4215 srom_command(u_int command, u_long addr)  in srom_command()
4223 srom_address(u_int command, u_long addr, u_char offset)  in srom_address()
4237 srom_data(u_int command, u_long addr)  in srom_data()
4271 sendto_srom(u_int command, u_long addr)  in sendto_srom()
4278 getfrom_srom(u_long addr)  in getfrom_srom()
4383     u_long iobase = dev->base_addr;  in srom_exec()
4802 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)  in mii_rd()
4815 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)  in mii_wr()
4828 mii_rdata(u_long ioaddr)  in mii_rdata()
4842 mii_wdata(int data, int len, u_long ioaddr)  in mii_wdata()
4853 mii_address(u_char addr, u_long ioaddr)  in mii_address()
4865 mii_ta(u_long rw, u_long ioaddr)  in mii_ta()
4890 sendto_mii(u32 command, int data, u_long ioaddr)  in sendto_mii()
4902 getfrom_mii(u32 command, u_long ioaddr)  in getfrom_mii()
4916 mii_get_oui(u_char phyaddr, u_long ioaddr)  in mii_get_oui()
4966     u_long iobase = dev->base_addr;  in mii_get_phy()
5069     u_long iobase = dev->base_addr;  in de4x5_switch_mac_port()
5105     u_long iobase = dev->base_addr;  in gep_wr()
5118     u_long iobase = dev->base_addr;  in gep_rd()
5133     u_long iobase = dev->base_addr;  in yawn()
5224 	printk("\t0x%8.8lx  0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);  in de4x5_dbg_open()
5228 		printk("0x%8.8lx  ",(u_long)&lp->rx_ring[i].status);  in de4x5_dbg_open()
5231 	printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);  in de4x5_dbg_open()
5235 		printk("0x%8.8lx  ", (u_long)&lp->tx_ring[i].status);  in de4x5_dbg_open()
5238 	printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);  in de4x5_dbg_open()
5263     u_long iobase = dev->base_addr;  in de4x5_dbg_mii()
5360     u_long iobase = dev->base_addr;  in de4x5_ioctl()
5368     u_long flags = 0;  in de4x5_ioctl()