683     outl(imr, DE4X5_IMR);               /* Enable the IRQs */\
689     outl(imr, DE4X5_IMR);               /* Disable the IRQs */\
694     outl(imr, DE4X5_IMR);               /* Unmask the IRQs */\
700     outl(imr, DE4X5_IMR);               /* Mask the IRQs */\
709     outl(omr, DE4X5_OMR);               /* Enable the TX and/or RX */\
715     outl(omr, DE4X5_OMR);               /* Disable the TX and/or RX */ \
721 #define RESET_SIA outl(0, DE4X5_SICR);  /* Reset SIA connectivity regs */
1066     outl(i | BMR_SWR, DE4X5_BMR);\
1068     outl(i, DE4X5_BMR);\
1075     outl(GEP_HRST, DE4X5_GEP);           /* Hard RESET the PHY dev. */\
1077     outl(0x00, DE4X5_GEP);\
1227 	outl(lp->dma_rings, DE4X5_RRBA);  in de4x5_hw_init()
1228 	outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),  in de4x5_hw_init()
1406     outl(bmr, DE4X5_BMR);  in de4x5_sw_reset()
1413     outl(lp->dma_rings, DE4X5_RRBA);  in de4x5_sw_reset()
1414     outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),  in de4x5_sw_reset()
1434     outl(omr|OMR_ST, DE4X5_OMR);  in de4x5_sw_reset()
1442     outl(omr, DE4X5_OMR);                        /* Stop everything! */  in de4x5_sw_reset()
1506 	    outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */  in de4x5_queue_pkt()
1557 	outl(sts, DE4X5_STS);            /* Reset the board interrupts */  in de4x5_interrupt()
1712 		    outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */  in de4x5_tx()
1777 	outl(omr, DE4X5_OMR);  in de4x5_txur()
1784 	outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);  in de4x5_txur()
1798     outl(omr & ~OMR_SR, DE4X5_OMR);  in de4x5_rx_ovfc()
1806     outl(omr, DE4X5_OMR);  in de4x5_rx_ovfc()
1927 	    outl(omr, DE4X5_OMR);  in set_multicast_list()
1934 	    outl(POLL_DEMAND, DE4X5_TPD);       /* Start the TX */  in set_multicast_list()
1986     outl(omr, DE4X5_OMR);  in SetMulticastFilter()
2058 	outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);  in de4x5_eisa_probe()
2059 	outl(0x00006000, PCI_CFLT);  in de4x5_eisa_probe()
2060 	outl(iobase, PCI_CBIO);  in de4x5_eisa_probe()
2574 	    outl(omr | OMR_FDX, DE4X5_OMR);  in dc21041_autoconf()
2621 		outl(omr & ~OMR_FDX, DE4X5_OMR);  in dc21041_autoconf()
2655 		outl(omr & ~OMR_FDX, DE4X5_OMR);  in dc21041_autoconf()
2686 		outl(omr & ~OMR_FDX, DE4X5_OMR);  in dc21041_autoconf()
2725 	outl(omr | OMR_FDX, DE4X5_OMR);  in dc21041_autoconf()
3034 		outl(omr & ~OMR_FDX, DE4X5_OMR);  in dc2114x_autoconf()
3065 		outl(omr & ~OMR_FDX, DE4X5_OMR);  in dc2114x_autoconf()
3274     outl(POLL_DEMAND, DE4X5_TPD);  in de4x5_init_connection()
3332 	outl(irq_mask, DE4X5_IMR);  in test_media()
3336 	outl(sts, DE4X5_STS);  in test_media()
3341 	    outl(csr12, DE4X5_SISR);  in test_media()
3561 	outl(POLL_DEMAND, DE4X5_TPD);  in ping_media()
3702 	outl(lp->dma_rings, DE4X5_RRBA);  in de4x5_rst_desc_ring()
3703 	outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),  in de4x5_rst_desc_ring()
3737 	outl(lp->cache.csr0, DE4X5_BMR);  in de4x5_cache_state()
3738 	outl(lp->cache.csr6, DE4X5_OMR);  in de4x5_cache_state()
3739 	outl(lp->cache.csr7, DE4X5_IMR);  in de4x5_cache_state()
3788 	outl(irq_mask, DE4X5_IMR);  in test_ans()
3792 	outl(sts, DE4X5_STS);  in test_ans()
3818 	outl(sts, DE4X5_STS);  in de4x5_setup_intr()
3837 	    outl(1, DE4X5_SICR);  in reset_init_sia()
3843 	    outl(csr15 | lp->cache.gepc, DE4X5_SIGR);  in reset_init_sia()
3844 	    outl(csr15 | lp->cache.gep, DE4X5_SIGR);  in reset_init_sia()
3847 	outl(csr15, DE4X5_SIGR);  in reset_init_sia()
3849     outl(csr14, DE4X5_STRR);  in reset_init_sia()
3850     outl(csr13, DE4X5_SICR);  in reset_init_sia()
3954 	    outl(0, aprom_addr);       /* Reset Ethernet Address ROM Pointer */  in DevicePresent()
4273     outl(command, addr);  in sendto_srom()
4398 	outl(lp->cache.csr14, DE4X5_STRR);  in srom_exec()
4399 	outl(lp->cache.csr13, DE4X5_SICR);  in srom_exec()
4895     outl(command | j, ioaddr);  in sendto_mii()
4897     outl(command | MII_MDC | j, ioaddr);  in sendto_mii()
4904     outl(command, ioaddr);  in getfrom_mii()
4906     outl(command | MII_MDC, ioaddr);  in getfrom_mii()
5079     outl(omr, DE4X5_OMR);  in de4x5_switch_mac_port()
5093     outl(omr, DE4X5_OMR);  in de4x5_switch_mac_port()
5108 	outl(data, DE4X5_GEP);  in gep_wr()
5110 	outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);  in gep_wr()
5149 	    outl(0, DE4X5_SICR);  in yawn()
5166 	    outl(0, DE4X5_SICR);  in yawn()
5393 	outl(POLL_DEMAND, DE4X5_TPD);                /* Start the TX */  in de4x5_ioctl()
5406 	outl(omr, DE4X5_OMR);  in de4x5_ioctl()
5435 	outl(tmp.addr[0], DE4X5_OMR);  in de4x5_ioctl()