Lines Matching refs:params
1096 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */ in setup_sge_queues()
1115 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */ in setup_sge_queues()
1132 t4_write_reg(adap, is_t4(adap->params.chip) ? in setup_sge_queues()
1734 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)) in tid_init()
1984 if (is_t4(adap->params.chip)) { in cxgb4_dbfifo_count()
2088 if (is_t4(adap->params.chip)) in cxgb4_sync_txq_pidx()
2140 } else if (is_t5(adap->params.chip)) { in cxgb4_read_tpte()
2240 if (is_t4(adap->params.chip)) { in drain_db_fifo()
2320 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in process_db_full()
2347 if (is_t4(adap->params.chip)) in sync_txq_pidx()
2380 if (is_t4(adap->params.chip)) { in process_db_drop()
2388 } else if (is_t5(adap->params.chip)) { in process_db_drop()
2409 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in process_db_drop()
2415 if (is_t4(adap->params.chip)) { in t4_db_full()
2426 if (is_t4(adap->params.chip)) { in t4_db_dropped()
2445 lli.mtus = adap->params.mtus; in uld_attach()
2456 lli.nchan = adap->params.nports; in uld_attach()
2457 lli.nports = adap->params.nports; in uld_attach()
2458 lli.wr_cred = adap->params.ofldq_wr_cred; in uld_attach()
2459 lli.adapter_type = adap->params.chip; in uld_attach()
2461 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk; in uld_attach()
2462 lli.udb_density = 1 << adap->params.sge.eq_qpp; in uld_attach()
2463 lli.ucq_density = 1 << adap->params.sge.iq_qpp; in uld_attach()
2464 lli.filt_mode = adap->params.tp.vlan_pri_map; in uld_attach()
2470 lli.fw_vers = adap->params.fw_vers; in uld_attach()
2476 lli.max_ordird_qp = adap->params.max_ordird_qp; in uld_attach()
2477 lli.max_ird_adapter = adap->params.max_ird_adapter; in uld_attach()
2478 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl; in uld_attach()
2853 if (adap->params.tp.vlan_pri_map & PORT_F) { in cxgb4_create_server_filter()
2859 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { in cxgb4_create_server_filter()
3188 adap->params.tp.tx_modq_map = 0xE4; in adap_init1()
3190 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); in adap_init1()
3447 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { in adap_init0_config()
3470 u32 params[7], val[7]; in adap_init0_config() local
3479 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | in adap_init0_config()
3482 adapter->pf, 0, 1, params, val); in adap_init0_config()
3692 u32 params[7], val[7]; in adap_init0() local
3720 t4_get_fw_version(adap, &adap->params.fw_vers); in adap_init0()
3721 t4_get_tp_version(adap, &adap->params.tp_vers); in adap_init0()
3736 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); in adap_init0()
3740 CHELSIO_CHIP_VERSION(adap->params.chip)); in adap_init0()
3780 ret = t4_get_vpd_params(adap, &adap->params.vpd); in adap_init0()
3796 adap->params.nports = hweight32(port_vec); in adap_init0()
3797 adap->params.portvec = port_vec; in adap_init0()
3813 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | in adap_init0()
3816 params, val); in adap_init0()
3853 adap->params.bypass = 1; in adap_init0()
3868 params[0] = FW_PARAM_PFVF(EQ_START); in adap_init0()
3869 params[1] = FW_PARAM_PFVF(L2T_START); in adap_init0()
3870 params[2] = FW_PARAM_PFVF(L2T_END); in adap_init0()
3871 params[3] = FW_PARAM_PFVF(FILTER_START); in adap_init0()
3872 params[4] = FW_PARAM_PFVF(FILTER_END); in adap_init0()
3873 params[5] = FW_PARAM_PFVF(IQFLINT_START); in adap_init0()
3874 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); in adap_init0()
3890 params[0] = FW_PARAM_PFVF(EQ_END); in adap_init0()
3891 params[1] = FW_PARAM_PFVF(IQFLINT_END); in adap_init0()
3892 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); in adap_init0()
3938 params[0] = FW_PARAM_PFVF(CLIP_START); in adap_init0()
3939 params[1] = FW_PARAM_PFVF(CLIP_END); in adap_init0()
3940 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); in adap_init0()
3947 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); in adap_init0()
3948 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); in adap_init0()
3949 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); in adap_init0()
3964 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); in adap_init0()
3966 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); in adap_init0()
3974 if (is_t4(adap->params.chip)) { in adap_init0()
3975 adap->params.ulptx_memwrite_dsgl = false; in adap_init0()
3977 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); in adap_init0()
3979 1, params, val); in adap_init0()
3980 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); in adap_init0()
3998 params[0] = FW_PARAM_DEV(NTID); in adap_init0()
3999 params[1] = FW_PARAM_PFVF(SERVER_START); in adap_init0()
4000 params[2] = FW_PARAM_PFVF(SERVER_END); in adap_init0()
4001 params[3] = FW_PARAM_PFVF(TDDP_START); in adap_init0()
4002 params[4] = FW_PARAM_PFVF(TDDP_END); in adap_init0()
4003 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); in adap_init0()
4005 params, val); in adap_init0()
4031 adap->params.ofldq_wr_cred = val[5]; in adap_init0()
4033 adap->params.offload = 1; in adap_init0()
4036 params[0] = FW_PARAM_PFVF(STAG_START); in adap_init0()
4037 params[1] = FW_PARAM_PFVF(STAG_END); in adap_init0()
4038 params[2] = FW_PARAM_PFVF(RQ_START); in adap_init0()
4039 params[3] = FW_PARAM_PFVF(RQ_END); in adap_init0()
4040 params[4] = FW_PARAM_PFVF(PBL_START); in adap_init0()
4041 params[5] = FW_PARAM_PFVF(PBL_END); in adap_init0()
4043 params, val); in adap_init0()
4053 params[0] = FW_PARAM_PFVF(SQRQ_START); in adap_init0()
4054 params[1] = FW_PARAM_PFVF(SQRQ_END); in adap_init0()
4055 params[2] = FW_PARAM_PFVF(CQ_START); in adap_init0()
4056 params[3] = FW_PARAM_PFVF(CQ_END); in adap_init0()
4057 params[4] = FW_PARAM_PFVF(OCQ_START); in adap_init0()
4058 params[5] = FW_PARAM_PFVF(OCQ_END); in adap_init0()
4059 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, in adap_init0()
4070 params[0] = FW_PARAM_DEV(MAXORDIRD_QP); in adap_init0()
4071 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); in adap_init0()
4072 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, in adap_init0()
4075 adap->params.max_ordird_qp = 8; in adap_init0()
4076 adap->params.max_ird_adapter = 32 * adap->tids.ntids; in adap_init0()
4079 adap->params.max_ordird_qp = val[0]; in adap_init0()
4080 adap->params.max_ird_adapter = val[1]; in adap_init0()
4084 adap->params.max_ordird_qp, in adap_init0()
4085 adap->params.max_ird_adapter); in adap_init0()
4088 params[0] = FW_PARAM_PFVF(ISCSI_START); in adap_init0()
4089 params[1] = FW_PARAM_PFVF(ISCSI_END); in adap_init0()
4091 params, val); in adap_init0()
4105 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); in adap_init0()
4127 if (adap->params.mtus[i] == 1492) { in adap_init0()
4128 adap->params.mtus[i] = 1488; in adap_init0()
4132 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, in adap_init0()
4133 adap->params.b_wnd); in adap_init0()
4237 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, in eeh_slot_reset()
4238 adap->params.b_wnd); in eeh_slot_reset()
4309 if (adap->params.nports * 8 > MAX_ETH_QSETS) { in cfg_queues()
4311 MAX_ETH_QSETS, adap->params.nports * 8); in cfg_queues()
4328 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g; in cfg_queues()
4353 s->ofldqsets = roundup(i, adap->params.nports); in cfg_queues()
4355 s->ofldqsets = adap->params.nports; in cfg_queues()
4357 s->rdmaqs = adap->params.nports; in cfg_queues()
4365 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) * in cfg_queues()
4366 adap->params.nports; in cfg_queues()
4367 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports); in cfg_queues()
4455 unsigned int nchan = adap->params.nports; in enable_msix()
4476 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need; in enable_msix()
4478 need = adap->params.nports + EXTRA_VECS + ofld_need; in enable_msix()
4549 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB) in print_port_info()
4551 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB) in print_port_info()
4553 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB) in print_port_info()
4569 adap->params.vpd.id, in print_port_info()
4570 CHELSIO_CHIP_RELEASE(adap->params.chip), buf, in print_port_info()
4571 is_offload(adap) ? "R" : "", adap->params.pci.width, spd, in print_port_info()
4575 adap->params.vpd.sn, adap->params.vpd.pn); in print_port_info()
4751 if (!is_t4(adapter->params.chip)) { in init_one()
4789 if (!is_t4(adapter->params.chip)) in init_one()
4837 } else if (adapter->params.nports == 1) { in init_one()
4844 u8 *na = adapter->params.vpd.na; in init_one()
4846 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); in init_one()
4864 adapter->params.offload = 0; in init_one()
4876 adapter->params.offload = 0; in init_one()
4882 adapter->params.offload = 0; in init_one()
4962 if (!is_t4(adapter->params.chip)) in init_one()
5026 if (!is_t4(adapter->params.chip)) in remove_one()