198 	struct adapter *adap = inode->i_private;  in cim_la_open()  local
200 	ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);  in cim_la_open()
204 	if (is_t6(adap->params.chip)) {  in cim_la_open()
206 		p = seq_open_tab(file, (adap->params.cim_la_size / 10) + 1,  in cim_la_open()
211 		p = seq_open_tab(file, adap->params.cim_la_size / 8,  in cim_la_open()
219 	ret = t4_cim_read_la(adap, (u32 *)p->data, NULL);  in cim_la_open()
256 	struct adapter *adap = inode->i_private;  in cim_pif_la_open()  local
263 	t4_cim_read_pif_la(adap, (u32 *)p->data,  in cim_pif_la_open()
302 	struct adapter *adap = inode->i_private;  in cim_ma_la_open()  local
309 	t4_cim_read_ma_la(adap, (u32 *)p->data,  in cim_ma_la_open()
331 	struct adapter *adap = seq->private;  in cim_qcfg_show()  local
339 	int cim_num_obq = is_t4(adap->params.chip) ?  in cim_qcfg_show()
342 	i = t4_cim_read(adap, is_t4(adap->params.chip) ? UP_IBQ_0_RDADDR_A :  in cim_qcfg_show()
346 		if (is_t4(adap->params.chip)) {  in cim_qcfg_show()
347 			i = t4_cim_read(adap, UP_OBQ_0_REALADDR_A,  in cim_qcfg_show()
351 			i = t4_cim_read(adap, UP_OBQ_0_SHADOW_REALADDR_A,  in cim_qcfg_show()
359 	t4_read_cimq_cfg(adap, base, size, thres);  in cim_qcfg_show()
405 	struct adapter *adap = inode->i_private - qid;  in cim_ibq_open()  local
411 	ret = t4_read_cim_ibq(adap, qid, (u32 *)p->data, CIM_IBQ_SIZE * 4);  in cim_ibq_open()
432 	struct adapter *adap = inode->i_private - qid;  in cim_obq_open()  local
438 	ret = t4_read_cim_obq(adap, qid, (u32 *)p->data, 6 * CIM_OBQ_SIZE * 4);  in cim_obq_open()
650 	struct adapter *adap = inode->i_private;  in tp_la_open()  local
652 	switch (DBGLAMODE_G(t4_read_reg(adap, TP_DBG_LA_CONFIG_A))) {  in tp_la_open()
667 	t4_tp_read_la(adap, (u64 *)p->data, NULL);  in tp_la_open()
678 	struct adapter *adap = file_inode(file)->i_private;  in tp_la_write()  local
688 	adap->params.tp.la_mask = val << 16;  in tp_la_write()
689 	t4_set_reg_field(adap, TP_DBG_LA_CONFIG_A, 0xffff0000U,  in tp_la_write()
690 			 adap->params.tp.la_mask);  in tp_la_write()
719 	struct adapter *adap = inode->i_private;  in ulprx_la_open()  local
726 	t4_ulprx_read_la(adap, (u32 *)p->data);  in ulprx_la_open()
762 	struct adapter *adap = seq->private;  in pm_stats_show()  local
764 	t4_pmtx_get_stats(adap, tx_cnt, tx_cyc);  in pm_stats_show()
765 	t4_pmrx_get_stats(adap, rx_cnt, rx_cyc);  in pm_stats_show()
787 	struct adapter *adap = file_inode(file)->i_private;  in pm_stats_clear()  local
789 	t4_write_reg(adap, PM_RX_STAT_CONFIG_A, 0);  in pm_stats_clear()
790 	t4_write_reg(adap, PM_TX_STAT_CONFIG_A, 0);  in pm_stats_clear()
806 	struct adapter *adap = seq->private;  in tx_rate_show()  local
808 	t4_get_chan_txrate(adap, nrate, orate);  in tx_rate_show()
809 	if (adap->params.arch.nchan == NCHAN) {  in tx_rate_show()
844 	struct adapter *adap = seq->private;  in cctrl_tbl_show()  local
850 	t4_read_cong_tbl(adap, incr);  in cctrl_tbl_show()
859 			   adap->params.a_wnd[i],  in cctrl_tbl_show()
860 			   dec_fac[adap->params.b_wnd[i]]);  in cctrl_tbl_show()
890 	struct adapter *adap = seq->private;  in clk_show()  local
891 	unsigned int cclk_ps = 1000000000 / adap->params.vpd.cclk;  /* in ps */  in clk_show()
892 	u32 res = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);  in clk_show()
908 		   t4_read_reg(adap, TP_DACK_TIMER_A));  in clk_show()
910 		   tp_tick_us * t4_read_reg(adap, TP_RXT_MIN_A));  in clk_show()
912 		   tp_tick_us * t4_read_reg(adap, TP_RXT_MAX_A));  in clk_show()
914 		   tp_tick_us * t4_read_reg(adap, TP_PERS_MIN_A));  in clk_show()
916 		   tp_tick_us * t4_read_reg(adap, TP_PERS_MAX_A));  in clk_show()
918 		   tp_tick_us * t4_read_reg(adap, TP_KEEP_IDLE_A));  in clk_show()
920 		   tp_tick_us * t4_read_reg(adap, TP_KEEP_INTVL_A));  in clk_show()
922 		   tp_tick_us * INITSRTT_G(t4_read_reg(adap, TP_INIT_SRTT_A)));  in clk_show()
924 		   tp_tick_us * t4_read_reg(adap, TP_FINWAIT2_TIMER_A));  in clk_show()
1068 	struct adapter *adap = inode->i_private;  in devlog_open()  local
1069 	struct devlog_params *dparams = &adap->params.devlog;  in devlog_open()
1092 	spin_lock(&adap->win0_lock);  in devlog_open()
1093 	ret = t4_memory_rw(adap, adap->params.drv_memwin, dparams->memtype,  in devlog_open()
1096 	spin_unlock(&adap->win0_lock);  in devlog_open()
1136 	struct adapter *adap = seq->private - mbox;  in mbox_show()  local
1137 	void __iomem *addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);  in mbox_show()
1143 	if (is_t4(adap->params.chip)) {  in mbox_show()
1147 		void __iomem *ctrl = adap->regs + PF_REG(mbox, ctrl_reg);  in mbox_show()
1173 	struct adapter *adap;  in mbox_write()  local
1190 	adap = ino->i_private - mbox;  in mbox_write()
1191 	addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);  in mbox_write()
1218 	struct adapter *adap = seq->private - trcidx;  in mps_trc_show()  local
1220 	t4_get_trace_filter(adap, &tp, trcidx, &enabled);  in mps_trc_show()
1227 		dev_err(adap->pdev_dev, "illegal trace pattern skip offset\n");  in mps_trc_show()
1231 		i = adap->chan_map[tp.port & 3];  in mps_trc_show()
1233 			dev_err(adap->pdev_dev, "tracer %u is assigned "  in mps_trc_show()
1238 			   adap->port[i]->name, tp.port < 4 ? "Rx" : "Tx");  in mps_trc_show()
1307 	struct adapter *adap;  in mps_trc_write()  local
1312 	adap = ino->i_private - trcidx;  in mps_trc_write()
1335 	if (adap->trace_rss)  in mps_trc_write()
1336 		t4_write_reg(adap, MPS_TRC_CFG_A, TRC_RSS_ENABLE);  in mps_trc_write()
1338 		t4_write_reg(adap, MPS_TRC_CFG_A, TRC_RSS_DISABLE);  in mps_trc_write()
1356 			if (!adap->trace_rss) {  in mps_trc_write()
1357 				t4_write_reg(adap, MPS_T5_TRC_RSS_CONTROL_A, j);  in mps_trc_write()
1363 				t4_write_reg(adap, MPS_TRC_RSS_CONTROL_A, j);  in mps_trc_write()
1366 				t4_write_reg(adap,  in mps_trc_write()
1370 				t4_write_reg(adap,  in mps_trc_write()
1374 				t4_write_reg(adap,  in mps_trc_write()
1412 			if (adap->chan_map[tp.port & 3] >= MAX_NPORTS)  in mps_trc_write()
1420 			if (adap->chan_map[tp.port] >= MAX_NPORTS)  in mps_trc_write()
1489 	i = t4_set_trace_filter(adap, &tp, trcidx, enable);  in mps_trc_write()
1511 	struct adapter *adap = file->private_data;  in flash_read()  local
1527 		ret = t4_read_flash(adap, pos - ofst, (len + 3) / 4,  in flash_read()
1560 	struct adapter *adap = seq->private;  in mps_tcam_show()  local
1561 	unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);  in mps_tcam_show()
1564 		if (adap->params.arch.mps_rplc_size > 128)  in mps_tcam_show()
1595 			t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);  in mps_tcam_show()
1596 			val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A);  in mps_tcam_show()
1598 			tcamy |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A);  in mps_tcam_show()
1602 			t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);  in mps_tcam_show()
1603 			val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A);  in mps_tcam_show()
1605 			tcamx |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A);  in mps_tcam_show()
1607 			tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx));  in mps_tcam_show()
1608 			tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx));  in mps_tcam_show()
1611 		cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx));  in mps_tcam_show()
1612 		cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx));  in mps_tcam_show()
1643 			ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd,  in mps_tcam_show()
1646 				dev_warn(adap->pdev_dev, "Can't read MPS "  in mps_tcam_show()
1655 				if (adap->params.arch.mps_rplc_size > 128) {  in mps_tcam_show()
1686 			if (adap->params.arch.mps_rplc_size > 128)  in mps_tcam_show()
1695 			if (adap->params.arch.mps_rplc_size > 128)  in mps_tcam_show()
1719 	struct adapter *adap = seq->private;  in mps_tcam_get_idx()  local
1720 	int max_mac_addr = is_t4(adap->params.chip) ?  in mps_tcam_get_idx()
1772 	struct adapter *adap = seq->private;  in sensors_show()  local
1785 	ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,  in sensors_show()
1835 	struct adapter *adap = inode->i_private;  in rss_open()  local
1841 	ret = t4_read_rss(adap, (u16 *)p->data);  in rss_open()
2045 	struct adapter *adap = file_inode(file)->i_private;  in rss_key_write()  local
2064 	t4_write_rss_key(adap, key, -1);  in rss_key_write()
2227 static inline struct port_info *ethqset2pinfo(struct adapter *adap, int qset)  in ethqset2pinfo()  argument
2231 	for_each_port(adap, pidx) {  in ethqset2pinfo()
2232 		struct port_info *pi = adap2pinfo(adap, pidx);  in ethqset2pinfo()
2246 	struct adapter *adap = seq->private;  in sge_qinfo_show()  local
2247 	int eth_entries = DIV_ROUND_UP(adap->sge.ethqsets, 4);  in sge_qinfo_show()
2248 	int iscsi_entries = DIV_ROUND_UP(adap->sge.ofldqsets, 4);  in sge_qinfo_show()
2249 	int rdma_entries = DIV_ROUND_UP(adap->sge.rdmaqs, 4);  in sge_qinfo_show()
2250 	int ciq_entries = DIV_ROUND_UP(adap->sge.rdmaciqs, 4);  in sge_qinfo_show()
2279 		const struct sge_eth_rxq *rx = &adap->sge.ethrxq[base_qset];  in sge_qinfo_show()
2280 		const struct sge_eth_txq *tx = &adap->sge.ethtxq[base_qset];  in sge_qinfo_show()
2281 		int n = min(4, adap->sge.ethqsets - 4 * r);  in sge_qinfo_show()
2294 		   (ethqset2pinfo(adap, base_qset + i)->dcb.pgid >>  in sge_qinfo_show()
2297 		   (ethqset2pinfo(adap, base_qset + i)->dcb.pfcen >>  in sge_qinfo_show()
2305 		S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));  in sge_qinfo_show()
2307 		   adap->sge.counter_val[rx[i].rspq.pktcnt_idx]);  in sge_qinfo_show()
2332 			&adap->sge.ofldrxq[iscsi_idx * 4];  in sge_qinfo_show()
2334 			&adap->sge.ofldtxq[iscsi_idx * 4];  in sge_qinfo_show()
2335 		int n = min(4, adap->sge.ofldqsets - 4 * iscsi_idx);  in sge_qinfo_show()
2348 		S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));  in sge_qinfo_show()
2350 		   adap->sge.counter_val[rx[i].rspq.pktcnt_idx]);  in sge_qinfo_show()
2366 				&adap->sge.rdmarxq[rdma_idx * 4];  in sge_qinfo_show()
2367 		int n = min(4, adap->sge.rdmaqs - 4 * rdma_idx);  in sge_qinfo_show()
2377 		S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));  in sge_qinfo_show()
2379 		   adap->sge.counter_val[rx[i].rspq.pktcnt_idx]);  in sge_qinfo_show()
2394 		const struct sge_ofld_rxq *rx = &adap->sge.rdmaciq[ciq_idx * 4];  in sge_qinfo_show()
2395 		int n = min(4, adap->sge.rdmaciqs - 4 * ciq_idx);  in sge_qinfo_show()
2405 		S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));  in sge_qinfo_show()
2407 		   adap->sge.counter_val[rx[i].rspq.pktcnt_idx]);  in sge_qinfo_show()
2412 		const struct sge_ctrl_txq *tx = &adap->sge.ctrlq[ctrl_idx * 4];  in sge_qinfo_show()
2413 		int n = min(4, adap->params.nports - 4 * ctrl_idx);  in sge_qinfo_show()
2424 		const struct sge_rspq *evtq = &adap->sge.fw_evtq;  in sge_qinfo_show()
2433 			   qtimer_val(adap, evtq));  in sge_qinfo_show()
2435 			   adap->sge.counter_val[evtq->pktcnt_idx]);  in sge_qinfo_show()
2448 static int sge_queue_entries(const struct adapter *adap)  in sge_queue_entries()  argument
2450 	return DIV_ROUND_UP(adap->sge.ethqsets, 4) +  in sge_queue_entries()
2451 	       DIV_ROUND_UP(adap->sge.ofldqsets, 4) +  in sge_queue_entries()
2452 	       DIV_ROUND_UP(adap->sge.rdmaqs, 4) +  in sge_queue_entries()
2453 	       DIV_ROUND_UP(adap->sge.rdmaciqs, 4) +  in sge_queue_entries()
2506 	struct adapter *adap;  in mem_open()  local
2511 	adap = file->private_data - mem;  in mem_open()
2513 	(void)t4_fwcache(adap, FW_PARAM_DEV_FWCACHE_FLUSH);  in mem_open()
2524 	struct adapter *adap = file->private_data - mem;  in mem_read()  local
2539 	spin_lock(&adap->win0_lock);  in mem_read()
2540 	ret = t4_memory_rw(adap, 0, mem, pos, count, data, T4_MEMORY_READ);  in mem_read()
2541 	spin_unlock(&adap->win0_lock);  in mem_read()
2564 	struct adapter *adap = seq->private;  in tid_info_show()  local
2565 	const struct tid_info *t = &adap->tids;  in tid_info_show()
2566 	enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);  in tid_info_show()
2568 	if (t4_read_reg(adap, LE_DB_CONFIG_A) & HASHEN_F) {  in tid_info_show()
2572 			sb = t4_read_reg(adap, LE_DB_SERVER_INDEX_A) / 4;  in tid_info_show()
2574 			sb = t4_read_reg(adap, LE_DB_SRVR_START_INDEX_A);  in tid_info_show()
2578 				   adap->tids.hash_base,  in tid_info_show()
2583 		} else if (adap->flags & FW_OFLD_CONN) {  in tid_info_show()
2587 				   adap->tids.hash_base,  in tid_info_show()
2594 				   adap->tids.hash_base,  in tid_info_show()
2622 			   t4_read_reg(adap, LE_DB_ACT_CNT_IPV4_A),  in tid_info_show()
2623 			   t4_read_reg(adap, LE_DB_ACT_CNT_IPV6_A));  in tid_info_show()
2629 static void add_debugfs_mem(struct adapter *adap, const char *name,  in add_debugfs_mem()  argument
2632 	debugfs_create_file_size(name, S_IRUSR, adap->debugfs_root,  in add_debugfs_mem()
2633 				 (void *)adap + idx, &mem_debugfs_fops,  in add_debugfs_mem()
2647 	const struct adapter *adap = filp->private_data;  in blocked_fl_read()  local
2649 	ssize_t size = (adap->sge.egr_sz + 3) / 4 +  in blocked_fl_read()
2650 			adap->sge.egr_sz / 32 + 2; /* includes ,/\n/\0 */  in blocked_fl_read()
2657 		       adap->sge.egr_sz, adap->sge.blocked_fl);  in blocked_fl_read()
2669 	struct adapter *adap = filp->private_data;  in blocked_fl_write()  local
2671 	t = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), sizeof(long), GFP_KERNEL);  in blocked_fl_write()
2675 	err = bitmap_parse_user(ubuf, count, t, adap->sge.egr_sz);  in blocked_fl_write()
2679 	bitmap_copy(adap->sge.blocked_fl, t, adap->sge.egr_sz);  in blocked_fl_write()
2733 	struct adapter *adap = seq->private;  in meminfo_show()  local
2742 	lo = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);  in meminfo_show()
2744 		hi = t4_read_reg(adap, MA_EDRAM0_BAR_A);  in meminfo_show()
2751 		hi = t4_read_reg(adap, MA_EDRAM1_BAR_A);  in meminfo_show()
2758 	if (is_t5(adap->params.chip)) {  in meminfo_show()
2760 			hi = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);  in meminfo_show()
2768 			hi = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);  in meminfo_show()
2777 			hi = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);  in meminfo_show()
2789 	(md++)->base = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A);  in meminfo_show()
2790 	(md++)->base = t4_read_reg(adap, SGE_IMSG_CTXT_BADDR_A);  in meminfo_show()
2791 	(md++)->base = t4_read_reg(adap, SGE_FLM_CACHE_BADDR_A);  in meminfo_show()
2792 	(md++)->base = t4_read_reg(adap, TP_CMM_TCB_BASE_A);  in meminfo_show()
2793 	(md++)->base = t4_read_reg(adap, TP_CMM_MM_BASE_A);  in meminfo_show()
2794 	(md++)->base = t4_read_reg(adap, TP_CMM_TIMER_BASE_A);  in meminfo_show()
2795 	(md++)->base = t4_read_reg(adap, TP_CMM_MM_RX_FLST_BASE_A);  in meminfo_show()
2796 	(md++)->base = t4_read_reg(adap, TP_CMM_MM_TX_FLST_BASE_A);  in meminfo_show()
2797 	(md++)->base = t4_read_reg(adap, TP_CMM_MM_PS_FLST_BASE_A);  in meminfo_show()
2800 	md->base = t4_read_reg(adap, TP_PMM_TX_BASE_A);  in meminfo_show()
2802 		    t4_read_reg(adap, TP_PMM_TX_PAGE_SIZE_A) *  in meminfo_show()
2803 		    PMTXMAXPAGE_G(t4_read_reg(adap, TP_PMM_TX_MAX_PAGE_A));  in meminfo_show()
2806 	md->base = t4_read_reg(adap, TP_PMM_RX_BASE_A);  in meminfo_show()
2808 		    t4_read_reg(adap, TP_PMM_RX_PAGE_SIZE_A) *  in meminfo_show()
2809 		    PMRXMAXPAGE_G(t4_read_reg(adap, TP_PMM_RX_MAX_PAGE_A));  in meminfo_show()
2812 	if (t4_read_reg(adap, LE_DB_CONFIG_A) & HASHEN_F) {  in meminfo_show()
2813 		if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) {  in meminfo_show()
2814 			hi = t4_read_reg(adap, LE_DB_TID_HASHBASE_A) / 4;  in meminfo_show()
2815 			md->base = t4_read_reg(adap, LE_DB_HASH_TID_BASE_A);  in meminfo_show()
2817 			hi = t4_read_reg(adap, LE_DB_HASH_TID_BASE_A);  in meminfo_show()
2818 			md->base = t4_read_reg(adap,  in meminfo_show()
2829 	md->base = t4_read_reg(adap, ULP_ ## reg ## _LLIMIT_A);\  in meminfo_show()
2830 	(md++)->limit = t4_read_reg(adap, ULP_ ## reg ## _ULIMIT_A); \  in meminfo_show()
2844 	if (!is_t4(adap->params.chip)) {  in meminfo_show()
2846 		u32 sge_ctrl = t4_read_reg(adap, SGE_CONTROL2_A);  in meminfo_show()
2847 		u32 fifo_size = t4_read_reg(adap, SGE_DBVFIFO_SIZE_A);  in meminfo_show()
2849 		if (is_t5(adap->params.chip)) {  in meminfo_show()
2857 			md->base = BASEADDR_G(t4_read_reg(adap,  in meminfo_show()
2865 	md->base = t4_read_reg(adap, ULP_RX_CTX_BASE_A);  in meminfo_show()
2868 	md->base = t4_read_reg(adap, ULP_TX_ERR_TABLE_BASE_A);  in meminfo_show()
2872 	md->base = adap->vres.ocq.start;  in meminfo_show()
2873 	if (adap->vres.ocq.size)  in meminfo_show()
2874 		md->limit = md->base + adap->vres.ocq.size - 1;  in meminfo_show()
2904 	lo = t4_read_reg(adap, CIM_SDRAM_BASE_ADDR_A);  in meminfo_show()
2905 	hi = t4_read_reg(adap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1;  in meminfo_show()
2908 	lo = t4_read_reg(adap, CIM_EXTMEM2_BASE_ADDR_A);  in meminfo_show()
2909 	hi = t4_read_reg(adap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1;  in meminfo_show()
2912 	lo = t4_read_reg(adap, TP_PMM_RX_MAX_PAGE_A);  in meminfo_show()
2915 		   t4_read_reg(adap, TP_PMM_RX_PAGE_SIZE_A) >> 10,  in meminfo_show()
2918 	lo = t4_read_reg(adap, TP_PMM_TX_MAX_PAGE_A);  in meminfo_show()
2919 	hi = t4_read_reg(adap, TP_PMM_TX_PAGE_SIZE_A);  in meminfo_show()
2925 		   t4_read_reg(adap, TP_CMM_MM_MAX_PSTRUCT_A));  in meminfo_show()
2928 		if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5)  in meminfo_show()
2929 			lo = t4_read_reg(adap, MPS_RX_MAC_BG_PG_CNT0_A + i * 4);  in meminfo_show()
2931 			lo = t4_read_reg(adap, MPS_RX_PG_RSV0_A + i * 4);  in meminfo_show()
2932 		if (is_t5(adap->params.chip)) {  in meminfo_show()
2943 	for (i = 0; i < adap->params.arch.nchan; i++) {  in meminfo_show()
2944 		if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5)  in meminfo_show()
2945 			lo = t4_read_reg(adap,  in meminfo_show()
2948 			lo = t4_read_reg(adap, MPS_RX_PG_RSV4_A + i * 4);  in meminfo_show()
2949 		if (is_t5(adap->params.chip)) {  in meminfo_show()
2978 void add_debugfs_files(struct adapter *adap,  in add_debugfs_files()  argument
2987 				    adap->debugfs_root,  in add_debugfs_files()
2988 				    (void *)adap + files[i].data,  in add_debugfs_files()
2992 int t4_setup_debugfs(struct adapter *adap)  in t4_setup_debugfs()  argument
3058 	add_debugfs_files(adap,  in t4_setup_debugfs()
3061 	if (!is_t4(adap->params.chip))  in t4_setup_debugfs()
3062 		add_debugfs_files(adap,  in t4_setup_debugfs()
3066 	i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);  in t4_setup_debugfs()
3068 		size = t4_read_reg(adap, MA_EDRAM0_BAR_A);  in t4_setup_debugfs()
3069 		add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM0_SIZE_G(size));  in t4_setup_debugfs()
3072 		size = t4_read_reg(adap, MA_EDRAM1_BAR_A);  in t4_setup_debugfs()
3073 		add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size));  in t4_setup_debugfs()
3075 	if (is_t5(adap->params.chip)) {  in t4_setup_debugfs()
3077 			size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);  in t4_setup_debugfs()
3078 			add_debugfs_mem(adap, "mc0", MEM_MC0,  in t4_setup_debugfs()
3082 			size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);  in t4_setup_debugfs()
3083 			add_debugfs_mem(adap, "mc1", MEM_MC1,  in t4_setup_debugfs()
3088 			size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);  in t4_setup_debugfs()
3089 			add_debugfs_mem(adap, "mc", MEM_MC,  in t4_setup_debugfs()
3094 	de = debugfs_create_file_size("flash", S_IRUSR, adap->debugfs_root, adap,  in t4_setup_debugfs()
3095 				      &flash_debugfs_fops, adap->params.sf_size);  in t4_setup_debugfs()
3097 			    adap->debugfs_root, &adap->use_bd);  in t4_setup_debugfs()
3099 			    adap->debugfs_root, &adap->trace_rss);  in t4_setup_debugfs()