Lines Matching refs:base_addr

2208 		       enum sge_context_type type, int respq, u64 base_addr,  in t3_sge_init_ecntxt()  argument
2214 if (base_addr & 0xfff) /* must be 4K aligned */ in t3_sge_init_ecntxt()
2219 base_addr >>= 12; in t3_sge_init_ecntxt()
2223 V_EC_BASE_LO(base_addr & 0xffff)); in t3_sge_init_ecntxt()
2224 base_addr >>= 16; in t3_sge_init_ecntxt()
2225 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, base_addr); in t3_sge_init_ecntxt()
2226 base_addr >>= 32; in t3_sge_init_ecntxt()
2228 V_EC_BASE_HI(base_addr & 0xf) | V_EC_RESPQ(respq) | in t3_sge_init_ecntxt()
2251 int gts_enable, u64 base_addr, unsigned int size, in t3_sge_init_flcntxt() argument
2255 if (base_addr & 0xfff) /* must be 4K aligned */ in t3_sge_init_flcntxt()
2260 base_addr >>= 12; in t3_sge_init_flcntxt()
2261 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, base_addr); in t3_sge_init_flcntxt()
2262 base_addr >>= 32; in t3_sge_init_flcntxt()
2264 V_FL_BASE_HI((u32) base_addr) | in t3_sge_init_flcntxt()
2291 int irq_vec_idx, u64 base_addr, unsigned int size, in t3_sge_init_rspcntxt() argument
2296 if (base_addr & 0xfff) /* must be 4K aligned */ in t3_sge_init_rspcntxt()
2301 base_addr >>= 12; in t3_sge_init_rspcntxt()
2304 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr); in t3_sge_init_rspcntxt()
2305 base_addr >>= 32; in t3_sge_init_rspcntxt()
2309 V_CQ_BASE_HI((u32) base_addr) | intr | V_RQ_GEN(gen)); in t3_sge_init_rspcntxt()
2329 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, in t3_sge_init_cqcntxt() argument
2333 if (base_addr & 0xfff) /* must be 4K aligned */ in t3_sge_init_cqcntxt()
2338 base_addr >>= 12; in t3_sge_init_cqcntxt()
2340 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr); in t3_sge_init_cqcntxt()
2341 base_addr >>= 32; in t3_sge_init_cqcntxt()
2343 V_CQ_BASE_HI((u32) base_addr) | V_CQ_RSPQ(rspq) | in t3_sge_init_cqcntxt()
3493 unsigned int base_addr, const char *name) in mc7_prep() argument
3499 mc7->offset = base_addr - MC7_PMRX_BASE_ADDR; in mc7_prep()