124 static void t3_read_indirect(struct adapter *adap, unsigned int addr_reg,  in t3_read_indirect()  argument
129 		t3_write_reg(adap, addr_reg, start_idx);  in t3_read_indirect()
130 		*vals++ = t3_read_reg(adap, data_reg);  in t3_read_indirect()
152 	struct adapter *adap = mc7->adapter;  in t3_mc7_bd_read()  local
166 			t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start);  in t3_mc7_bd_read()
167 			t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);  in t3_mc7_bd_read()
168 			val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);  in t3_mc7_bd_read()
170 				val = t3_read_reg(adap,  in t3_mc7_bd_read()
175 			val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);  in t3_mc7_bd_read()
177 				val64 = t3_read_reg(adap,  in t3_mc7_bd_read()
196 static void mi1_init(struct adapter *adap, const struct adapter_info *ai)  in mi1_init()  argument
198 	u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1;  in mi1_init()
201 	t3_write_reg(adap, A_MI1_CFG, val);  in mi1_init()
1146 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,  in t3_cim_ctl_blk_read()  argument
1151 	if (t3_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)  in t3_cim_ctl_blk_read()
1155 		t3_write_reg(adap, A_CIM_HOST_ACC_CTRL, CIM_CTL_BASE + addr);  in t3_cim_ctl_blk_read()
1156 		ret = t3_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,  in t3_cim_ctl_blk_read()
1159 			*valp++ = t3_read_reg(adap, A_CIM_HOST_ACC_DATA);  in t3_cim_ctl_blk_read()
1810 static int mac_intr_handler(struct adapter *adap, unsigned int idx)  in mac_intr_handler()  argument
1812 	struct cmac *mac = &adap2pinfo(adap, idx)->mac;  in mac_intr_handler()
1819 	u32 cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset) &  in mac_intr_handler()
1824 		CH_ALERT(adap, "port%d: MAC TX FIFO parity error\n", idx);  in mac_intr_handler()
1828 		CH_ALERT(adap, "port%d: MAC RX FIFO parity error\n", idx);  in mac_intr_handler()
1841 		t3_set_reg_field(adap,  in mac_intr_handler()
1846 		t3_os_link_fault_handler(adap, idx);  in mac_intr_handler()
1850 		t3_fatal_err(adap);  in mac_intr_handler()
1852 	t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause);  in mac_intr_handler()
1940 static unsigned int calc_gpio_intr(struct adapter *adap)  in calc_gpio_intr()  argument
1944 	for_each_port(adap, i)  in calc_gpio_intr()
1945 		if ((adap2pinfo(adap, i)->phy.caps & SUPPORTED_IRQ) &&  in calc_gpio_intr()
1946 		    adapter_info(adap)->gpio_intr[i])  in calc_gpio_intr()
1947 			gpi_intr |= 1 << adapter_info(adap)->gpio_intr[i];  in calc_gpio_intr()
2173 static int clear_sge_ctxt(struct adapter *adap, unsigned int id,  in clear_sge_ctxt()  argument
2176 	t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0);  in clear_sge_ctxt()
2177 	t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0);  in clear_sge_ctxt()
2178 	t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0);  in clear_sge_ctxt()
2179 	t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0);  in clear_sge_ctxt()
2180 	t3_write_reg(adap, A_SG_CONTEXT_MASK0, 0xffffffff);  in clear_sge_ctxt()
2181 	t3_write_reg(adap, A_SG_CONTEXT_MASK1, 0xffffffff);  in clear_sge_ctxt()
2182 	t3_write_reg(adap, A_SG_CONTEXT_MASK2, 0xffffffff);  in clear_sge_ctxt()
2183 	t3_write_reg(adap, A_SG_CONTEXT_MASK3, 0xffffffff);  in clear_sge_ctxt()
2184 	t3_write_reg(adap, A_SG_CONTEXT_CMD,  in clear_sge_ctxt()
2186 	return t3_wait_op_done(adap, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,  in clear_sge_ctxt()
2535 void t3_tp_set_offload_mode(struct adapter *adap, int enable)  in t3_tp_set_offload_mode()  argument
2537 	if (is_offload(adap) || !enable)  in t3_tp_set_offload_mode()
2538 		t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE,  in t3_tp_set_offload_mode()
2559 #define mem_region(adap, start, size, reg) \  argument
2560 	t3_write_reg((adap), A_ ## reg, (start)); \
2571 static void partition_mem(struct adapter *adap, const struct tp_params *p)  in partition_mem()  argument
2573 	unsigned int m, pstructs, tids = t3_mc5_size(&adap->mc5);  in partition_mem()
2576 	if (adap->params.rev > 0) {  in partition_mem()
2589 	t3_write_reg(adap, A_TP_PMM_SIZE,  in partition_mem()
2592 	t3_write_reg(adap, A_TP_PMM_TX_BASE, 0);  in partition_mem()
2593 	t3_write_reg(adap, A_TP_PMM_TX_PAGE_SIZE, p->tx_pg_size);  in partition_mem()
2594 	t3_write_reg(adap, A_TP_PMM_TX_MAX_PAGE, p->tx_num_pgs);  in partition_mem()
2595 	t3_set_reg_field(adap, A_TP_PARA_REG3, V_TXDATAACKIDX(M_TXDATAACKIDX),  in partition_mem()
2598 	t3_write_reg(adap, A_TP_PMM_RX_BASE, 0);  in partition_mem()
2599 	t3_write_reg(adap, A_TP_PMM_RX_PAGE_SIZE, p->rx_pg_size);  in partition_mem()
2600 	t3_write_reg(adap, A_TP_PMM_RX_MAX_PAGE, p->rx_num_pgs);  in partition_mem()
2606 	t3_write_reg(adap, A_TP_CMM_MM_MAX_PSTRUCT, pstructs);  in partition_mem()
2609 	mem_region(adap, m, (64 << 10) * 64, SG_EGR_CNTX_BADDR);  in partition_mem()
2610 	mem_region(adap, m, (64 << 10) * 64, SG_CQ_CONTEXT_BADDR);  in partition_mem()
2611 	t3_write_reg(adap, A_TP_CMM_TIMER_BASE, V_CMTIMERMAXNUM(timers) | m);  in partition_mem()
2613 	mem_region(adap, m, pstructs * 64, TP_CMM_MM_BASE);  in partition_mem()
2614 	mem_region(adap, m, 64 * (pstructs / 24), TP_CMM_MM_PS_FLST_BASE);  in partition_mem()
2615 	mem_region(adap, m, 64 * (p->rx_num_pgs / 24), TP_CMM_MM_RX_FLST_BASE);  in partition_mem()
2616 	mem_region(adap, m, 64 * (p->tx_num_pgs / 24), TP_CMM_MM_TX_FLST_BASE);  in partition_mem()
2619 	t3_write_reg(adap, A_CIM_SDRAM_BASE_ADDR, m);  in partition_mem()
2620 	t3_write_reg(adap, A_CIM_SDRAM_ADDR_SIZE, p->cm_size - m);  in partition_mem()
2623 	m = t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -  in partition_mem()
2624 	    adap->params.mc5.nfilters - adap->params.mc5.nroutes;  in partition_mem()
2626 		adap->params.mc5.nservers += m - tids;  in partition_mem()
2629 static inline void tp_wr_indirect(struct adapter *adap, unsigned int addr,  in tp_wr_indirect()  argument
2632 	t3_write_reg(adap, A_TP_PIO_ADDR, addr);  in tp_wr_indirect()
2633 	t3_write_reg(adap, A_TP_PIO_DATA, val);  in tp_wr_indirect()
2636 static void tp_config(struct adapter *adap, const struct tp_params *p)  in tp_config()  argument
2638 	t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |  in tp_config()
2641 	t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |  in tp_config()
2644 	t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |  in tp_config()
2648 	t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO,  in tp_config()
2650 	t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);  in tp_config()
2651 	t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);  in tp_config()
2652 	t3_set_reg_field(adap, A_TP_PARA_REG6, 0,  in tp_config()
2653 			 adap->params.rev > 0 ? F_ENABLEESND :  in tp_config()
2656 	t3_set_reg_field(adap, A_TP_PC_CONFIG,  in tp_config()
2660 	t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL,  in tp_config()
2663 	t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);  in tp_config()
2664 	t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);  in tp_config()
2666 	if (adap->params.rev > 0) {  in tp_config()
2667 		tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);  in tp_config()
2668 		t3_set_reg_field(adap, A_TP_PARA_REG3, F_TXPACEAUTO,  in tp_config()
2670 		t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);  in tp_config()
2671 		t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEAUTOSTRICT);  in tp_config()
2673 		t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);  in tp_config()
2675 	if (adap->params.rev == T3_REV_C)  in tp_config()
2676 		t3_set_reg_field(adap, A_TP_PC_CONFIG,  in tp_config()
2680 	t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);  in tp_config()
2681 	t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);  in tp_config()
2682 	t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);  in tp_config()
2683 	t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);  in tp_config()
2701 static void tp_set_timers(struct adapter *adap, unsigned int core_clk)  in tp_set_timers()  argument
2708 	t3_write_reg(adap, A_TP_TIMER_RESOLUTION, V_TIMERRESOLUTION(tre) |  in tp_set_timers()
2711 	t3_write_reg(adap, A_TP_DACK_TIMER,  in tp_set_timers()
2713 	t3_write_reg(adap, A_TP_TCP_BACKOFF_REG0, 0x3020100);  in tp_set_timers()
2714 	t3_write_reg(adap, A_TP_TCP_BACKOFF_REG1, 0x7060504);  in tp_set_timers()
2715 	t3_write_reg(adap, A_TP_TCP_BACKOFF_REG2, 0xb0a0908);  in tp_set_timers()
2716 	t3_write_reg(adap, A_TP_TCP_BACKOFF_REG3, 0xf0e0d0c);  in tp_set_timers()
2717 	t3_write_reg(adap, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) |  in tp_set_timers()
2724 	t3_write_reg(adap, A_TP_MSL, adap->params.rev > 0 ? 0 : 2 SECONDS);  in tp_set_timers()
2725 	t3_write_reg(adap, A_TP_RXT_MIN, tps / (1000 / TP_RTO_MIN));  in tp_set_timers()
2726 	t3_write_reg(adap, A_TP_RXT_MAX, 64 SECONDS);  in tp_set_timers()
2727 	t3_write_reg(adap, A_TP_PERS_MIN, 5 SECONDS);  in tp_set_timers()
2728 	t3_write_reg(adap, A_TP_PERS_MAX, 64 SECONDS);  in tp_set_timers()
2729 	t3_write_reg(adap, A_TP_KEEP_IDLE, 7200 SECONDS);  in tp_set_timers()
2730 	t3_write_reg(adap, A_TP_KEEP_INTVL, 75 SECONDS);  in tp_set_timers()
2731 	t3_write_reg(adap, A_TP_INIT_SRTT, 3 SECONDS);  in tp_set_timers()
2732 	t3_write_reg(adap, A_TP_FINWAIT2_TIMER, 600 SECONDS);  in tp_set_timers()
2745 static int t3_tp_set_coalescing_size(struct adapter *adap,  in t3_tp_set_coalescing_size()  argument
2753 	val = t3_read_reg(adap, A_TP_PARA_REG3);  in t3_tp_set_coalescing_size()
2761 		t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) |  in t3_tp_set_coalescing_size()
2764 	t3_write_reg(adap, A_TP_PARA_REG3, val);  in t3_tp_set_coalescing_size()
2776 static void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size)  in t3_tp_set_max_rxsize()  argument
2778 	t3_write_reg(adap, A_TP_PARA_REG7,  in t3_tp_set_max_rxsize()
2862 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],  in t3_load_mtus()  argument
2880 		t3_write_reg(adap, A_TP_MTU_TABLE,  in t3_load_mtus()
2889 			t3_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |  in t3_load_mtus()
2902 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps)  in t3_tp_get_mib_stats()  argument
2904 	t3_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_RDATA, (u32 *) tps,  in t3_tp_get_mib_stats()
2908 #define ulp_region(adap, name, start, len) \  argument
2909 	t3_write_reg((adap), A_ULPRX_ ## name ## _LLIMIT, (start)); \
2910 	t3_write_reg((adap), A_ULPRX_ ## name ## _ULIMIT, \
2914 #define ulptx_region(adap, name, start, len) \  argument
2915 	t3_write_reg((adap), A_ULPTX_ ## name ## _LLIMIT, (start)); \
2916 	t3_write_reg((adap), A_ULPTX_ ## name ## _ULIMIT, \
2919 static void ulp_config(struct adapter *adap, const struct tp_params *p)  in ulp_config()  argument
2923 	ulp_region(adap, ISCSI, m, p->chan_rx_size / 8);  in ulp_config()
2924 	ulp_region(adap, TDDP, m, p->chan_rx_size / 8);  in ulp_config()
2925 	ulptx_region(adap, TPT, m, p->chan_rx_size / 4);  in ulp_config()
2926 	ulp_region(adap, STAG, m, p->chan_rx_size / 4);  in ulp_config()
2927 	ulp_region(adap, RQ, m, p->chan_rx_size / 4);  in ulp_config()
2928 	ulptx_region(adap, PBL, m, p->chan_rx_size / 4);  in ulp_config()
2929 	ulp_region(adap, PBL, m, p->chan_rx_size / 4);  in ulp_config()
2930 	t3_write_reg(adap, A_ULPRX_TDDP_TAGMASK, 0xffffffff);  in ulp_config()
2940 int t3_set_proto_sram(struct adapter *adap, const u8 *data)  in t3_set_proto_sram()  argument
2946 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, be32_to_cpu(*buf++));  in t3_set_proto_sram()
2947 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, be32_to_cpu(*buf++));  in t3_set_proto_sram()
2948 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, be32_to_cpu(*buf++));  in t3_set_proto_sram()
2949 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, be32_to_cpu(*buf++));  in t3_set_proto_sram()
2950 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, be32_to_cpu(*buf++));  in t3_set_proto_sram()
2952 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);  in t3_set_proto_sram()
2953 		if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1))  in t3_set_proto_sram()
2956 	t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, 0);  in t3_set_proto_sram()
3002 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched)  in t3_config_sched()  argument
3005 	unsigned int clk = adap->params.vpd.cclk * 1000;  in t3_config_sched()
3027 	t3_write_reg(adap, A_TP_TM_PIO_ADDR,  in t3_config_sched()
3029 	v = t3_read_reg(adap, A_TP_TM_PIO_DATA);  in t3_config_sched()
3034 	t3_write_reg(adap, A_TP_TM_PIO_DATA, v);  in t3_config_sched()
3038 static int tp_init(struct adapter *adap, const struct tp_params *p)  in tp_init()  argument
3042 	tp_config(adap, p);  in tp_init()
3043 	t3_set_vlan_accel(adap, 3, 0);  in tp_init()
3045 	if (is_offload(adap)) {  in tp_init()
3046 		tp_set_timers(adap, adap->params.vpd.cclk * 1000);  in tp_init()
3047 		t3_write_reg(adap, A_TP_RESET, F_FLSTINITENABLE);  in tp_init()
3048 		busy = t3_wait_op_done(adap, A_TP_RESET, F_FLSTINITENABLE,  in tp_init()
3051 			CH_ERR(adap, "TP initialization timed out\n");  in tp_init()
3055 		t3_write_reg(adap, A_TP_RESET, F_TPRESET);  in tp_init()
3063 static void chan_init_hw(struct adapter *adap, unsigned int chan_map)  in chan_init_hw()  argument
3068 		t3_set_reg_field(adap, A_ULPRX_CTL, F_ROUND_ROBIN, 0);  in chan_init_hw()
3069 		t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0);  in chan_init_hw()
3070 		t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_ENFORCEPKT |  in chan_init_hw()
3073 		t3_write_reg(adap, A_PM1_TX_CFG,  in chan_init_hw()
3076 		t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN);  in chan_init_hw()
3077 		t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB);  in chan_init_hw()
3078 		t3_write_reg(adap, A_ULPTX_DMA_WEIGHT,  in chan_init_hw()
3080 		t3_write_reg(adap, A_MPS_CFG, F_TPTXPORT0EN | F_TPTXPORT1EN |  in chan_init_hw()
3083 		t3_write_reg(adap, A_PM1_TX_CFG, 0x80008000);  in chan_init_hw()
3084 		t3_set_reg_field(adap, A_TP_PC_CONFIG, 0, F_TXTOSQUEUEMAPMODE);  in chan_init_hw()
3085 		t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,  in chan_init_hw()
3088 			t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE,  in chan_init_hw()
3273 static void config_pcie(struct adapter *adap)  in config_pcie()  argument
3292 	pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL, &val);  in config_pcie()
3295 	pci_read_config_word(adap->pdev, 0x2, &devid);  in config_pcie()
3297 		pcie_capability_write_word(adap->pdev, PCI_EXP_DEVCTL,  in config_pcie()
3303 	pcie_capability_read_word(adap->pdev, PCI_EXP_LNKCTL, &val);  in config_pcie()
3305 	fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));  in config_pcie()
3306 	fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx :  in config_pcie()
3307 	    G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));  in config_pcie()
3308 	log2_width = fls(adap->params.pci.width) - 1;  in config_pcie()
3314 	if (adap->params.rev == 0)  in config_pcie()
3315 		t3_set_reg_field(adap, A_PCIE_PEX_CTRL1,  in config_pcie()
3319 		t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_ACKLAT(M_ACKLAT),  in config_pcie()
3322 	t3_set_reg_field(adap, A_PCIE_PEX_CTRL0, V_REPLAYLMT(M_REPLAYLMT),  in config_pcie()
3325 	t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);  in config_pcie()
3326 	t3_set_reg_field(adap, A_PCIE_CFG, 0,  in config_pcie()
3586 static int init_parity(struct adapter *adap)  in init_parity()  argument
3590 	if (t3_read_reg(adap, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)  in init_parity()
3594 		err = clear_sge_ctxt(adap, i, F_EGRESS);  in init_parity()
3596 		err = clear_sge_ctxt(adap, i, F_EGRESS);  in init_parity()
3598 		err = clear_sge_ctxt(adap, i, F_RESPONSEQ);  in init_parity()
3602 	t3_write_reg(adap, A_CIM_IBQ_DBG_DATA, 0);  in init_parity()
3605 			t3_write_reg(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGEN |  in init_parity()
3608 			err = t3_wait_op_done(adap, A_CIM_IBQ_DBG_CFG,  in init_parity()