45 static void lio_cn68xx_set_dpi_regs(struct octeon_device *oct)  in lio_cn68xx_set_dpi_regs()  argument
50 	lio_pci_writeq(oct, CN6XXX_DPI_DMA_CTL_MASK, CN6XXX_DPI_DMA_CONTROL);  in lio_cn68xx_set_dpi_regs()
51 	dev_dbg(&oct->pci_dev->dev, "DPI_DMA_CONTROL: 0x%016llx\n",  in lio_cn68xx_set_dpi_regs()
52 		lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL));  in lio_cn68xx_set_dpi_regs()
59 		lio_pci_writeq(oct, 0, CN6XXX_DPI_DMA_ENG_ENB(i));  in lio_cn68xx_set_dpi_regs()
60 		lio_pci_writeq(oct, fifo_sizes[i], CN6XXX_DPI_DMA_ENG_BUF(i));  in lio_cn68xx_set_dpi_regs()
61 		dev_dbg(&oct->pci_dev->dev, "DPI_ENG_BUF%d: 0x%016llx\n", i,  in lio_cn68xx_set_dpi_regs()
62 			lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i)));  in lio_cn68xx_set_dpi_regs()
69 	lio_pci_writeq(oct, 1, CN6XXX_DPI_CTL);  in lio_cn68xx_set_dpi_regs()
70 	dev_dbg(&oct->pci_dev->dev, "DPI_CTL: 0x%016llx\n",  in lio_cn68xx_set_dpi_regs()
71 		lio_pci_readq(oct, CN6XXX_DPI_CTL));  in lio_cn68xx_set_dpi_regs()
74 static int lio_cn68xx_soft_reset(struct octeon_device *oct)  in lio_cn68xx_soft_reset()  argument
76 	lio_cn6xxx_soft_reset(oct);  in lio_cn68xx_soft_reset()
77 	lio_cn68xx_set_dpi_regs(oct);  in lio_cn68xx_soft_reset()
82 static void lio_cn68xx_setup_pkt_ctl_regs(struct octeon_device *oct)  in lio_cn68xx_setup_pkt_ctl_regs()  argument
84 	struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip;  in lio_cn68xx_setup_pkt_ctl_regs()
87 	pktctl = octeon_read_csr64(oct, CN6XXX_SLI_PKT_CTL);  in lio_cn68xx_setup_pkt_ctl_regs()
90 	max_oqs = CFG_GET_OQ_MAX_Q(CHIP_FIELD(oct, cn6xxx, conf));  in lio_cn68xx_setup_pkt_ctl_regs()
91 	tx_pipe  = octeon_read_csr64(oct, CN68XX_SLI_TX_PIPE);  in lio_cn68xx_setup_pkt_ctl_regs()
94 	octeon_write_csr64(oct, CN68XX_SLI_TX_PIPE, tx_pipe);  in lio_cn68xx_setup_pkt_ctl_regs()
101 	octeon_write_csr64(oct, CN6XXX_SLI_PKT_CTL, pktctl);  in lio_cn68xx_setup_pkt_ctl_regs()
104 static int lio_cn68xx_setup_device_regs(struct octeon_device *oct)  in lio_cn68xx_setup_device_regs()  argument
106 	lio_cn6xxx_setup_pcie_mps(oct, PCIE_MPS_DEFAULT);  in lio_cn68xx_setup_device_regs()
107 	lio_cn6xxx_setup_pcie_mrrs(oct, PCIE_MRRS_256B);  in lio_cn68xx_setup_device_regs()
108 	lio_cn6xxx_enable_error_reporting(oct);  in lio_cn68xx_setup_device_regs()
110 	lio_cn6xxx_setup_global_input_regs(oct);  in lio_cn68xx_setup_device_regs()
111 	lio_cn68xx_setup_pkt_ctl_regs(oct);  in lio_cn68xx_setup_device_regs()
112 	lio_cn6xxx_setup_global_output_regs(oct);  in lio_cn68xx_setup_device_regs()
117 	octeon_write_csr64(oct, CN6XXX_SLI_WINDOW_CTL, 0x200000ULL);  in lio_cn68xx_setup_device_regs()
122 static inline void lio_cn68xx_vendor_message_fix(struct octeon_device *oct)  in lio_cn68xx_vendor_message_fix()  argument
127 	pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, &val);  in lio_cn68xx_vendor_message_fix()
129 	pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, val);  in lio_cn68xx_vendor_message_fix()
132 int lio_is_210nv(struct octeon_device *oct)  in lio_is_210nv()  argument
134 	u64 mio_qlm4_cfg = lio_pci_readq(oct, CN6XXX_MIO_QLM4_CFG);  in lio_is_210nv()
139 int lio_setup_cn68xx_octeon_device(struct octeon_device *oct)  in lio_setup_cn68xx_octeon_device()  argument
141 	struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip;  in lio_setup_cn68xx_octeon_device()
144 	if (octeon_map_pci_barx(oct, 0, 0))  in lio_setup_cn68xx_octeon_device()
147 	if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) {  in lio_setup_cn68xx_octeon_device()
148 		dev_err(&oct->pci_dev->dev, "%s CN68XX BAR1 map failed\n",  in lio_setup_cn68xx_octeon_device()
150 		octeon_unmap_pci_barx(oct, 0);  in lio_setup_cn68xx_octeon_device()
156 	oct->fn_list.setup_iq_regs = lio_cn6xxx_setup_iq_regs;  in lio_setup_cn68xx_octeon_device()
157 	oct->fn_list.setup_oq_regs = lio_cn6xxx_setup_oq_regs;  in lio_setup_cn68xx_octeon_device()
159 	oct->fn_list.process_interrupt_regs = lio_cn6xxx_process_interrupt_regs;  in lio_setup_cn68xx_octeon_device()
160 	oct->fn_list.soft_reset = lio_cn68xx_soft_reset;  in lio_setup_cn68xx_octeon_device()
161 	oct->fn_list.setup_device_regs = lio_cn68xx_setup_device_regs;  in lio_setup_cn68xx_octeon_device()
162 	oct->fn_list.reinit_regs = lio_cn6xxx_reinit_regs;  in lio_setup_cn68xx_octeon_device()
163 	oct->fn_list.update_iq_read_idx = lio_cn6xxx_update_read_index;  in lio_setup_cn68xx_octeon_device()
165 	oct->fn_list.bar1_idx_setup = lio_cn6xxx_bar1_idx_setup;  in lio_setup_cn68xx_octeon_device()
166 	oct->fn_list.bar1_idx_write = lio_cn6xxx_bar1_idx_write;  in lio_setup_cn68xx_octeon_device()
167 	oct->fn_list.bar1_idx_read = lio_cn6xxx_bar1_idx_read;  in lio_setup_cn68xx_octeon_device()
169 	oct->fn_list.enable_interrupt = lio_cn6xxx_enable_interrupt;  in lio_setup_cn68xx_octeon_device()
170 	oct->fn_list.disable_interrupt = lio_cn6xxx_disable_interrupt;  in lio_setup_cn68xx_octeon_device()
172 	oct->fn_list.enable_io_queues = lio_cn6xxx_enable_io_queues;  in lio_setup_cn68xx_octeon_device()
173 	oct->fn_list.disable_io_queues = lio_cn6xxx_disable_io_queues;  in lio_setup_cn68xx_octeon_device()
175 	lio_cn6xxx_setup_reg_address(oct, oct->chip, &oct->reg_list);  in lio_setup_cn68xx_octeon_device()
178 	if (lio_is_210nv(oct))  in lio_setup_cn68xx_octeon_device()
182 		       oct_get_config_info(oct, card_type);  in lio_setup_cn68xx_octeon_device()
184 		dev_err(&oct->pci_dev->dev, "%s No Config found for CN68XX %s\n",  in lio_setup_cn68xx_octeon_device()
188 		octeon_unmap_pci_barx(oct, 0);  in lio_setup_cn68xx_octeon_device()
189 		octeon_unmap_pci_barx(oct, 1);  in lio_setup_cn68xx_octeon_device()
193 	oct->coproc_clock_rate = 1000000ULL * lio_cn6xxx_coprocessor_clock(oct);  in lio_setup_cn68xx_octeon_device()
195 	lio_cn68xx_vendor_message_fix(oct);  in lio_setup_cn68xx_octeon_device()