Lines Matching refs:oct
43 int lio_cn6xxx_soft_reset(struct octeon_device *oct) in lio_cn6xxx_soft_reset() argument
45 octeon_write_csr64(oct, CN6XXX_WIN_WR_MASK_REG, 0xFF); in lio_cn6xxx_soft_reset()
47 dev_dbg(&oct->pci_dev->dev, "BIST enabled for soft reset\n"); in lio_cn6xxx_soft_reset()
49 lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_BIST); in lio_cn6xxx_soft_reset()
50 octeon_write_csr64(oct, CN6XXX_SLI_SCRATCH1, 0x1234ULL); in lio_cn6xxx_soft_reset()
52 lio_pci_readq(oct, CN6XXX_CIU_SOFT_RST); in lio_cn6xxx_soft_reset()
53 lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_RST); in lio_cn6xxx_soft_reset()
61 if (octeon_read_csr64(oct, CN6XXX_SLI_SCRATCH1) == 0x1234ULL) { in lio_cn6xxx_soft_reset()
62 dev_err(&oct->pci_dev->dev, "Soft reset failed\n"); in lio_cn6xxx_soft_reset()
66 dev_dbg(&oct->pci_dev->dev, "Reset completed\n"); in lio_cn6xxx_soft_reset()
67 octeon_write_csr64(oct, CN6XXX_WIN_WR_MASK_REG, 0xFF); in lio_cn6xxx_soft_reset()
72 void lio_cn6xxx_enable_error_reporting(struct octeon_device *oct) in lio_cn6xxx_enable_error_reporting() argument
76 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_enable_error_reporting()
78 dev_err(&oct->pci_dev->dev, "PCI-E Link error detected: 0x%08x\n", in lio_cn6xxx_enable_error_reporting()
84 dev_dbg(&oct->pci_dev->dev, "Enabling PCI-E error reporting..\n"); in lio_cn6xxx_enable_error_reporting()
85 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); in lio_cn6xxx_enable_error_reporting()
88 void lio_cn6xxx_setup_pcie_mps(struct octeon_device *oct, in lio_cn6xxx_setup_pcie_mps() argument
95 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_setup_pcie_mps()
102 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); in lio_cn6xxx_setup_pcie_mps()
106 r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mps()
108 lio_pci_writeq(oct, r64, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mps()
111 void lio_cn6xxx_setup_pcie_mrrs(struct octeon_device *oct, in lio_cn6xxx_setup_pcie_mrrs() argument
118 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_setup_pcie_mrrs()
125 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); in lio_cn6xxx_setup_pcie_mrrs()
129 r64 = octeon_read_csr64(oct, CN6XXX_SLI_S2M_PORTX_CTL(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
131 octeon_write_csr64(oct, CN6XXX_SLI_S2M_PORTX_CTL(oct->pcie_port), r64); in lio_cn6xxx_setup_pcie_mrrs()
134 r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
136 lio_pci_writeq(oct, r64, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
139 u32 lio_cn6xxx_coprocessor_clock(struct octeon_device *oct) in lio_cn6xxx_coprocessor_clock() argument
144 return ((lio_pci_readq(oct, CN6XXX_MIO_RST_BOOT) >> 24) & 0x3f) * 50; in lio_cn6xxx_coprocessor_clock()
147 u32 lio_cn6xxx_get_oq_ticks(struct octeon_device *oct, in lio_cn6xxx_get_oq_ticks() argument
151 u32 oqticks_per_us = lio_cn6xxx_coprocessor_clock(oct); in lio_cn6xxx_get_oq_ticks()
172 void lio_cn6xxx_setup_global_input_regs(struct octeon_device *oct) in lio_cn6xxx_setup_global_input_regs() argument
175 octeon_write_csr(oct, CN6XXX_SLI_PKT_INPUT_CONTROL, in lio_cn6xxx_setup_global_input_regs()
179 octeon_write_csr64(oct, CN6XXX_SLI_PKT_INSTR_RD_SIZE, in lio_cn6xxx_setup_global_input_regs()
183 octeon_write_csr64(oct, CN6XXX_SLI_IN_PCIE_PORT, in lio_cn6xxx_setup_global_input_regs()
184 (oct->pcie_port * 0x5555555555555555ULL)); in lio_cn6xxx_setup_global_input_regs()
187 static void lio_cn66xx_setup_pkt_ctl_regs(struct octeon_device *oct) in lio_cn66xx_setup_pkt_ctl_regs() argument
191 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn66xx_setup_pkt_ctl_regs()
193 pktctl = octeon_read_csr64(oct, CN6XXX_SLI_PKT_CTL); in lio_cn66xx_setup_pkt_ctl_regs()
207 octeon_write_csr64(oct, CN6XXX_SLI_PKT_CTL, pktctl); in lio_cn66xx_setup_pkt_ctl_regs()
210 void lio_cn6xxx_setup_global_output_regs(struct octeon_device *oct) in lio_cn6xxx_setup_global_output_regs() argument
213 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_setup_global_output_regs()
216 octeon_write_csr64(oct, CN6XXX_SLI_PKT_PCIE_PORT64, in lio_cn6xxx_setup_global_output_regs()
217 (oct->pcie_port * 0x5555555555555555ULL)); in lio_cn6xxx_setup_global_output_regs()
220 octeon_write_csr64(oct, CN6XXX_SLI_OQ_WMARK, 32); in lio_cn6xxx_setup_global_output_regs()
223 octeon_write_csr64(oct, CN6XXX_SLI_OQ_WMARK, 0); in lio_cn6xxx_setup_global_output_regs()
227 octeon_write_csr(oct, CN6XXX_SLI_PKT_IPTR, 0xFFFFFFFF); in lio_cn6xxx_setup_global_output_regs()
230 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_BMODE, 0); in lio_cn6xxx_setup_global_output_regs()
235 octeon_write_csr(oct, CN6XXX_SLI_PKT_DPADDR, 0xFFFFFFFF); in lio_cn6xxx_setup_global_output_regs()
240 octeon_write_csr(oct, CN6XXX_SLI_PKT_SLIST_ROR, 0); in lio_cn6xxx_setup_global_output_regs()
241 octeon_write_csr(oct, CN6XXX_SLI_PKT_SLIST_NS, 0); in lio_cn6xxx_setup_global_output_regs()
245 octeon_write_csr64(oct, CN6XXX_SLI_PKT_SLIST_ES64, in lio_cn6xxx_setup_global_output_regs()
248 octeon_write_csr64(oct, CN6XXX_SLI_PKT_SLIST_ES64, 0ULL); in lio_cn6xxx_setup_global_output_regs()
252 octeon_write_csr(oct, CN6XXX_SLI_PKT_DATA_OUT_ROR, 0); in lio_cn6xxx_setup_global_output_regs()
253 octeon_write_csr(oct, CN6XXX_SLI_PKT_DATA_OUT_NS, 0); in lio_cn6xxx_setup_global_output_regs()
254 octeon_write_csr64(oct, CN6XXX_SLI_PKT_DATA_OUT_ES64, in lio_cn6xxx_setup_global_output_regs()
258 octeon_write_csr(oct, CN6XXX_SLI_OQ_INT_LEVEL_PKTS, in lio_cn6xxx_setup_global_output_regs()
261 lio_cn6xxx_get_oq_ticks(oct, (u32) in lio_cn6xxx_setup_global_output_regs()
264 octeon_write_csr(oct, CN6XXX_SLI_OQ_INT_LEVEL_TIME, time_threshold); in lio_cn6xxx_setup_global_output_regs()
267 static int lio_cn6xxx_setup_device_regs(struct octeon_device *oct) in lio_cn6xxx_setup_device_regs() argument
269 lio_cn6xxx_setup_pcie_mps(oct, PCIE_MPS_DEFAULT); in lio_cn6xxx_setup_device_regs()
270 lio_cn6xxx_setup_pcie_mrrs(oct, PCIE_MRRS_512B); in lio_cn6xxx_setup_device_regs()
271 lio_cn6xxx_enable_error_reporting(oct); in lio_cn6xxx_setup_device_regs()
273 lio_cn6xxx_setup_global_input_regs(oct); in lio_cn6xxx_setup_device_regs()
274 lio_cn66xx_setup_pkt_ctl_regs(oct); in lio_cn6xxx_setup_device_regs()
275 lio_cn6xxx_setup_global_output_regs(oct); in lio_cn6xxx_setup_device_regs()
280 octeon_write_csr64(oct, CN6XXX_SLI_WINDOW_CTL, 0x200000ULL); in lio_cn6xxx_setup_device_regs()
284 void lio_cn6xxx_setup_iq_regs(struct octeon_device *oct, u32 iq_no) in lio_cn6xxx_setup_iq_regs() argument
286 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; in lio_cn6xxx_setup_iq_regs()
289 octeon_write_csr64(oct, CN6XXX_SLI_IQ_PKT_INSTR_HDR64(iq_no), 0); in lio_cn6xxx_setup_iq_regs()
292 octeon_write_csr64(oct, CN6XXX_SLI_IQ_BASE_ADDR64(iq_no), in lio_cn6xxx_setup_iq_regs()
294 octeon_write_csr(oct, CN6XXX_SLI_IQ_SIZE(iq_no), iq->max_count); in lio_cn6xxx_setup_iq_regs()
299 iq->doorbell_reg = oct->mmio[0].hw_addr + CN6XXX_SLI_IQ_DOORBELL(iq_no); in lio_cn6xxx_setup_iq_regs()
300 iq->inst_cnt_reg = oct->mmio[0].hw_addr in lio_cn6xxx_setup_iq_regs()
302 dev_dbg(&oct->pci_dev->dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n", in lio_cn6xxx_setup_iq_regs()
311 static void lio_cn66xx_setup_iq_regs(struct octeon_device *oct, u32 iq_no) in lio_cn66xx_setup_iq_regs() argument
313 lio_cn6xxx_setup_iq_regs(oct, iq_no); in lio_cn66xx_setup_iq_regs()
318 octeon_write_csr64(oct, CN66XX_SLI_IQ_BP64(iq_no), in lio_cn66xx_setup_iq_regs()
322 void lio_cn6xxx_setup_oq_regs(struct octeon_device *oct, u32 oq_no) in lio_cn6xxx_setup_oq_regs() argument
325 struct octeon_droq *droq = oct->droq[oq_no]; in lio_cn6xxx_setup_oq_regs()
327 octeon_write_csr64(oct, CN6XXX_SLI_OQ_BASE_ADDR64(oq_no), in lio_cn6xxx_setup_oq_regs()
329 octeon_write_csr(oct, CN6XXX_SLI_OQ_SIZE(oq_no), droq->max_count); in lio_cn6xxx_setup_oq_regs()
331 octeon_write_csr(oct, CN6XXX_SLI_OQ_BUFF_INFO_SIZE(oq_no), in lio_cn6xxx_setup_oq_regs()
336 oct->mmio[0].hw_addr + CN6XXX_SLI_OQ_PKTS_SENT(oq_no); in lio_cn6xxx_setup_oq_regs()
338 oct->mmio[0].hw_addr + CN6XXX_SLI_OQ_PKTS_CREDIT(oq_no); in lio_cn6xxx_setup_oq_regs()
341 intr = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB); in lio_cn6xxx_setup_oq_regs()
343 octeon_write_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB, intr); in lio_cn6xxx_setup_oq_regs()
346 intr = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB); in lio_cn6xxx_setup_oq_regs()
348 octeon_write_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB, intr); in lio_cn6xxx_setup_oq_regs()
351 void lio_cn6xxx_enable_io_queues(struct octeon_device *oct) in lio_cn6xxx_enable_io_queues() argument
355 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_SIZE); in lio_cn6xxx_enable_io_queues()
356 mask |= oct->io_qmask.iq64B; in lio_cn6xxx_enable_io_queues()
357 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_SIZE, mask); in lio_cn6xxx_enable_io_queues()
359 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); in lio_cn6xxx_enable_io_queues()
360 mask |= oct->io_qmask.iq; in lio_cn6xxx_enable_io_queues()
361 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, mask); in lio_cn6xxx_enable_io_queues()
363 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in lio_cn6xxx_enable_io_queues()
364 mask |= oct->io_qmask.oq; in lio_cn6xxx_enable_io_queues()
365 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, mask); in lio_cn6xxx_enable_io_queues()
368 void lio_cn6xxx_disable_io_queues(struct octeon_device *oct) in lio_cn6xxx_disable_io_queues() argument
374 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); in lio_cn6xxx_disable_io_queues()
375 mask ^= oct->io_qmask.iq; in lio_cn6xxx_disable_io_queues()
376 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, mask); in lio_cn6xxx_disable_io_queues()
379 mask = oct->io_qmask.iq; in lio_cn6xxx_disable_io_queues()
380 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_IQ); in lio_cn6xxx_disable_io_queues()
382 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_IQ); in lio_cn6xxx_disable_io_queues()
388 if (!(oct->io_qmask.iq & (1UL << i))) in lio_cn6xxx_disable_io_queues()
390 octeon_write_csr(oct, CN6XXX_SLI_IQ_DOORBELL(i), 0xFFFFFFFF); in lio_cn6xxx_disable_io_queues()
391 d32 = octeon_read_csr(oct, CN6XXX_SLI_IQ_DOORBELL(i)); in lio_cn6xxx_disable_io_queues()
395 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in lio_cn6xxx_disable_io_queues()
396 mask ^= oct->io_qmask.oq; in lio_cn6xxx_disable_io_queues()
397 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, mask); in lio_cn6xxx_disable_io_queues()
401 mask = oct->io_qmask.oq; in lio_cn6xxx_disable_io_queues()
402 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_OQ); in lio_cn6xxx_disable_io_queues()
404 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_OQ); in lio_cn6xxx_disable_io_queues()
412 if (!(oct->io_qmask.oq & (1UL << i))) in lio_cn6xxx_disable_io_queues()
414 octeon_write_csr(oct, CN6XXX_SLI_OQ_PKTS_CREDIT(i), 0xFFFFFFFF); in lio_cn6xxx_disable_io_queues()
415 d32 = octeon_read_csr(oct, CN6XXX_SLI_OQ_PKTS_CREDIT(i)); in lio_cn6xxx_disable_io_queues()
417 d32 = octeon_read_csr(oct, CN6XXX_SLI_OQ_PKTS_SENT(i)); in lio_cn6xxx_disable_io_queues()
418 octeon_write_csr(oct, CN6XXX_SLI_OQ_PKTS_SENT(i), d32); in lio_cn6xxx_disable_io_queues()
421 d32 = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT); in lio_cn6xxx_disable_io_queues()
423 octeon_write_csr(oct, CN6XXX_SLI_PKT_CNT_INT, d32); in lio_cn6xxx_disable_io_queues()
425 d32 = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT); in lio_cn6xxx_disable_io_queues()
427 octeon_write_csr(oct, CN6XXX_SLI_PKT_TIME_INT, d32); in lio_cn6xxx_disable_io_queues()
430 void lio_cn6xxx_reinit_regs(struct octeon_device *oct) in lio_cn6xxx_reinit_regs() argument
435 if (!(oct->io_qmask.iq & (1UL << i))) in lio_cn6xxx_reinit_regs()
437 oct->fn_list.setup_iq_regs(oct, i); in lio_cn6xxx_reinit_regs()
441 if (!(oct->io_qmask.oq & (1UL << i))) in lio_cn6xxx_reinit_regs()
443 oct->fn_list.setup_oq_regs(oct, i); in lio_cn6xxx_reinit_regs()
446 oct->fn_list.setup_device_regs(oct); in lio_cn6xxx_reinit_regs()
448 oct->fn_list.enable_interrupt(oct->chip); in lio_cn6xxx_reinit_regs()
450 oct->fn_list.enable_io_queues(oct); in lio_cn6xxx_reinit_regs()
454 if (!(oct->io_qmask.oq & (1UL << i))) in lio_cn6xxx_reinit_regs()
456 writel(oct->droq[i]->max_count, oct->droq[i]->pkts_credit_reg); in lio_cn6xxx_reinit_regs()
461 lio_cn6xxx_bar1_idx_setup(struct octeon_device *oct, in lio_cn6xxx_bar1_idx_setup() argument
469 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
470 lio_pci_writeq(oct, (bar1 & 0xFFFFFFFEULL), in lio_cn6xxx_bar1_idx_setup()
471 CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
472 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
479 lio_pci_writeq(oct, (((core_addr >> 22) << 4) | PCI_BAR1_MASK), in lio_cn6xxx_bar1_idx_setup()
480 CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
482 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
485 void lio_cn6xxx_bar1_idx_write(struct octeon_device *oct, in lio_cn6xxx_bar1_idx_write() argument
489 lio_pci_writeq(oct, mask, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_write()
492 u32 lio_cn6xxx_bar1_idx_read(struct octeon_device *oct, u32 idx) in lio_cn6xxx_bar1_idx_read() argument
494 return (u32)lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_read()
498 lio_cn6xxx_update_read_index(struct octeon_device *oct __attribute__((unused)), in lio_cn6xxx_update_read_index() argument
540 static void lio_cn6xxx_get_pcie_qlmport(struct octeon_device *oct) in lio_cn6xxx_get_pcie_qlmport() argument
545 oct->pcie_port = octeon_read_csr(oct, CN6XXX_SLI_MAC_NUMBER) & 0xff; in lio_cn6xxx_get_pcie_qlmport()
547 dev_dbg(&oct->pci_dev->dev, "Using PCIE Port %d\n", oct->pcie_port); in lio_cn6xxx_get_pcie_qlmport()
551 lio_cn6xxx_process_pcie_error_intr(struct octeon_device *oct, u64 intr64) in lio_cn6xxx_process_pcie_error_intr() argument
553 dev_err(&oct->pci_dev->dev, "Error Intr: 0x%016llx\n", in lio_cn6xxx_process_pcie_error_intr()
557 int lio_cn6xxx_process_droq_intr_regs(struct octeon_device *oct) in lio_cn6xxx_process_droq_intr_regs() argument
563 droq_cnt_enb = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB); in lio_cn6xxx_process_droq_intr_regs()
564 droq_cnt_mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT); in lio_cn6xxx_process_droq_intr_regs()
567 droq_time_mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT); in lio_cn6xxx_process_droq_intr_regs()
568 droq_int_enb = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB); in lio_cn6xxx_process_droq_intr_regs()
571 droq_mask &= oct->io_qmask.oq; in lio_cn6xxx_process_droq_intr_regs()
573 oct->droq_intr = 0; in lio_cn6xxx_process_droq_intr_regs()
580 droq = oct->droq[oq_no]; in lio_cn6xxx_process_droq_intr_regs()
581 pkt_count = octeon_droq_check_hw_for_pkts(oct, droq); in lio_cn6xxx_process_droq_intr_regs()
583 oct->droq_intr |= (1ULL << oq_no); in lio_cn6xxx_process_droq_intr_regs()
589 (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_process_droq_intr_regs()
595 value = octeon_read_csr(oct, reg); in lio_cn6xxx_process_droq_intr_regs()
597 octeon_write_csr(oct, reg, value); in lio_cn6xxx_process_droq_intr_regs()
599 value = octeon_read_csr(oct, reg); in lio_cn6xxx_process_droq_intr_regs()
601 octeon_write_csr(oct, reg, value); in lio_cn6xxx_process_droq_intr_regs()
612 droq_time_mask &= oct->io_qmask.oq; in lio_cn6xxx_process_droq_intr_regs()
613 droq_cnt_mask &= oct->io_qmask.oq; in lio_cn6xxx_process_droq_intr_regs()
617 octeon_write_csr(oct, CN6XXX_SLI_PKT_TIME_INT, droq_time_mask); in lio_cn6xxx_process_droq_intr_regs()
620 octeon_write_csr(oct, CN6XXX_SLI_PKT_CNT_INT, droq_cnt_mask); in lio_cn6xxx_process_droq_intr_regs()
627 struct octeon_device *oct = (struct octeon_device *)dev; in lio_cn6xxx_process_interrupt_regs() local
628 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_process_interrupt_regs()
640 oct->int_status = 0; in lio_cn6xxx_process_interrupt_regs()
643 lio_cn6xxx_process_pcie_error_intr(oct, intr64); in lio_cn6xxx_process_interrupt_regs()
646 lio_cn6xxx_process_droq_intr_regs(oct); in lio_cn6xxx_process_interrupt_regs()
647 oct->int_status |= OCT_DEV_INTR_PKT_DATA; in lio_cn6xxx_process_interrupt_regs()
651 oct->int_status |= OCT_DEV_INTR_DMA0_FORCE; in lio_cn6xxx_process_interrupt_regs()
654 oct->int_status |= OCT_DEV_INTR_DMA1_FORCE; in lio_cn6xxx_process_interrupt_regs()
662 void lio_cn6xxx_setup_reg_address(struct octeon_device *oct, in lio_cn6xxx_setup_reg_address() argument
666 u8 __iomem *bar0_pciaddr = oct->mmio[0].hw_addr; in lio_cn6xxx_setup_reg_address()
697 lio_cn6xxx_get_pcie_qlmport(oct); in lio_cn6xxx_setup_reg_address()
702 bar0_pciaddr + CN6XXX_SLI_INT_ENB64(oct->pcie_port); in lio_cn6xxx_setup_reg_address()
705 int lio_setup_cn66xx_octeon_device(struct octeon_device *oct) in lio_setup_cn66xx_octeon_device() argument
707 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_setup_cn66xx_octeon_device()
709 if (octeon_map_pci_barx(oct, 0, 0)) in lio_setup_cn66xx_octeon_device()
712 if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) { in lio_setup_cn66xx_octeon_device()
713 dev_err(&oct->pci_dev->dev, "%s CN66XX BAR1 map failed\n", in lio_setup_cn66xx_octeon_device()
715 octeon_unmap_pci_barx(oct, 0); in lio_setup_cn66xx_octeon_device()
721 oct->fn_list.setup_iq_regs = lio_cn66xx_setup_iq_regs; in lio_setup_cn66xx_octeon_device()
722 oct->fn_list.setup_oq_regs = lio_cn6xxx_setup_oq_regs; in lio_setup_cn66xx_octeon_device()
724 oct->fn_list.soft_reset = lio_cn6xxx_soft_reset; in lio_setup_cn66xx_octeon_device()
725 oct->fn_list.setup_device_regs = lio_cn6xxx_setup_device_regs; in lio_setup_cn66xx_octeon_device()
726 oct->fn_list.reinit_regs = lio_cn6xxx_reinit_regs; in lio_setup_cn66xx_octeon_device()
727 oct->fn_list.update_iq_read_idx = lio_cn6xxx_update_read_index; in lio_setup_cn66xx_octeon_device()
729 oct->fn_list.bar1_idx_setup = lio_cn6xxx_bar1_idx_setup; in lio_setup_cn66xx_octeon_device()
730 oct->fn_list.bar1_idx_write = lio_cn6xxx_bar1_idx_write; in lio_setup_cn66xx_octeon_device()
731 oct->fn_list.bar1_idx_read = lio_cn6xxx_bar1_idx_read; in lio_setup_cn66xx_octeon_device()
733 oct->fn_list.process_interrupt_regs = lio_cn6xxx_process_interrupt_regs; in lio_setup_cn66xx_octeon_device()
734 oct->fn_list.enable_interrupt = lio_cn6xxx_enable_interrupt; in lio_setup_cn66xx_octeon_device()
735 oct->fn_list.disable_interrupt = lio_cn6xxx_disable_interrupt; in lio_setup_cn66xx_octeon_device()
737 oct->fn_list.enable_io_queues = lio_cn6xxx_enable_io_queues; in lio_setup_cn66xx_octeon_device()
738 oct->fn_list.disable_io_queues = lio_cn6xxx_disable_io_queues; in lio_setup_cn66xx_octeon_device()
740 lio_cn6xxx_setup_reg_address(oct, oct->chip, &oct->reg_list); in lio_setup_cn66xx_octeon_device()
743 oct_get_config_info(oct, LIO_210SV); in lio_setup_cn66xx_octeon_device()
745 dev_err(&oct->pci_dev->dev, "%s No Config found for CN66XX\n", in lio_setup_cn66xx_octeon_device()
747 octeon_unmap_pci_barx(oct, 0); in lio_setup_cn66xx_octeon_device()
748 octeon_unmap_pci_barx(oct, 1); in lio_setup_cn66xx_octeon_device()
752 oct->coproc_clock_rate = 1000000ULL * lio_cn6xxx_coprocessor_clock(oct); in lio_setup_cn66xx_octeon_device()
757 int lio_validate_cn6xxx_config_info(struct octeon_device *oct, in lio_validate_cn6xxx_config_info() argument
763 dev_err(&oct->pci_dev->dev, "%s: Num IQ (%d) exceeds Max (%d)\n", in lio_validate_cn6xxx_config_info()
770 dev_err(&oct->pci_dev->dev, "%s: Num OQ (%d) exceeds Max (%d)\n", in lio_validate_cn6xxx_config_info()
778 dev_err(&oct->pci_dev->dev, "%s: Invalid instr type for IQ\n", in lio_validate_cn6xxx_config_info()
784 dev_err(&oct->pci_dev->dev, "%s: Invalid parameter for OQ\n", in lio_validate_cn6xxx_config_info()
790 dev_err(&oct->pci_dev->dev, "%s: No Time Interrupt for OQ\n", in lio_validate_cn6xxx_config_info()