47 #define MACB_RX_INT_FLAGS	(MACB_BIT(RCOMP) | MACB_BIT(RXUBR)	\
48 				 | MACB_BIT(ISR_ROVR))
49 #define MACB_TX_ERR_FLAGS	(MACB_BIT(ISR_TUND)			\
50 					| MACB_BIT(ISR_RLE)		\
51 					| MACB_BIT(TXERR))
52 #define MACB_TX_INT_FLAGS	(MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
135 	u32 value = MACB_BIT(LLB);  in hw_is_native_io()
143 	return value == MACB_BIT(LLB);  in hw_is_native_io()
316 			reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));  in macb_handle_link_change()
321 				reg |= MACB_BIT(FD);  in macb_handle_link_change()
323 				reg |= MACB_BIT(SPD);  in macb_handle_link_change()
425 	macb_writel(bp, NCR, MACB_BIT(MPE));  in macb_mii_init()
517 	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));  in macb_halt_tx()
523 		if (!(status & MACB_BIT(TGO)))  in macb_halt_tx()
597 		if (ctrl & MACB_BIT(TX_USED)) {  in macb_tx_error_task()
609 			if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {  in macb_tx_error_task()
621 			if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))  in macb_tx_error_task()
625 			desc->ctrl = ctrl | MACB_BIT(TX_USED);  in macb_tx_error_task()
634 	desc->ctrl = MACB_BIT(TX_USED);  in macb_tx_error_task()
651 	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));  in macb_tx_error_task()
668 		queue_writel(queue, ISR, MACB_BIT(TCOMP));  in macb_tx_interrupt()
690 		if (!(ctrl & MACB_BIT(TX_USED)))  in macb_tx_interrupt()
759 				paddr |= MACB_BIT(RX_WRAP);  in gem_rx_refill()
766 			bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);  in gem_rx_refill()
786 		desc->addr &= ~MACB_BIT(RX_USED);  in discard_partial_frame()
819 		if (!(addr & MACB_BIT(RX_USED)))  in gem_rx()
825 		if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {  in gem_rx()
906 			desc->addr &= ~MACB_BIT(RX_USED);  in macb_rx_frame()
933 		desc->addr &= ~MACB_BIT(RX_USED);  in macb_rx_frame()
970 		if (!(addr & MACB_BIT(RX_USED)))  in macb_rx()
973 		if (ctrl & MACB_BIT(RX_SOF)) {  in macb_rx()
979 		if (ctrl & MACB_BIT(RX_EOF)) {  in macb_rx()
1022 				macb_writel(bp, ISR, MACB_BIT(RCOMP));  in macb_poll()
1069 				queue_writel(queue, ISR, MACB_BIT(RCOMP));  in macb_interrupt()
1087 		if (status & MACB_BIT(TCOMP))  in macb_interrupt()
1101 		if (status & MACB_BIT(RXUBR)) {  in macb_interrupt()
1103 			macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));  in macb_interrupt()
1104 			macb_writel(bp, NCR, ctrl | MACB_BIT(RE));  in macb_interrupt()
1107 				macb_writel(bp, ISR, MACB_BIT(RXUBR));  in macb_interrupt()
1110 		if (status & MACB_BIT(ISR_ROVR)) {  in macb_interrupt()
1118 				queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));  in macb_interrupt()
1121 		if (status & MACB_BIT(HRESP)) {  in macb_interrupt()
1130 				queue_writel(queue, ISR, MACB_BIT(HRESP));  in macb_interrupt()
1246 	ctrl = MACB_BIT(TX_USED);  in macb_tx_map()
1258 			ctrl |= MACB_BIT(TX_LAST);  in macb_tx_map()
1262 			ctrl |= MACB_BIT(TX_WRAP);  in macb_tx_map()
1339 	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));  in macb_start_xmit()
1514 			queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);  in gem_init_rings()
1516 		queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);  in gem_init_rings()
1538 	bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);  in macb_init_rings()
1542 		bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);  in macb_init_rings()
1546 	bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);  in macb_init_rings()
1563 	macb_writel(bp, NCR, MACB_BIT(CLRSTAT));  in macb_reset_hw()
1688 	config |= MACB_BIT(PAE);		/* PAuse Enable */  in macb_init_hw()
1689 	config |= MACB_BIT(DRFCS);		/* Discard Rx FCS */  in macb_init_hw()
1691 		config |= MACB_BIT(JFRAME);	/* Enable jumbo frames */  in macb_init_hw()
1693 		config |= MACB_BIT(BIG);	/* Receive oversized frames */  in macb_init_hw()
1695 		config |= MACB_BIT(CAF);	/* Copy All Frames */  in macb_init_hw()
1699 		config |= MACB_BIT(NBC);	/* No BroadCast */  in macb_init_hw()
1721 			     MACB_BIT(HRESP));  in macb_init_hw()
1725 	macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));  in macb_init_hw()
1820 		cfg |= MACB_BIT(CAF);  in macb_set_rx_mode()
1827 		cfg &= ~MACB_BIT(CAF);  in macb_set_rx_mode()
1838 		cfg |= MACB_BIT(NCFGR_MTI);  in macb_set_rx_mode()
1842 		cfg |= MACB_BIT(NCFGR_MTI);  in macb_set_rx_mode()
1847 		cfg &= ~MACB_BIT(NCFGR_MTI);  in macb_set_rx_mode()
2409 		val = MACB_BIT(RMII);  in macb_init()
2411 		val = MACB_BIT(MII);  in macb_init()
2414 		val |= MACB_BIT(CLKEN);  in macb_init()
2470 	lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);  in at91ether_start()
2480 	macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));  in at91ether_start()
2494 	macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));  in at91ether_open()
2503 	macb_writel(lp, IER, MACB_BIT(RCOMP)	|  in at91ether_open()
2504 			     MACB_BIT(RXUBR)	|  in at91ether_open()
2505 			     MACB_BIT(ISR_TUND)	|  in at91ether_open()
2506 			     MACB_BIT(ISR_RLE)	|  in at91ether_open()
2507 			     MACB_BIT(TCOMP)	|  in at91ether_open()
2508 			     MACB_BIT(ISR_ROVR)	|  in at91ether_open()
2509 			     MACB_BIT(HRESP));  in at91ether_open()
2527 	macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));  in at91ether_close()
2530 	macb_writel(lp, IDR, MACB_BIT(RCOMP)	|  in at91ether_close()
2531 			     MACB_BIT(RXUBR)	|  in at91ether_close()
2532 			     MACB_BIT(ISR_TUND)	|  in at91ether_close()
2533 			     MACB_BIT(ISR_RLE)	|  in at91ether_close()
2534 			     MACB_BIT(TCOMP)	|  in at91ether_close()
2535 			     MACB_BIT(ISR_ROVR) |  in at91ether_close()
2536 			     MACB_BIT(HRESP));  in at91ether_close()
2559 	if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {  in at91ether_start_xmit()
2591 	while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {  in at91ether_rx()
2607 		if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))  in at91ether_rx()
2611 		lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);  in at91ether_rx()
2634 	if (intstatus & MACB_BIT(RCOMP))  in at91ether_interrupt()
2638 	if (intstatus & MACB_BIT(TCOMP)) {  in at91ether_interrupt()
2640 		if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))  in at91ether_interrupt()
2655 	if (intstatus & MACB_BIT(RXUBR)) {  in at91ether_interrupt()
2657 		macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));  in at91ether_interrupt()
2658 		macb_writel(lp, NCR, ctl | MACB_BIT(RE));  in at91ether_interrupt()
2661 	if (intstatus & MACB_BIT(ISR_ROVR))  in at91ether_interrupt()
2731 	reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);  in at91ether_init()
2733 		reg |= MACB_BIT(RM9200_RMII);  in at91ether_init()