Lines Matching refs:tp
88 #define tg3_flag(tp, flag) \ argument
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \ argument
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \ argument
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
128 #define TG3_MAX_MTU(tp) \ argument
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
135 #define TG3_RX_STD_RING_SIZE(tp) \ argument
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
139 #define TG3_RX_JMB_RING_SIZE(tp) \ argument
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
154 #define TG3_RX_STD_RING_BYTES(tp) \ argument
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \ argument
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \ argument
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ argument
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ argument
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD argument
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) argument
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset) argument
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD) argument
211 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3) argument
212 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1) argument
471 static void tg3_write32(struct tg3 *tp, u32 off, u32 val) in tg3_write32() argument
473 writel(val, tp->regs + off); in tg3_write32()
476 static u32 tg3_read32(struct tg3 *tp, u32 off) in tg3_read32() argument
478 return readl(tp->regs + off); in tg3_read32()
481 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) in tg3_ape_write32() argument
483 writel(val, tp->aperegs + off); in tg3_ape_write32()
486 static u32 tg3_ape_read32(struct tg3 *tp, u32 off) in tg3_ape_read32() argument
488 return readl(tp->aperegs + off); in tg3_ape_read32()
491 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) in tg3_write_indirect_reg32() argument
495 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
498 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
501 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) in tg3_write_flush_reg32() argument
503 writel(val, tp->regs + off); in tg3_write_flush_reg32()
504 readl(tp->regs + off); in tg3_write_flush_reg32()
507 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) in tg3_read_indirect_reg32() argument
512 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
515 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
519 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) in tg3_write_indirect_mbox() argument
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
534 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
537 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
549 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) in tg3_read_indirect_mbox() argument
554 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
557 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
566 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) in _tw32_flush() argument
568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) in _tw32_flush()
570 tp->write32(tp, off, val); in _tw32_flush()
573 tg3_write32(tp, off, val); in _tw32_flush()
576 tp->read32(tp, off); in _tw32_flush()
585 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) in tw32_mailbox_flush() argument
587 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) || in tw32_mailbox_flush()
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) && in tw32_mailbox_flush()
590 !tg3_flag(tp, ICH_WORKAROUND))) in tw32_mailbox_flush()
591 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
594 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) in tg3_write32_tx_mbox() argument
596 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
598 if (tg3_flag(tp, TXD_MBOX_HWBUG)) in tg3_write32_tx_mbox()
600 if (tg3_flag(tp, MBOX_WRITE_REORDER) || in tg3_write32_tx_mbox()
601 tg3_flag(tp, FLUSH_POSTED_WRITES)) in tg3_write32_tx_mbox()
605 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) in tg3_read32_mbox_5906() argument
607 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
610 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) in tg3_write32_mbox_5906() argument
612 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
615 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
616 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
617 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
621 #define tw32(reg, val) tp->write32(tp, reg, val)
622 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624 #define tr32(reg) tp->read32(tp, reg)
626 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) in tg3_write_mem() argument
630 if (tg3_asic_rev(tp) == ASIC_REV_5906 && in tg3_write_mem()
634 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
635 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_write_mem()
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
648 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
651 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) in tg3_read_mem() argument
655 if (tg3_asic_rev(tp) == ASIC_REV_5906 && in tg3_read_mem()
661 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
662 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_read_mem()
663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
675 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
678 static void tg3_ape_lock_init(struct tg3 *tp) in tg3_ape_lock_init() argument
683 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_lock_init()
698 if (!tp->pci_fn) in tg3_ape_lock_init()
701 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
703 tg3_ape_write32(tp, regbase + 4 * i, bit); in tg3_ape_lock_init()
708 static int tg3_ape_lock(struct tg3 *tp, int locknum) in tg3_ape_lock() argument
714 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_lock()
719 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_lock()
723 if (!tp->pci_fn) in tg3_ape_lock()
726 bit = 1 << tp->pci_fn; in tg3_ape_lock()
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) { in tg3_ape_lock()
748 tg3_ape_write32(tp, req + off, bit); in tg3_ape_lock()
752 status = tg3_ape_read32(tp, gnt + off); in tg3_ape_lock()
755 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
763 tg3_ape_write32(tp, gnt + off, bit); in tg3_ape_lock()
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum) in tg3_ape_unlock() argument
774 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_unlock()
779 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_unlock()
783 if (!tp->pci_fn) in tg3_ape_unlock()
786 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
798 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_unlock()
803 tg3_ape_write32(tp, gnt + 4 * locknum, bit); in tg3_ape_unlock()
806 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us) in tg3_ape_event_lock() argument
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) in tg3_ape_event_lock()
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); in tg3_ape_event_lock()
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_event_lock()
827 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us) in tg3_ape_wait_for_event() argument
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); in tg3_ape_wait_for_event()
843 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, in tg3_ape_scratchpad_read() argument
849 if (!tg3_flag(tp, APE_HAS_NCSI)) in tg3_ape_scratchpad_read()
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_ape_scratchpad_read()
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_scratchpad_read()
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) + in tg3_ape_scratchpad_read()
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN); in tg3_ape_scratchpad_read()
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_scratchpad_read()
877 err = tg3_ape_event_lock(tp, 1000); in tg3_ape_scratchpad_read()
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata); in tg3_ape_scratchpad_read()
886 tg3_ape_write32(tp, bufoff, base_off); in tg3_ape_scratchpad_read()
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length); in tg3_ape_scratchpad_read()
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_scratchpad_read()
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); in tg3_ape_scratchpad_read()
894 if (tg3_ape_wait_for_event(tp, 30000)) in tg3_ape_scratchpad_read()
898 u32 val = tg3_ape_read32(tp, msgoff + i); in tg3_ape_scratchpad_read()
907 static int tg3_ape_send_event(struct tg3 *tp, u32 event) in tg3_ape_send_event() argument
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_ape_send_event()
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_send_event()
921 err = tg3_ape_event_lock(tp, 1000); in tg3_ape_send_event()
925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, in tg3_ape_send_event()
928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_send_event()
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); in tg3_ape_send_event()
934 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) in tg3_ape_driver_state_change() argument
939 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_driver_state_change()
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, in tg3_ape_driver_state_change()
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, in tg3_ape_driver_state_change()
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); in tg3_ape_driver_state_change()
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); in tg3_ape_driver_state_change()
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, in tg3_ape_driver_state_change()
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, in tg3_ape_driver_state_change()
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, in tg3_ape_driver_state_change()
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); in tg3_ape_driver_state_change()
967 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
968 tg3_flag(tp, WOL_ENABLE)) { in tg3_ape_driver_state_change()
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, in tg3_ape_driver_state_change()
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); in tg3_ape_driver_state_change()
985 tg3_ape_send_event(tp, event); in tg3_ape_driver_state_change()
988 static void tg3_disable_ints(struct tg3 *tp) in tg3_disable_ints() argument
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
994 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
998 static void tg3_enable_ints(struct tg3 *tp) in tg3_enable_ints() argument
1002 tp->irq_sync = 0; in tg3_enable_ints()
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1009 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1010 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1013 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_enable_ints()
1016 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1020 if (!tg3_flag(tp, TAGGED_STATUS) && in tg3_enable_ints()
1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1024 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1031 struct tg3 *tp = tnapi->tp; in tg3_has_work() local
1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_has_work()
1060 struct tg3 *tp = tnapi->tp; in tg3_int_reenable() local
1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) in tg3_int_reenable()
1070 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1074 static void tg3_switch_clocks(struct tg3 *tp) in tg3_switch_clocks() argument
1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) in tg3_switch_clocks()
1088 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1090 if (tg3_flag(tp, 5705_PLUS)) { in tg3_switch_clocks()
1109 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, in __tg3_readphy() argument
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1122 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1154 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1158 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1163 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) in tg3_readphy() argument
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1168 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, in __tg3_writephy() argument
1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1185 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1213 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1217 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1222 static int tg3_writephy(struct tg3 *tp, int reg, u32 val) in tg3_writephy() argument
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1227 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) in tg3_phy_cl45_write() argument
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_write()
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_write()
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_write()
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_write()
1250 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) in tg3_phy_cl45_read() argument
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_read()
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_read()
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_read()
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_read()
1273 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) in tg3_phydsp_read() argument
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_read()
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_read()
1284 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) in tg3_phydsp_write() argument
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_write()
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write()
1295 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) in tg3_phy_auxctl_read() argument
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, in tg3_phy_auxctl_read()
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); in tg3_phy_auxctl_read()
1308 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) in tg3_phy_auxctl_write() argument
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); in tg3_phy_auxctl_write()
1316 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable) in tg3_phy_toggle_auxctl_smdsp() argument
1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); in tg3_phy_toggle_auxctl_smdsp()
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_toggle_auxctl_smdsp()
1337 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val) in tg3_phy_shdw_write() argument
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW, in tg3_phy_shdw_write()
1343 static int tg3_bmcr_reset(struct tg3 *tp) in tg3_bmcr_reset() argument
1352 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control); in tg3_bmcr_reset()
1376 struct tg3 *tp = bp->priv; in tg3_mdio_read() local
1379 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1381 if (__tg3_readphy(tp, mii_id, reg, &val)) in tg3_mdio_read()
1384 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1391 struct tg3 *tp = bp->priv; in tg3_mdio_write() local
1394 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1396 if (__tg3_writephy(tp, mii_id, reg, val)) in tg3_mdio_write()
1399 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1404 static void tg3_mdio_config_5785(struct tg3 *tp) in tg3_mdio_config_5785() argument
1409 phydev = tp->mdio_bus->phy_map[tp->phy_addr]; in tg3_mdio_config_5785()
1440 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) in tg3_mdio_config_5785()
1453 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1454 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1456 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1471 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1472 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1477 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1485 static void tg3_mdio_start(struct tg3 *tp) in tg3_mdio_start() argument
1487 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1488 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1491 if (tg3_flag(tp, MDIOBUS_INITED) && in tg3_mdio_start()
1492 tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_mdio_start()
1493 tg3_mdio_config_5785(tp); in tg3_mdio_start()
1496 static int tg3_mdio_init(struct tg3 *tp) in tg3_mdio_init() argument
1502 if (tg3_flag(tp, 5717_PLUS)) { in tg3_mdio_init()
1505 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1507 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) in tg3_mdio_init()
1513 tp->phy_addr += 7; in tg3_mdio_init()
1514 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) { in tg3_mdio_init()
1517 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1520 tp->phy_addr = addr; in tg3_mdio_init()
1522 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1524 tg3_mdio_start(tp); in tg3_mdio_init()
1526 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) in tg3_mdio_init()
1529 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1530 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1533 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1534 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", in tg3_mdio_init()
1535 (tp->pdev->bus->number << 8) | tp->pdev->devfn); in tg3_mdio_init()
1536 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1537 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1538 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1539 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1540 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1541 tp->mdio_bus->irq = &tp->mdio_irq[0]; in tg3_mdio_init()
1544 tp->mdio_bus->irq[i] = PHY_POLL; in tg3_mdio_init()
1551 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) in tg3_mdio_init()
1552 tg3_bmcr_reset(tp); in tg3_mdio_init()
1554 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1556 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1557 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1561 phydev = tp->mdio_bus->phy_map[tp->phy_addr]; in tg3_mdio_init()
1564 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1565 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1566 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1581 if (tg3_flag(tp, RGMII_INBAND_DISABLE)) in tg3_mdio_init()
1583 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_init()
1585 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_init()
1595 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1599 tg3_flag_set(tp, MDIOBUS_INITED); in tg3_mdio_init()
1601 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_mdio_init()
1602 tg3_mdio_config_5785(tp); in tg3_mdio_init()
1607 static void tg3_mdio_fini(struct tg3 *tp) in tg3_mdio_fini() argument
1609 if (tg3_flag(tp, MDIOBUS_INITED)) { in tg3_mdio_fini()
1610 tg3_flag_clear(tp, MDIOBUS_INITED); in tg3_mdio_fini()
1611 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1612 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1617 static inline void tg3_generate_fw_event(struct tg3 *tp) in tg3_generate_fw_event() argument
1625 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1631 static void tg3_wait_for_event_ack(struct tg3 *tp) in tg3_wait_for_event_ack() argument
1638 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1653 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1661 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data) in tg3_phy_gather_ump_data() argument
1666 if (!tg3_readphy(tp, MII_BMCR, ®)) in tg3_phy_gather_ump_data()
1668 if (!tg3_readphy(tp, MII_BMSR, ®)) in tg3_phy_gather_ump_data()
1673 if (!tg3_readphy(tp, MII_ADVERTISE, ®)) in tg3_phy_gather_ump_data()
1675 if (!tg3_readphy(tp, MII_LPA, ®)) in tg3_phy_gather_ump_data()
1680 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1681 if (!tg3_readphy(tp, MII_CTRL1000, ®)) in tg3_phy_gather_ump_data()
1683 if (!tg3_readphy(tp, MII_STAT1000, ®)) in tg3_phy_gather_ump_data()
1688 if (!tg3_readphy(tp, MII_PHYADDR, ®)) in tg3_phy_gather_ump_data()
1696 static void tg3_ump_link_report(struct tg3 *tp) in tg3_ump_link_report() argument
1700 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) in tg3_ump_link_report()
1703 tg3_phy_gather_ump_data(tp, data); in tg3_ump_link_report()
1705 tg3_wait_for_event_ack(tp); in tg3_ump_link_report()
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); in tg3_ump_link_report()
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); in tg3_ump_link_report()
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]); in tg3_ump_link_report()
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]); in tg3_ump_link_report()
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]); in tg3_ump_link_report()
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]); in tg3_ump_link_report()
1714 tg3_generate_fw_event(tp); in tg3_ump_link_report()
1718 static void tg3_stop_fw(struct tg3 *tp) in tg3_stop_fw() argument
1720 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_stop_fw()
1722 tg3_wait_for_event_ack(tp); in tg3_stop_fw()
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); in tg3_stop_fw()
1726 tg3_generate_fw_event(tp); in tg3_stop_fw()
1729 tg3_wait_for_event_ack(tp); in tg3_stop_fw()
1734 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) in tg3_write_sig_pre_reset() argument
1736 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, in tg3_write_sig_pre_reset()
1739 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_pre_reset()
1742 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1747 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1752 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1763 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) in tg3_write_sig_post_reset() argument
1765 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_post_reset()
1768 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_post_reset()
1773 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_post_reset()
1784 static void tg3_write_sig_legacy(struct tg3 *tp, int kind) in tg3_write_sig_legacy() argument
1786 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_write_sig_legacy()
1789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1794 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1799 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1809 static int tg3_poll_fw(struct tg3 *tp) in tg3_poll_fw() argument
1814 if (tg3_flag(tp, NO_FWARE_REPORTED)) in tg3_poll_fw()
1817 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_poll_fw()
1822 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_poll_fw()
1827 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1837 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); in tg3_poll_fw()
1840 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1841 if (!tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1842 tg3_flag_set(tp, NO_FWARE_REPORTED); in tg3_poll_fw()
1843 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1857 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1858 tg3_flag_set(tp, NO_FWARE_REPORTED); in tg3_poll_fw()
1860 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1863 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { in tg3_poll_fw()
1873 static void tg3_link_report(struct tg3 *tp) in tg3_link_report() argument
1875 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1876 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1877 tg3_ump_link_report(tp); in tg3_link_report()
1878 } else if (netif_msg_link(tp)) { in tg3_link_report()
1879 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1880 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1882 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1884 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1887 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1893 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1894 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1895 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1897 tg3_ump_link_report(tp); in tg3_link_report()
1900 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1963 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) in tg3_setup_flow_control() argument
1967 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1968 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1970 if (tg3_flag(tp, USE_PHYLIB)) in tg3_setup_flow_control()
1971 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg; in tg3_setup_flow_control()
1973 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1975 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_setup_flow_control()
1976 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1981 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1983 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
1986 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1988 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1990 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1991 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
1994 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1996 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1998 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
1999 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2006 struct tg3 *tp = netdev_priv(dev); in tg3_adjust_link() local
2007 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr]; in tg3_adjust_link()
2009 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2011 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2014 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2023 tg3_asic_rev(tp) != ASIC_REV_5785) in tg3_adjust_link()
2032 tp->link_config.flowctrl); in tg3_adjust_link()
2040 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); in tg3_adjust_link()
2044 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2045 tp->mac_mode = mac_mode; in tg3_adjust_link()
2046 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2050 if (tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_adjust_link()
2070 if (phydev->link != tp->old_link || in tg3_adjust_link()
2071 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2072 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2073 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2076 tp->old_link = phydev->link; in tg3_adjust_link()
2077 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2078 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2080 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2083 tg3_link_report(tp); in tg3_adjust_link()
2086 static int tg3_phy_init(struct tg3 *tp) in tg3_phy_init() argument
2090 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2094 tg3_bmcr_reset(tp); in tg3_phy_init()
2096 phydev = tp->mdio_bus->phy_map[tp->phy_addr]; in tg3_phy_init()
2099 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), in tg3_phy_init()
2102 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2110 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2123 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]); in tg3_phy_init()
2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2134 static void tg3_phy_start(struct tg3 *tp) in tg3_phy_start() argument
2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2141 phydev = tp->mdio_bus->phy_map[tp->phy_addr]; in tg3_phy_start()
2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2145 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2146 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2147 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2148 phydev->advertising = tp->link_config.advertising; in tg3_phy_start()
2156 static void tg3_phy_stop(struct tg3 *tp) in tg3_phy_stop() argument
2158 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2161 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]); in tg3_phy_stop()
2164 static void tg3_phy_fini(struct tg3 *tp) in tg3_phy_fini() argument
2166 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2167 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]); in tg3_phy_fini()
2168 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2172 static int tg3_phy_set_extloopbk(struct tg3 *tp) in tg3_phy_set_extloopbk() argument
2177 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2180 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2182 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2189 err = tg3_phy_auxctl_read(tp, in tg3_phy_set_extloopbk()
2195 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2202 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) in tg3_phy_fet_toggle_apd() argument
2206 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_phy_fet_toggle_apd()
2209 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_fet_toggle_apd()
2211 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { in tg3_phy_fet_toggle_apd()
2216 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); in tg3_phy_fet_toggle_apd()
2218 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_phy_fet_toggle_apd()
2222 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) in tg3_phy_toggle_apd() argument
2226 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_apd()
2227 (tg3_flag(tp, 5717_PLUS) && in tg3_phy_toggle_apd()
2228 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2231 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2232 tg3_phy_fet_toggle_apd(tp, enable); in tg3_phy_toggle_apd()
2240 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable) in tg3_phy_toggle_apd()
2243 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg); in tg3_phy_toggle_apd()
2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg); in tg3_phy_toggle_apd()
2253 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable) in tg3_phy_toggle_automdix() argument
2257 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_automdix()
2258 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2261 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2264 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { in tg3_phy_toggle_automdix()
2267 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_toggle_automdix()
2269 if (!tg3_readphy(tp, reg, &phy)) { in tg3_phy_toggle_automdix()
2274 tg3_writephy(tp, reg, phy); in tg3_phy_toggle_automdix()
2276 tg3_writephy(tp, MII_TG3_FET_TEST, ephy); in tg3_phy_toggle_automdix()
2281 ret = tg3_phy_auxctl_read(tp, in tg3_phy_toggle_automdix()
2288 tg3_phy_auxctl_write(tp, in tg3_phy_toggle_automdix()
2294 static void tg3_phy_set_wirespeed(struct tg3 *tp) in tg3_phy_set_wirespeed() argument
2299 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2302 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
2304 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
2308 static void tg3_phy_apply_otp(struct tg3 *tp) in tg3_phy_apply_otp() argument
2312 if (!tp->phy_otp) in tg3_phy_apply_otp()
2315 otp = tp->phy_otp; in tg3_phy_apply_otp()
2317 if (tg3_phy_toggle_auxctl_smdsp(tp, true)) in tg3_phy_apply_otp()
2322 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); in tg3_phy_apply_otp()
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); in tg3_phy_apply_otp()
2330 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); in tg3_phy_apply_otp()
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); in tg3_phy_apply_otp()
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); in tg3_phy_apply_otp()
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); in tg3_phy_apply_otp()
2342 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_apply_otp()
2345 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee) in tg3_eee_pull_config() argument
2348 struct ethtool_eee *dest = &tp->eee; in tg3_eee_pull_config()
2350 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val)) in tg3_eee_pull_config()
2367 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val)) in tg3_eee_pull_config()
2372 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val)) in tg3_eee_pull_config()
2385 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up) in tg3_phy_eee_adjust() argument
2389 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2392 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2394 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2396 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2397 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2398 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2401 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2408 tg3_eee_pull_config(tp, NULL); in tg3_phy_eee_adjust()
2409 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2410 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2413 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2415 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_eee_adjust()
2416 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); in tg3_phy_eee_adjust()
2417 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_eee_adjust()
2425 static void tg3_phy_eee_enable(struct tg3 *tp) in tg3_phy_eee_enable() argument
2429 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2430 (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_phy_eee_enable()
2431 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_phy_eee_enable()
2432 tg3_flag(tp, 57765_CLASS)) && in tg3_phy_eee_enable()
2433 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_eee_enable()
2436 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); in tg3_phy_eee_enable()
2437 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_eee_enable()
2444 static int tg3_wait_macro_done(struct tg3 *tp) in tg3_wait_macro_done() argument
2451 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { in tg3_wait_macro_done()
2462 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) in tg3_phy_write_and_check_testpat() argument
2475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2477 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2484 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2489 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2491 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2492 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2498 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2506 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || in tg3_phy_write_and_check_testpat()
2507 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || in tg3_phy_write_and_check_testpat()
2508 tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2516 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); in tg3_phy_write_and_check_testpat()
2517 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
2528 static int tg3_phy_reset_chanpat(struct tg3 *tp) in tg3_phy_reset_chanpat() argument
2535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_reset_chanpat()
2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2539 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2541 if (tg3_wait_macro_done(tp)) in tg3_phy_reset_chanpat()
2548 static int tg3_phy_reset_5703_4_5(struct tg3 *tp) in tg3_phy_reset_5703_4_5() argument
2557 err = tg3_bmcr_reset(tp); in tg3_phy_reset_5703_4_5()
2564 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) in tg3_phy_reset_5703_4_5()
2568 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2571 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
2575 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) in tg3_phy_reset_5703_4_5()
2578 tg3_writephy(tp, MII_CTRL1000, in tg3_phy_reset_5703_4_5()
2581 err = tg3_phy_toggle_auxctl_smdsp(tp, true); in tg3_phy_reset_5703_4_5()
2586 tg3_phydsp_write(tp, 0x8005, 0x0800); in tg3_phy_reset_5703_4_5()
2588 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); in tg3_phy_reset_5703_4_5()
2593 err = tg3_phy_reset_chanpat(tp); in tg3_phy_reset_5703_4_5()
2597 tg3_phydsp_write(tp, 0x8005, 0x0000); in tg3_phy_reset_5703_4_5()
2599 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); in tg3_phy_reset_5703_4_5()
2600 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
2602 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset_5703_4_5()
2604 tg3_writephy(tp, MII_CTRL1000, phy9_orig); in tg3_phy_reset_5703_4_5()
2606 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32); in tg3_phy_reset_5703_4_5()
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2616 static void tg3_carrier_off(struct tg3 *tp) in tg3_carrier_off() argument
2618 netif_carrier_off(tp->dev); in tg3_carrier_off()
2619 tp->link_up = false; in tg3_carrier_off()
2622 static void tg3_warn_mgmt_link_flap(struct tg3 *tp) in tg3_warn_mgmt_link_flap() argument
2624 if (tg3_flag(tp, ENABLE_ASF)) in tg3_warn_mgmt_link_flap()
2625 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2632 static int tg3_phy_reset(struct tg3 *tp) in tg3_phy_reset() argument
2637 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_phy_reset()
2642 err = tg3_readphy(tp, MII_BMSR, &val); in tg3_phy_reset()
2643 err |= tg3_readphy(tp, MII_BMSR, &val); in tg3_phy_reset()
2647 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2648 netif_carrier_off(tp->dev); in tg3_phy_reset()
2649 tg3_link_report(tp); in tg3_phy_reset()
2652 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_phy_reset()
2653 tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_phy_reset()
2654 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_phy_reset()
2655 err = tg3_phy_reset_5703_4_5(tp); in tg3_phy_reset()
2662 if (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_phy_reset()
2663 tg3_chip_rev(tp) != CHIPREV_5784_AX) { in tg3_phy_reset()
2670 err = tg3_bmcr_reset(tp); in tg3_phy_reset()
2676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); in tg3_phy_reset()
2681 if (tg3_chip_rev(tp) == CHIPREV_5784_AX || in tg3_phy_reset()
2682 tg3_chip_rev(tp) == CHIPREV_5761_AX) { in tg3_phy_reset()
2692 if (tg3_flag(tp, 5717_PLUS) && in tg3_phy_reset()
2693 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2696 tg3_phy_apply_otp(tp); in tg3_phy_reset()
2698 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2699 tg3_phy_toggle_apd(tp, true); in tg3_phy_reset()
2701 tg3_phy_toggle_apd(tp, false); in tg3_phy_reset()
2704 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2705 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2706 tg3_phydsp_write(tp, 0x201f, 0x2aaa); in tg3_phy_reset()
2707 tg3_phydsp_write(tp, 0x000a, 0x0323); in tg3_phy_reset()
2708 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2711 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2712 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2716 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2717 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2718 tg3_phydsp_write(tp, 0x000a, 0x310b); in tg3_phy_reset()
2719 tg3_phydsp_write(tp, 0x201f, 0x9506); in tg3_phy_reset()
2720 tg3_phydsp_write(tp, 0x401f, 0x14e2); in tg3_phy_reset()
2721 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2723 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2724 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); in tg3_phy_reset()
2726 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset()
2728 tg3_writephy(tp, MII_TG3_TEST1, in tg3_phy_reset()
2731 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); in tg3_phy_reset()
2733 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2739 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2741 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_phy_reset()
2742 } else if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2744 err = tg3_phy_auxctl_read(tp, in tg3_phy_reset()
2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_reset()
2754 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2755 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) in tg3_phy_reset()
2756 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_reset()
2760 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_phy_reset()
2762 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); in tg3_phy_reset()
2765 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0) in tg3_phy_reset()
2766 tg3_phydsp_write(tp, 0xffb, 0x4000); in tg3_phy_reset()
2768 tg3_phy_toggle_automdix(tp, true); in tg3_phy_reset()
2769 tg3_phy_set_wirespeed(tp); in tg3_phy_reset()
2789 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) in tg3_set_function_status() argument
2793 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_function_status()
2794 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_set_function_status()
2795 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); in tg3_set_function_status()
2799 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2803 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_function_status()
2804 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_set_function_status()
2805 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); in tg3_set_function_status()
2812 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) in tg3_pwrsrc_switch_to_vmain() argument
2814 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vmain()
2817 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_pwrsrc_switch_to_vmain()
2818 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_pwrsrc_switch_to_vmain()
2819 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_pwrsrc_switch_to_vmain()
2820 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_pwrsrc_switch_to_vmain()
2823 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); in tg3_pwrsrc_switch_to_vmain()
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2828 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); in tg3_pwrsrc_switch_to_vmain()
2830 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2837 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) in tg3_pwrsrc_die_with_vmain() argument
2841 if (!tg3_flag(tp, IS_NIC) || in tg3_pwrsrc_die_with_vmain()
2842 tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_pwrsrc_die_with_vmain()
2843 tg3_asic_rev(tp) == ASIC_REV_5701) in tg3_pwrsrc_die_with_vmain()
2846 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2861 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) in tg3_pwrsrc_switch_to_vaux() argument
2863 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vaux()
2866 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_pwrsrc_switch_to_vaux()
2867 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_pwrsrc_switch_to_vaux()
2868 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2875 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2876 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2883 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2899 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_pwrsrc_switch_to_vaux()
2901 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2907 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2920 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2926 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2932 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2938 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) in tg3_frob_aux_power_5717() argument
2943 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_frob_aux_power_5717()
2946 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) in tg3_frob_aux_power_5717()
2949 msg = tg3_set_function_status(tp, msg); in tg3_frob_aux_power_5717()
2955 tg3_pwrsrc_switch_to_vaux(tp); in tg3_frob_aux_power_5717()
2957 tg3_pwrsrc_die_with_vmain(tp); in tg3_frob_aux_power_5717()
2960 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); in tg3_frob_aux_power_5717()
2963 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) in tg3_frob_aux_power() argument
2968 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) in tg3_frob_aux_power()
2971 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_frob_aux_power()
2972 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_frob_aux_power()
2973 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_frob_aux_power()
2974 tg3_frob_aux_power_5717(tp, include_wol ? in tg3_frob_aux_power()
2975 tg3_flag(tp, WOL_ENABLE) != 0 : 0); in tg3_frob_aux_power()
2979 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2982 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
2997 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || in tg3_frob_aux_power()
2998 tg3_flag(tp, ENABLE_ASF)) in tg3_frob_aux_power()
3002 tg3_pwrsrc_switch_to_vaux(tp); in tg3_frob_aux_power()
3004 tg3_pwrsrc_die_with_vmain(tp); in tg3_frob_aux_power()
3007 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) in tg3_5700_link_polarity() argument
3009 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3011 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3020 static bool tg3_phy_power_bug(struct tg3 *tp) in tg3_phy_power_bug() argument
3022 switch (tg3_asic_rev(tp)) { in tg3_phy_power_bug()
3027 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3031 if (!tp->pci_fn) in tg3_phy_power_bug()
3036 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3037 !tp->pci_fn) in tg3_phy_power_bug()
3045 static bool tg3_phy_led_bug(struct tg3 *tp) in tg3_phy_led_bug() argument
3047 switch (tg3_asic_rev(tp)) { in tg3_phy_led_bug()
3050 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3051 !tp->pci_fn) in tg3_phy_led_bug()
3059 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) in tg3_power_down_phy() argument
3063 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3066 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3067 if (tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_power_down_phy()
3079 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_phy()
3080 tg3_bmcr_reset(tp); in tg3_power_down_phy()
3085 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3087 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_power_down_phy()
3090 tg3_writephy(tp, MII_ADVERTISE, 0); in tg3_power_down_phy()
3091 tg3_writephy(tp, MII_BMCR, in tg3_power_down_phy()
3094 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_power_down_phy()
3096 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { in tg3_power_down_phy()
3098 tg3_writephy(tp, in tg3_power_down_phy()
3102 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_power_down_phy()
3106 if (!tg3_phy_led_bug(tp)) in tg3_power_down_phy()
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_power_down_phy()
3113 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); in tg3_power_down_phy()
3119 if (tg3_phy_power_bug(tp)) in tg3_power_down_phy()
3122 if (tg3_chip_rev(tp) == CHIPREV_5784_AX || in tg3_power_down_phy()
3123 tg3_chip_rev(tp) == CHIPREV_5761_AX) { in tg3_power_down_phy()
3130 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); in tg3_power_down_phy()
3134 static int tg3_nvram_lock(struct tg3 *tp) in tg3_nvram_lock() argument
3136 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_lock()
3139 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3151 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3157 static void tg3_nvram_unlock(struct tg3 *tp) in tg3_nvram_unlock() argument
3159 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_unlock()
3160 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3161 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3162 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3168 static void tg3_enable_nvram_access(struct tg3 *tp) in tg3_enable_nvram_access() argument
3170 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_enable_nvram_access()
3178 static void tg3_disable_nvram_access(struct tg3 *tp) in tg3_disable_nvram_access() argument
3180 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_disable_nvram_access()
3187 static int tg3_nvram_read_using_eeprom(struct tg3 *tp, in tg3_nvram_read_using_eeprom() argument
3229 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) in tg3_nvram_exec_cmd() argument
3248 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) in tg3_nvram_phys_addr() argument
3250 if (tg3_flag(tp, NVRAM) && in tg3_nvram_phys_addr()
3251 tg3_flag(tp, NVRAM_BUFFERED) && in tg3_nvram_phys_addr()
3252 tg3_flag(tp, FLASH) && in tg3_nvram_phys_addr()
3253 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && in tg3_nvram_phys_addr()
3254 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3256 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3258 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3263 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) in tg3_nvram_logical_addr() argument
3265 if (tg3_flag(tp, NVRAM) && in tg3_nvram_logical_addr()
3266 tg3_flag(tp, NVRAM_BUFFERED) && in tg3_nvram_logical_addr()
3267 tg3_flag(tp, FLASH) && in tg3_nvram_logical_addr()
3268 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && in tg3_nvram_logical_addr()
3269 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3272 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3284 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) in tg3_nvram_read() argument
3288 if (!tg3_flag(tp, NVRAM)) in tg3_nvram_read()
3289 return tg3_nvram_read_using_eeprom(tp, offset, val); in tg3_nvram_read()
3291 offset = tg3_nvram_phys_addr(tp, offset); in tg3_nvram_read()
3296 ret = tg3_nvram_lock(tp); in tg3_nvram_read()
3300 tg3_enable_nvram_access(tp); in tg3_nvram_read()
3303 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | in tg3_nvram_read()
3309 tg3_disable_nvram_access(tp); in tg3_nvram_read()
3311 tg3_nvram_unlock(tp); in tg3_nvram_read()
3317 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) in tg3_nvram_read_be32() argument
3320 int res = tg3_nvram_read(tp, offset, &v); in tg3_nvram_read_be32()
3326 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, in tg3_nvram_write_block_using_eeprom() argument
3376 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, in tg3_nvram_write_block_unbuffered() argument
3380 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3396 ret = tg3_nvram_read_be32(tp, phy_addr + j, in tg3_nvram_write_block_unbuffered()
3415 tg3_enable_nvram_access(tp); in tg3_nvram_write_block_unbuffered()
3423 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3432 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3458 ret = tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_unbuffered()
3467 tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_unbuffered()
3475 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, in tg3_nvram_write_block_buffered() argument
3487 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3489 phy_addr = tg3_nvram_phys_addr(tp, offset); in tg3_nvram_write_block_buffered()
3495 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3502 !tg3_flag(tp, FLASH) || in tg3_nvram_write_block_buffered()
3503 !tg3_flag(tp, 57765_PLUS)) in tg3_nvram_write_block_buffered()
3506 if (tg3_asic_rev(tp) != ASIC_REV_5752 && in tg3_nvram_write_block_buffered()
3507 !tg3_flag(tp, 5755_PLUS) && in tg3_nvram_write_block_buffered()
3508 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3513 ret = tg3_nvram_exec_cmd(tp, cmd); in tg3_nvram_write_block_buffered()
3517 if (!tg3_flag(tp, FLASH)) { in tg3_nvram_write_block_buffered()
3522 ret = tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_buffered()
3530 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) in tg3_nvram_write_block() argument
3534 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
3535 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3540 if (!tg3_flag(tp, NVRAM)) { in tg3_nvram_write_block()
3541 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); in tg3_nvram_write_block()
3545 ret = tg3_nvram_lock(tp); in tg3_nvram_write_block()
3549 tg3_enable_nvram_access(tp); in tg3_nvram_write_block()
3550 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) in tg3_nvram_write_block()
3556 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { in tg3_nvram_write_block()
3557 ret = tg3_nvram_write_block_buffered(tp, offset, len, in tg3_nvram_write_block()
3560 ret = tg3_nvram_write_block_unbuffered(tp, offset, len, in tg3_nvram_write_block()
3567 tg3_disable_nvram_access(tp); in tg3_nvram_write_block()
3568 tg3_nvram_unlock(tp); in tg3_nvram_write_block()
3571 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
3572 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3585 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base) in tg3_pause_cpu() argument
3595 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3603 static int tg3_rxcpu_pause(struct tg3 *tp) in tg3_rxcpu_pause() argument
3605 int rc = tg3_pause_cpu(tp, RX_CPU_BASE); in tg3_rxcpu_pause()
3615 static int tg3_txcpu_pause(struct tg3 *tp) in tg3_txcpu_pause() argument
3617 return tg3_pause_cpu(tp, TX_CPU_BASE); in tg3_txcpu_pause()
3621 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base) in tg3_resume_cpu() argument
3628 static void tg3_rxcpu_resume(struct tg3 *tp) in tg3_rxcpu_resume() argument
3630 tg3_resume_cpu(tp, RX_CPU_BASE); in tg3_rxcpu_resume()
3634 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base) in tg3_halt_cpu() argument
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); in tg3_halt_cpu()
3640 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_halt_cpu()
3647 rc = tg3_rxcpu_pause(tp); in tg3_halt_cpu()
3653 if (tg3_flag(tp, IS_SSB_CORE)) in tg3_halt_cpu()
3656 rc = tg3_txcpu_pause(tp); in tg3_halt_cpu()
3660 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3666 if (tg3_flag(tp, NVRAM)) in tg3_halt_cpu()
3671 static int tg3_fw_data_len(struct tg3 *tp, in tg3_fw_data_len() argument
3690 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3693 fw_len = tp->fw->size; in tg3_fw_data_len()
3699 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, in tg3_load_firmware_cpu() argument
3705 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3707 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { in tg3_load_firmware_cpu()
3708 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3714 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766) in tg3_load_firmware_cpu()
3719 if (tg3_asic_rev(tp) != ASIC_REV_57766) { in tg3_load_firmware_cpu()
3723 int lock_err = tg3_nvram_lock(tp); in tg3_load_firmware_cpu()
3724 err = tg3_halt_cpu(tp, cpu_base); in tg3_load_firmware_cpu()
3726 tg3_nvram_unlock(tp); in tg3_load_firmware_cpu()
3731 write_op(tp, cpu_scratch_base + i, 0); in tg3_load_firmware_cpu()
3745 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++) in tg3_load_firmware_cpu()
3746 write_op(tp, cpu_scratch_base + in tg3_load_firmware_cpu()
3765 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc) in tg3_pause_cpu_and_set_pc() argument
3786 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) in tg3_load_5701_a0_firmware_fix() argument
3791 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3799 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3805 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3812 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3815 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3822 tg3_rxcpu_resume(tp); in tg3_load_5701_a0_firmware_fix()
3827 static int tg3_validate_rxcpu_state(struct tg3 *tp) in tg3_validate_rxcpu_state() argument
3844 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3848 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE); in tg3_validate_rxcpu_state()
3850 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3859 static void tg3_load_57766_firmware(struct tg3 *tp) in tg3_load_57766_firmware() argument
3863 if (!tg3_flag(tp, NO_NVRAM)) in tg3_load_57766_firmware()
3866 if (tg3_validate_rxcpu_state(tp)) in tg3_load_57766_firmware()
3869 if (!tp->fw) in tg3_load_57766_firmware()
3886 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3890 if (tg3_rxcpu_pause(tp)) in tg3_load_57766_firmware()
3894 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr); in tg3_load_57766_firmware()
3896 tg3_rxcpu_resume(tp); in tg3_load_57766_firmware()
3900 static int tg3_load_tso_firmware(struct tg3 *tp) in tg3_load_tso_firmware() argument
3906 if (!tg3_flag(tp, FW_TSO)) in tg3_load_tso_firmware()
3909 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3917 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3919 if (tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_load_tso_firmware()
3928 err = tg3_load_firmware_cpu(tp, cpu_base, in tg3_load_tso_firmware()
3935 err = tg3_pause_cpu_and_set_pc(tp, cpu_base, in tg3_load_tso_firmware()
3938 netdev_err(tp->dev, in tg3_load_tso_firmware()
3945 tg3_resume_cpu(tp, cpu_base); in tg3_load_tso_firmware()
3950 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index) in __tg3_set_one_mac_addr() argument
3969 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1) in __tg3_set_mac_addr() argument
3977 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3980 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in __tg3_set_mac_addr()
3981 tg3_asic_rev(tp) == ASIC_REV_5704) { in __tg3_set_mac_addr()
3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3986 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
3987 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
3988 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
3989 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
3990 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
3991 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
3996 static void tg3_enable_register_access(struct tg3 *tp) in tg3_enable_register_access() argument
4002 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
4003 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4006 static int tg3_power_up(struct tg3 *tp) in tg3_power_up() argument
4010 tg3_enable_register_access(tp); in tg3_power_up()
4012 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4015 tg3_pwrsrc_switch_to_vmain(tp); in tg3_power_up()
4017 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4025 static int tg3_power_down_prepare(struct tg3 *tp) in tg3_power_down_prepare() argument
4030 tg3_enable_register_access(tp); in tg3_power_down_prepare()
4033 if (tg3_flag(tp, CLKREQ_BUG)) in tg3_power_down_prepare()
4034 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4041 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4042 tg3_flag(tp, WOL_ENABLE); in tg3_power_down_prepare()
4044 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_power_down_prepare()
4046 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4047 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4051 phydev = tp->mdio_bus->phy_map[tp->phy_addr]; in tg3_power_down_prepare()
4053 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4055 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4056 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4057 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4058 tp->link_config.advertising = phydev->advertising; in tg3_power_down_prepare()
4065 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { in tg3_power_down_prepare()
4066 if (tg3_flag(tp, WOL_SPEED_100MB)) in tg3_power_down_prepare()
4091 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4092 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4094 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4095 tg3_setup_phy(tp, false); in tg3_power_down_prepare()
4098 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_prepare()
4103 } else if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
4108 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); in tg3_power_down_prepare()
4114 if (tg3_flag(tp, WOL_CAP)) in tg3_power_down_prepare()
4115 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | in tg3_power_down_prepare()
4123 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4125 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4126 tg3_phy_auxctl_write(tp, in tg3_power_down_prepare()
4134 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4136 else if (tp->phy_flags & in tg3_power_down_prepare()
4138 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4145 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4146 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_power_down_prepare()
4147 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? in tg3_power_down_prepare()
4149 if (tg3_5700_link_polarity(tp, speed)) in tg3_power_down_prepare()
4158 if (!tg3_flag(tp, 5750_PLUS)) in tg3_power_down_prepare()
4159 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4162 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && in tg3_power_down_prepare()
4163 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) in tg3_power_down_prepare()
4166 if (tg3_flag(tp, ENABLE_APE)) in tg3_power_down_prepare()
4178 if (!tg3_flag(tp, WOL_SPEED_100MB) && in tg3_power_down_prepare()
4179 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4180 tg3_asic_rev(tp) == ASIC_REV_5701)) { in tg3_power_down_prepare()
4183 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4189 } else if (tg3_flag(tp, 5780_CLASS) || in tg3_power_down_prepare()
4190 tg3_flag(tp, CPMU_PRESENT) || in tg3_power_down_prepare()
4191 tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_prepare()
4193 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { in tg3_power_down_prepare()
4196 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4197 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_power_down_prepare()
4202 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
4210 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4213 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4216 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
4219 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4220 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_power_down_prepare()
4229 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4233 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) in tg3_power_down_prepare()
4234 tg3_power_down_phy(tp, do_low_power); in tg3_power_down_prepare()
4236 tg3_frob_aux_power(tp, true); in tg3_power_down_prepare()
4239 if ((!tg3_flag(tp, IS_SSB_CORE)) && in tg3_power_down_prepare()
4240 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) || in tg3_power_down_prepare()
4241 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) { in tg3_power_down_prepare()
4246 if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
4249 err = tg3_nvram_lock(tp); in tg3_power_down_prepare()
4250 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_power_down_prepare()
4252 tg3_nvram_unlock(tp); in tg3_power_down_prepare()
4256 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); in tg3_power_down_prepare()
4258 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN); in tg3_power_down_prepare()
4263 static void tg3_power_down(struct tg3 *tp) in tg3_power_down() argument
4265 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4266 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4269 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) in tg3_aux_stat_to_speed_duplex() argument
4303 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4316 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) in tg3_phy_autoneg_cfg() argument
4325 err = tg3_writephy(tp, MII_ADVERTISE, new_adv); in tg3_phy_autoneg_cfg()
4329 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4332 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_phy_autoneg_cfg()
4333 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) in tg3_phy_autoneg_cfg()
4336 err = tg3_writephy(tp, MII_CTRL1000, new_adv); in tg3_phy_autoneg_cfg()
4341 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4347 err = tg3_phy_toggle_auxctl_smdsp(tp, true); in tg3_phy_autoneg_cfg()
4359 if (!tp->eee.eee_enabled) { in tg3_phy_autoneg_cfg()
4361 tp->eee.advertised = 0; in tg3_phy_autoneg_cfg()
4363 tp->eee.advertised = advertise & in tg3_phy_autoneg_cfg()
4368 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); in tg3_phy_autoneg_cfg()
4372 switch (tg3_asic_rev(tp)) { in tg3_phy_autoneg_cfg()
4382 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); in tg3_phy_autoneg_cfg()
4386 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) in tg3_phy_autoneg_cfg()
4387 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | in tg3_phy_autoneg_cfg()
4391 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_autoneg_cfg()
4400 static void tg3_phy_copper_begin(struct tg3 *tp) in tg3_phy_copper_begin() argument
4402 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4403 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4406 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4407 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4410 if (tg3_flag(tp, WOL_SPEED_100MB)) in tg3_phy_copper_begin()
4413 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4414 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4422 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4423 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4427 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4430 tg3_phy_autoneg_cfg(tp, adv, fc); in tg3_phy_copper_begin()
4432 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4433 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4441 tg3_writephy(tp, MII_BMCR, in tg3_phy_copper_begin()
4447 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4448 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4450 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_phy_copper_begin()
4455 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL); in tg3_phy_copper_begin()
4459 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4473 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4476 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && in tg3_phy_copper_begin()
4478 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); in tg3_phy_copper_begin()
4483 if (tg3_readphy(tp, MII_BMSR, &tmp) || in tg3_phy_copper_begin()
4484 tg3_readphy(tp, MII_BMSR, &tmp)) in tg3_phy_copper_begin()
4491 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_copper_begin()
4497 static int tg3_phy_pull_config(struct tg3 *tp) in tg3_phy_pull_config() argument
4502 err = tg3_readphy(tp, MII_BMCR, &val); in tg3_phy_pull_config()
4507 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4508 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4509 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_phy_pull_config()
4515 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4518 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4524 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4528 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4537 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4539 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4541 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4547 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4548 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4549 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_phy_pull_config()
4551 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4554 err = tg3_readphy(tp, MII_ADVERTISE, &val); in tg3_phy_pull_config()
4559 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4561 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4563 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4566 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4569 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4570 err = tg3_readphy(tp, MII_CTRL1000, &val); in tg3_phy_pull_config()
4576 err = tg3_readphy(tp, MII_ADVERTISE, &val); in tg3_phy_pull_config()
4581 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4587 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4594 static int tg3_init_5401phy_dsp(struct tg3 *tp) in tg3_init_5401phy_dsp() argument
4600 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_init_5401phy_dsp()
4602 err |= tg3_phydsp_write(tp, 0x0012, 0x1804); in tg3_init_5401phy_dsp()
4603 err |= tg3_phydsp_write(tp, 0x0013, 0x1204); in tg3_init_5401phy_dsp()
4604 err |= tg3_phydsp_write(tp, 0x8006, 0x0132); in tg3_init_5401phy_dsp()
4605 err |= tg3_phydsp_write(tp, 0x8006, 0x0232); in tg3_init_5401phy_dsp()
4606 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); in tg3_init_5401phy_dsp()
4613 static bool tg3_phy_eee_config_ok(struct tg3 *tp) in tg3_phy_eee_config_ok() argument
4617 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4620 tg3_eee_pull_config(tp, &eee); in tg3_phy_eee_config_ok()
4622 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4623 if (tp->eee.advertised != eee.advertised || in tg3_phy_eee_config_ok()
4624 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4625 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4636 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) in tg3_phy_copper_an_config_ok() argument
4640 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4644 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4645 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4649 if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) in tg3_phy_copper_an_config_ok()
4655 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4660 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) in tg3_phy_copper_an_config_ok()
4664 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_phy_copper_an_config_ok()
4665 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) { in tg3_phy_copper_an_config_ok()
4680 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) in tg3_phy_copper_fetch_rmtadv() argument
4684 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4687 if (tg3_readphy(tp, MII_STAT1000, &val)) in tg3_phy_copper_fetch_rmtadv()
4693 if (tg3_readphy(tp, MII_LPA, rmtadv)) in tg3_phy_copper_fetch_rmtadv()
4697 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4702 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up) in tg3_test_and_report_link_chg() argument
4704 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4706 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4708 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4710 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4713 tg3_link_report(tp); in tg3_test_and_report_link_chg()
4720 static void tg3_clear_mac_status(struct tg3 *tp) in tg3_clear_mac_status() argument
4732 static void tg3_setup_eee(struct tg3 *tp) in tg3_setup_eee() argument
4738 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) in tg3_setup_eee()
4747 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4751 if (tg3_asic_rev(tp) != ASIC_REV_5717) in tg3_setup_eee()
4754 if (tg3_flag(tp, ENABLE_APE)) in tg3_setup_eee()
4757 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4761 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4768 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset) in tg3_setup_copper_phy() argument
4777 tg3_clear_mac_status(tp); in tg3_setup_copper_phy()
4779 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4781 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4785 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); in tg3_setup_copper_phy()
4790 if ((tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_setup_copper_phy()
4791 tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_setup_copper_phy()
4792 tg3_asic_rev(tp) == ASIC_REV_5705) && in tg3_setup_copper_phy()
4793 tp->link_up) { in tg3_setup_copper_phy()
4794 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4795 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4800 tg3_phy_reset(tp); in tg3_setup_copper_phy()
4802 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4803 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4804 if (tg3_readphy(tp, MII_BMSR, &bmsr) || in tg3_setup_copper_phy()
4805 !tg3_flag(tp, INIT_COMPLETE)) in tg3_setup_copper_phy()
4809 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
4813 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4816 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4823 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4826 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4827 err = tg3_phy_reset(tp); in tg3_setup_copper_phy()
4829 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
4834 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_setup_copper_phy()
4835 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) { in tg3_setup_copper_phy()
4837 tg3_writephy(tp, 0x15, 0x0a75); in tg3_setup_copper_phy()
4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4839 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_setup_copper_phy()
4840 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4844 tg3_readphy(tp, MII_TG3_ISTAT, &val); in tg3_setup_copper_phy()
4845 tg3_readphy(tp, MII_TG3_ISTAT, &val); in tg3_setup_copper_phy()
4847 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4848 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); in tg3_setup_copper_phy()
4849 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4850 tg3_writephy(tp, MII_TG3_IMASK, ~0); in tg3_setup_copper_phy()
4852 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_setup_copper_phy()
4853 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_setup_copper_phy()
4854 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4855 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_setup_copper_phy()
4858 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); in tg3_setup_copper_phy()
4864 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4865 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4867 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4868 err = tg3_phy_auxctl_read(tp, in tg3_setup_copper_phy()
4872 tg3_phy_auxctl_write(tp, in tg3_setup_copper_phy()
4881 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4882 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4891 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); in tg3_setup_copper_phy()
4894 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && in tg3_setup_copper_phy()
4899 tg3_aux_stat_to_speed_duplex(tp, aux_stat, in tg3_setup_copper_phy()
4905 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
4906 if (tg3_readphy(tp, MII_BMCR, &bmcr)) in tg3_setup_copper_phy()
4916 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4917 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4919 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4920 bool eee_config_ok = tg3_phy_eee_config_ok(tp); in tg3_setup_copper_phy()
4924 tg3_phy_copper_an_config_ok(tp, &lcl_adv) && in tg3_setup_copper_phy()
4925 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) in tg3_setup_copper_phy()
4933 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4935 tg3_setup_eee(tp); in tg3_setup_copper_phy()
4936 tg3_phy_reset(tp); in tg3_setup_copper_phy()
4940 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4941 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4947 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4950 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4958 if (!tg3_readphy(tp, reg, &val) && (val & bit)) in tg3_setup_copper_phy()
4959 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4961 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); in tg3_setup_copper_phy()
4966 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4967 tg3_phy_copper_begin(tp); in tg3_setup_copper_phy()
4969 if (tg3_flag(tp, ROBOSWITCH)) { in tg3_setup_copper_phy()
4974 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4975 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4978 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4979 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || in tg3_setup_copper_phy()
4980 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
4984 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
4986 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4987 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4991 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
4992 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4999 if (tg3_flag(tp, RGMII_MODE)) { in tg3_setup_copper_phy()
5003 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5005 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5008 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5016 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5017 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5018 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5020 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_setup_copper_phy()
5022 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5023 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5025 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5031 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5032 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) { in tg3_setup_copper_phy()
5033 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5034 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5038 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5041 tg3_phy_eee_adjust(tp, current_link_up); in tg3_setup_copper_phy()
5043 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_setup_copper_phy()
5051 if (tg3_asic_rev(tp) == ASIC_REV_5700 && in tg3_setup_copper_phy()
5053 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5054 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { in tg3_setup_copper_phy()
5060 tg3_write_mem(tp, in tg3_setup_copper_phy()
5066 if (tg3_flag(tp, CLKREQ_BUG)) { in tg3_setup_copper_phy()
5067 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5068 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5069 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5072 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5076 tg3_test_and_report_link_chg(tp, current_link_up); in tg3_setup_copper_phy()
5145 static int tg3_fiber_aneg_smachine(struct tg3 *tp, in tg3_fiber_aneg_smachine() argument
5225 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5226 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5248 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5254 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5255 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5269 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5270 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5355 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5356 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5397 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) in fiber_autoneg() argument
5407 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5411 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5420 status = tg3_fiber_aneg_smachine(tp, &aninfo); in fiber_autoneg()
5427 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5428 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5442 static void tg3_init_bcm8002(struct tg3 *tp) in tg3_init_bcm8002() argument
5448 if (tg3_flag(tp, INIT_COMPLETE) && in tg3_init_bcm8002()
5453 tg3_writephy(tp, 0x16, 0x8007); in tg3_init_bcm8002()
5456 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_init_bcm8002()
5464 tg3_writephy(tp, 0x10, 0x8411); in tg3_init_bcm8002()
5467 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5469 tg3_writephy(tp, 0x18, 0x00a0); in tg3_init_bcm8002()
5470 tg3_writephy(tp, 0x16, 0x41ff); in tg3_init_bcm8002()
5473 tg3_writephy(tp, 0x13, 0x0400); in tg3_init_bcm8002()
5475 tg3_writephy(tp, 0x13, 0x0000); in tg3_init_bcm8002()
5477 tg3_writephy(tp, 0x11, 0x0a50); in tg3_init_bcm8002()
5479 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5489 tg3_writephy(tp, 0x10, 0x8011); in tg3_init_bcm8002()
5492 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) in tg3_setup_fiber_hw_autoneg() argument
5506 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 && in tg3_setup_fiber_hw_autoneg()
5507 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) { in tg3_setup_fiber_hw_autoneg()
5519 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5534 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5543 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5550 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5551 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5555 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5566 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5567 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5587 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5590 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_hw_autoneg()
5592 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5593 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5595 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5596 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5618 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5620 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5622 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5629 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5630 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5637 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) in tg3_setup_fiber_by_hand() argument
5644 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5648 if (fiber_autoneg(tp, &txflags, &rxflags)) { in tg3_setup_fiber_by_hand()
5661 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5664 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_by_hand()
5686 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_by_hand()
5691 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5694 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5702 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset) in tg3_setup_fiber_phy() argument
5711 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5712 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5713 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5715 if (!tg3_flag(tp, HW_AUTONEG) && in tg3_setup_fiber_phy()
5716 tp->link_up && in tg3_setup_fiber_phy()
5717 tg3_flag(tp, INIT_COMPLETE)) { in tg3_setup_fiber_phy()
5733 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5734 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5735 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5738 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5739 tg3_init_bcm8002(tp); in tg3_setup_fiber_phy()
5746 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5749 if (tg3_flag(tp, HW_AUTONEG)) in tg3_setup_fiber_phy()
5750 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); in tg3_setup_fiber_phy()
5752 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); in tg3_setup_fiber_phy()
5754 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5756 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5771 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5772 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5773 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5776 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5781 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5782 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5787 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5788 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5789 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5794 if (!tg3_test_and_report_link_chg(tp, current_link_up)) { in tg3_setup_fiber_phy()
5795 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5797 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5798 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5799 tg3_link_report(tp); in tg3_setup_fiber_phy()
5805 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset) in tg3_setup_fiber_mii_phy() argument
5814 if ((tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_setup_fiber_mii_phy()
5815 tg3_asic_rev(tp) == ASIC_REV_5720) && in tg3_setup_fiber_mii_phy()
5816 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) && in tg3_setup_fiber_mii_phy()
5820 tg3_phy_reset(tp); in tg3_setup_fiber_mii_phy()
5822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5825 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5833 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5845 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5848 tg3_clear_mac_status(tp); in tg3_setup_fiber_mii_phy()
5853 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5854 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5857 tg3_clear_mac_status(tp); in tg3_setup_fiber_mii_phy()
5860 tg3_phy_reset(tp); in tg3_setup_fiber_mii_phy()
5862 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5864 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5865 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5866 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
5873 err |= tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_fiber_mii_phy()
5875 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5876 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5878 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5881 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5887 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5888 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5891 tg3_writephy(tp, MII_ADVERTISE, newadv); in tg3_setup_fiber_mii_phy()
5893 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_setup_fiber_mii_phy()
5896 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5897 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5907 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5917 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5920 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5924 tg3_writephy(tp, MII_ADVERTISE, adv); in tg3_setup_fiber_mii_phy()
5925 tg3_writephy(tp, MII_BMCR, bmcr | in tg3_setup_fiber_mii_phy()
5929 tg3_carrier_off(tp); in tg3_setup_fiber_mii_phy()
5931 tg3_writephy(tp, MII_BMCR, new_bmcr); in tg3_setup_fiber_mii_phy()
5933 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5934 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5935 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
5941 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5959 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); in tg3_setup_fiber_mii_phy()
5960 err |= tg3_readphy(tp, MII_LPA, &remote_adv); in tg3_setup_fiber_mii_phy()
5969 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5971 } else if (!tg3_flag(tp, 5780_CLASS)) { in tg3_setup_fiber_mii_phy()
5981 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_mii_phy()
5983 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5984 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
5985 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5987 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5992 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
5993 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
5995 tg3_test_and_report_link_chg(tp, current_link_up); in tg3_setup_fiber_mii_phy()
5999 static void tg3_serdes_parallel_detect(struct tg3 *tp) in tg3_serdes_parallel_detect() argument
6001 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
6003 tp->serdes_counter--; in tg3_serdes_parallel_detect()
6007 if (!tp->link_up && in tg3_serdes_parallel_detect()
6008 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6011 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_serdes_parallel_detect()
6016 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); in tg3_serdes_parallel_detect()
6017 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); in tg3_serdes_parallel_detect()
6020 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6022 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6023 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6033 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_serdes_parallel_detect()
6034 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6037 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6038 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6039 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6045 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6050 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_serdes_parallel_detect()
6051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); in tg3_serdes_parallel_detect()
6053 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6059 static int tg3_setup_phy(struct tg3 *tp, bool force_reset) in tg3_setup_phy() argument
6064 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6065 err = tg3_setup_fiber_phy(tp, force_reset); in tg3_setup_phy()
6066 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6067 err = tg3_setup_fiber_mii_phy(tp, force_reset); in tg3_setup_phy()
6069 err = tg3_setup_copper_phy(tp, force_reset); in tg3_setup_phy()
6071 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { in tg3_setup_phy()
6089 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_setup_phy()
6090 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_setup_phy()
6095 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6096 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6103 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_setup_phy()
6104 if (tp->link_up) { in tg3_setup_phy()
6106 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6112 if (tg3_flag(tp, ASPM_WORKAROUND)) { in tg3_setup_phy()
6114 if (!tp->link_up) in tg3_setup_phy()
6116 tp->pwrmgmt_thresh; in tg3_setup_phy()
6126 static u64 tg3_refclk_read(struct tg3 *tp) in tg3_refclk_read() argument
6133 static void tg3_refclk_write(struct tg3 *tp, u64 newval) in tg3_refclk_write() argument
6143 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6144 static inline void tg3_full_unlock(struct tg3 *tp);
6147 struct tg3 *tp = netdev_priv(dev); in tg3_get_ts_info() local
6153 if (tg3_flag(tp, PTP_CAPABLE)) { in tg3_get_ts_info()
6159 if (tp->ptp_clock) in tg3_get_ts_info()
6160 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6175 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_adjfreq() local
6195 tg3_full_lock(tp, 0); in tg3_ptp_adjfreq()
6204 tg3_full_unlock(tp); in tg3_ptp_adjfreq()
6211 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_adjtime() local
6213 tg3_full_lock(tp, 0); in tg3_ptp_adjtime()
6214 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6215 tg3_full_unlock(tp); in tg3_ptp_adjtime()
6223 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_gettime() local
6225 tg3_full_lock(tp, 0); in tg3_ptp_gettime()
6226 ns = tg3_refclk_read(tp); in tg3_ptp_gettime()
6227 ns += tp->ptp_adjust; in tg3_ptp_gettime()
6228 tg3_full_unlock(tp); in tg3_ptp_gettime()
6239 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_settime() local
6243 tg3_full_lock(tp, 0); in tg3_ptp_settime()
6244 tg3_refclk_write(tp, ns); in tg3_ptp_settime()
6245 tp->ptp_adjust = 0; in tg3_ptp_settime()
6246 tg3_full_unlock(tp); in tg3_ptp_settime()
6254 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_enable() local
6263 tg3_full_lock(tp, 0); in tg3_ptp_enable()
6274 netdev_warn(tp->dev, in tg3_ptp_enable()
6281 netdev_warn(tp->dev, in tg3_ptp_enable()
6300 tg3_full_unlock(tp); in tg3_ptp_enable()
6326 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock, in tg3_hwclock_to_timestamp() argument
6331 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6335 static void tg3_ptp_init(struct tg3 *tp) in tg3_ptp_init() argument
6337 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_ptp_init()
6341 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real())); in tg3_ptp_init()
6342 tp->ptp_adjust = 0; in tg3_ptp_init()
6343 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6347 static void tg3_ptp_resume(struct tg3 *tp) in tg3_ptp_resume() argument
6349 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_ptp_resume()
6352 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6353 tp->ptp_adjust = 0; in tg3_ptp_resume()
6356 static void tg3_ptp_fini(struct tg3 *tp) in tg3_ptp_fini() argument
6358 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6361 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6362 tp->ptp_clock = NULL; in tg3_ptp_fini()
6363 tp->ptp_adjust = 0; in tg3_ptp_fini()
6366 static inline int tg3_irq_sync(struct tg3 *tp) in tg3_irq_sync() argument
6368 return tp->irq_sync; in tg3_irq_sync()
6371 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) in tg3_rd32_loop() argument
6380 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) in tg3_dump_legacy_regs() argument
6382 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); in tg3_dump_legacy_regs()
6383 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); in tg3_dump_legacy_regs()
6384 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); in tg3_dump_legacy_regs()
6385 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); in tg3_dump_legacy_regs()
6386 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); in tg3_dump_legacy_regs()
6387 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); in tg3_dump_legacy_regs()
6388 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); in tg3_dump_legacy_regs()
6389 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); in tg3_dump_legacy_regs()
6390 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); in tg3_dump_legacy_regs()
6391 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); in tg3_dump_legacy_regs()
6392 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); in tg3_dump_legacy_regs()
6393 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); in tg3_dump_legacy_regs()
6394 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); in tg3_dump_legacy_regs()
6395 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); in tg3_dump_legacy_regs()
6396 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); in tg3_dump_legacy_regs()
6397 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); in tg3_dump_legacy_regs()
6398 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); in tg3_dump_legacy_regs()
6399 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); in tg3_dump_legacy_regs()
6400 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); in tg3_dump_legacy_regs()
6402 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_dump_legacy_regs()
6403 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); in tg3_dump_legacy_regs()
6405 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); in tg3_dump_legacy_regs()
6406 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); in tg3_dump_legacy_regs()
6407 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6408 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6409 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6410 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6411 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6412 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); in tg3_dump_legacy_regs()
6414 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_dump_legacy_regs()
6415 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6416 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6417 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6420 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); in tg3_dump_legacy_regs()
6421 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); in tg3_dump_legacy_regs()
6422 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); in tg3_dump_legacy_regs()
6423 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); in tg3_dump_legacy_regs()
6424 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); in tg3_dump_legacy_regs()
6426 if (tg3_flag(tp, NVRAM)) in tg3_dump_legacy_regs()
6427 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); in tg3_dump_legacy_regs()
6430 static void tg3_dump_state(struct tg3 *tp) in tg3_dump_state() argument
6439 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_dump_state()
6444 tg3_dump_legacy_regs(tp, regs); in tg3_dump_state()
6451 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6458 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6459 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6462 netdev_err(tp->dev, in tg3_dump_state()
6473 netdev_err(tp->dev, in tg3_dump_state()
6492 static void tg3_tx_recover(struct tg3 *tp) in tg3_tx_recover() argument
6494 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || in tg3_tx_recover()
6495 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6497 netdev_warn(tp->dev, in tg3_tx_recover()
6503 tg3_flag_set(tp, TX_RECOVERY_PENDING); in tg3_tx_recover()
6520 struct tg3 *tp = tnapi->tp; in tg3_tx() local
6524 int index = tnapi - tp->napi; in tg3_tx()
6527 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx()
6530 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6538 tg3_tx_recover(tp); in tg3_tx()
6547 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp); in tg3_tx()
6552 pci_unmap_single(tp->pdev, in tg3_tx()
6572 pci_unmap_page(tp->pdev, in tg3_tx()
6592 tg3_tx_recover(tp); in tg3_tx()
6626 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) in tg3_rx_data_free() argument
6628 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) + in tg3_rx_data_free()
6634 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), in tg3_rx_data_free()
6652 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, in tg3_alloc_rx_data() argument
6664 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6667 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6671 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6687 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) + in tg3_alloc_rx_data()
6699 mapping = pci_map_single(tp->pdev, in tg3_alloc_rx_data()
6700 data + TG3_RX_OFFSET(tp), in tg3_alloc_rx_data()
6703 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) { in tg3_alloc_rx_data()
6726 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx() local
6729 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6734 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6742 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6793 struct tg3 *tp = tnapi->tp; in tg3_rx() local
6824 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6830 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6845 tp->rx_dropped++; in tg3_rx()
6849 prefetch(data + TG3_RX_OFFSET(tp)); in tg3_rx()
6861 if (len > TG3_RX_COPY_THRESH(tp)) { in tg3_rx()
6865 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key, in tg3_rx()
6870 pci_unmap_single(tp->pdev, dma_addr, skb_size, in tg3_rx()
6885 skb_reserve(skb, TG3_RX_OFFSET(tp)); in tg3_rx()
6890 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6896 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in tg3_rx()
6898 data + TG3_RX_OFFSET(tp), in tg3_rx()
6900 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in tg3_rx()
6905 tg3_hwclock_to_timestamp(tp, tstamp, in tg3_rx()
6908 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6916 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6918 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6926 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6938 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6940 tp->rx_std_ring_mask; in tg3_rx()
6948 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
6962 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_rx()
6968 tp->rx_std_ring_mask; in tg3_rx()
6974 tp->rx_jmb_ring_mask; in tg3_rx()
6985 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
6986 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
6988 if (tnapi != &tp->napi[1]) { in tg3_rx()
6989 tp->rx_refill = true; in tg3_rx()
6990 napi_schedule(&tp->napi[1].napi); in tg3_rx()
6997 static void tg3_poll_link(struct tg3 *tp) in tg3_poll_link() argument
7000 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_poll_link()
7001 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7006 spin_lock(&tp->lock); in tg3_poll_link()
7007 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_poll_link()
7015 tg3_setup_phy(tp, false); in tg3_poll_link()
7016 spin_unlock(&tp->lock); in tg3_poll_link()
7021 static int tg3_rx_prodring_xfer(struct tg3 *tp, in tg3_rx_prodring_xfer() argument
7042 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7046 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7081 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7083 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7100 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7104 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7139 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7141 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7149 struct tg3 *tp = tnapi->tp; in tg3_poll_work() local
7154 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_work()
7168 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7169 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7174 tp->rx_refill = false; in tg3_poll_work()
7175 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7176 err |= tg3_rx_prodring_xfer(tp, dpr, in tg3_poll_work()
7177 &tp->napi[i].prodring); in tg3_poll_work()
7192 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7198 static inline void tg3_reset_task_schedule(struct tg3 *tp) in tg3_reset_task_schedule() argument
7200 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7201 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7204 static inline void tg3_reset_task_cancel(struct tg3 *tp) in tg3_reset_task_cancel() argument
7206 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7207 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task_cancel()
7208 tg3_flag_clear(tp, TX_RECOVERY_PENDING); in tg3_reset_task_cancel()
7214 struct tg3 *tp = tnapi->tp; in tg3_poll_msix() local
7221 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_msix()
7242 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7252 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7253 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7267 tg3_reset_task_schedule(tp); in tg3_poll_msix()
7271 static void tg3_process_error(struct tg3 *tp) in tg3_process_error() argument
7276 if (tg3_flag(tp, ERROR_PROCESSED)) in tg3_process_error()
7282 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7287 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7292 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7299 tg3_dump_state(tp); in tg3_process_error()
7301 tg3_flag_set(tp, ERROR_PROCESSED); in tg3_process_error()
7302 tg3_reset_task_schedule(tp); in tg3_process_error()
7308 struct tg3 *tp = tnapi->tp; in tg3_poll() local
7314 tg3_process_error(tp); in tg3_poll()
7316 tg3_poll_link(tp); in tg3_poll()
7320 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll()
7326 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_poll()
7349 tg3_reset_task_schedule(tp); in tg3_poll()
7353 static void tg3_napi_disable(struct tg3 *tp) in tg3_napi_disable() argument
7357 for (i = tp->irq_cnt - 1; i >= 0; i--) in tg3_napi_disable()
7358 napi_disable(&tp->napi[i].napi); in tg3_napi_disable()
7361 static void tg3_napi_enable(struct tg3 *tp) in tg3_napi_enable() argument
7365 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_enable()
7366 napi_enable(&tp->napi[i].napi); in tg3_napi_enable()
7369 static void tg3_napi_init(struct tg3 *tp) in tg3_napi_init() argument
7373 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); in tg3_napi_init()
7374 for (i = 1; i < tp->irq_cnt; i++) in tg3_napi_init()
7375 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); in tg3_napi_init()
7378 static void tg3_napi_fini(struct tg3 *tp) in tg3_napi_fini() argument
7382 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7383 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7386 static inline void tg3_netif_stop(struct tg3 *tp) in tg3_netif_stop() argument
7388 tp->dev->trans_start = jiffies; /* prevent tx timeout */ in tg3_netif_stop()
7389 tg3_napi_disable(tp); in tg3_netif_stop()
7390 netif_carrier_off(tp->dev); in tg3_netif_stop()
7391 netif_tx_disable(tp->dev); in tg3_netif_stop()
7395 static inline void tg3_netif_start(struct tg3 *tp) in tg3_netif_start() argument
7397 tg3_ptp_resume(tp); in tg3_netif_start()
7403 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7405 if (tp->link_up) in tg3_netif_start()
7406 netif_carrier_on(tp->dev); in tg3_netif_start()
7408 tg3_napi_enable(tp); in tg3_netif_start()
7409 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7410 tg3_enable_ints(tp); in tg3_netif_start()
7413 static void tg3_irq_quiesce(struct tg3 *tp) in tg3_irq_quiesce() argument
7414 __releases(tp->lock) in tg3_irq_quiesce()
7415 __acquires(tp->lock) in tg3_irq_quiesce()
7419 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7421 tp->irq_sync = 1; in tg3_irq_quiesce()
7424 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7426 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7427 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7429 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7437 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) in tg3_full_lock() argument
7439 spin_lock_bh(&tp->lock); in tg3_full_lock()
7441 tg3_irq_quiesce(tp); in tg3_full_lock()
7444 static inline void tg3_full_unlock(struct tg3 *tp) in tg3_full_unlock() argument
7446 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7455 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot() local
7461 if (likely(!tg3_irq_sync(tp))) in tg3_msi_1shot()
7474 struct tg3 *tp = tnapi->tp; in tg3_msi() local
7487 if (likely(!tg3_irq_sync(tp))) in tg3_msi()
7496 struct tg3 *tp = tnapi->tp; in tg3_interrupt() local
7506 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt()
7525 if (tg3_irq_sync(tp)) in tg3_interrupt()
7545 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged() local
7555 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt_tagged()
7583 if (tg3_irq_sync(tp)) in tg3_interrupt_tagged()
7598 struct tg3 *tp = tnapi->tp; in tg3_test_isr() local
7603 tg3_disable_ints(tp); in tg3_test_isr()
7613 struct tg3 *tp = netdev_priv(dev); in tg3_poll_controller() local
7615 if (tg3_irq_sync(tp)) in tg3_poll_controller()
7618 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7619 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7625 struct tg3 *tp = netdev_priv(dev); in tg3_tx_timeout() local
7627 if (netif_msg_tx_err(tp)) { in tg3_tx_timeout()
7629 tg3_dump_state(tp); in tg3_tx_timeout()
7632 tg3_reset_task_schedule(tp); in tg3_tx_timeout()
7646 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping, in tg3_4g_tso_overflow_test() argument
7649 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) { in tg3_4g_tso_overflow_test()
7658 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, in tg3_40bit_overflow_test() argument
7662 if (tg3_flag(tp, 40BIT_DMA_BUG)) in tg3_40bit_overflow_test()
7684 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set() local
7687 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) in tg3_tx_frag_set()
7693 if (tg3_4g_tso_overflow_test(tp, map, len, mss)) in tg3_tx_frag_set()
7696 if (tg3_40bit_overflow_test(tp, map, len)) in tg3_tx_frag_set()
7699 if (tp->dma_limit) { in tg3_tx_frag_set()
7702 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7703 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7704 len -= tp->dma_limit; in tg3_tx_frag_set()
7708 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7709 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7752 pci_unmap_single(tnapi->tp->pdev, in tg3_tx_skb_unmap()
7769 pci_unmap_page(tnapi->tp->pdev, in tg3_tx_skb_unmap()
7787 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround() local
7792 if (tg3_asic_rev(tp) != ASIC_REV_5701) in tigon3_dma_hwbug_workaround()
7806 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, in tigon3_dma_hwbug_workaround()
7809 if (pci_dma_mapping_error(tp->pdev, new_addr)) { in tigon3_dma_hwbug_workaround()
7849 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi, in tg3_tso_bug() argument
7871 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7880 tg3_start_xmit(nskb, tp->dev); in tg3_tso_bug()
7892 struct tg3 *tp = netdev_priv(dev); in tg3_start_xmit() local
7906 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in tg3_start_xmit()
7907 if (tg3_flag(tp, ENABLE_TSS)) in tg3_start_xmit()
7949 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
7955 tg3_flag(tp, TSO_BUG)) { in tg3_start_xmit()
7957 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
7972 if (tg3_flag(tp, HW_TSO_1) || in tg3_start_xmit()
7973 tg3_flag(tp, HW_TSO_2) || in tg3_start_xmit()
7974 tg3_flag(tp, HW_TSO_3)) { in tg3_start_xmit()
7982 if (tg3_flag(tp, HW_TSO_3)) { in tg3_start_xmit()
7987 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_start_xmit()
7989 else if (tg3_flag(tp, HW_TSO_1) || in tg3_start_xmit()
7990 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_start_xmit()
8018 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in tg3_start_xmit()
8028 tg3_flag(tp, TX_TSTAMP_EN)) { in tg3_start_xmit()
8035 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); in tg3_start_xmit()
8036 if (pci_dma_mapping_error(tp->pdev, mapping)) in tg3_start_xmit()
8045 if (tg3_flag(tp, 5701_DMA_BUG)) in tg3_start_xmit()
8055 if (!tg3_flag(tp, HW_TSO_1) && in tg3_start_xmit()
8056 !tg3_flag(tp, HW_TSO_2) && in tg3_start_xmit()
8057 !tg3_flag(tp, HW_TSO_3)) in tg3_start_xmit()
8068 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in tg3_start_xmit()
8074 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8100 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
8147 tp->tx_dropped++; in tg3_start_xmit()
8151 static void tg3_mac_loopback(struct tg3 *tp, bool enable) in tg3_mac_loopback() argument
8154 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8157 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8159 if (!tg3_flag(tp, 5705_PLUS)) in tg3_mac_loopback()
8160 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8162 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8163 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8165 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8167 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8169 if (tg3_flag(tp, 5705_PLUS) || in tg3_mac_loopback()
8170 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8171 tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_mac_loopback()
8172 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8175 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8179 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) in tg3_phy_lpbk_set() argument
8183 tg3_phy_toggle_apd(tp, false); in tg3_phy_lpbk_set()
8184 tg3_phy_toggle_automdix(tp, false); in tg3_phy_lpbk_set()
8186 if (extlpbk && tg3_phy_set_extloopbk(tp)) in tg3_phy_lpbk_set()
8198 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8208 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8209 tg3_readphy(tp, MII_CTRL1000, &val); in tg3_phy_lpbk_set()
8212 tg3_writephy(tp, MII_CTRL1000, val); in tg3_phy_lpbk_set()
8216 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); in tg3_phy_lpbk_set()
8221 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_lpbk_set()
8224 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8225 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_phy_lpbk_set()
8229 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8230 tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_phy_lpbk_set()
8231 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | in tg3_phy_lpbk_set()
8236 tg3_readphy(tp, MII_TG3_FET_PTEST, &val); in tg3_phy_lpbk_set()
8240 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8241 tg3_flag(tp, 5780_CLASS)) { in tg3_phy_lpbk_set()
8244 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8247 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8254 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_phy_lpbk_set()
8255 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8262 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_lpbk_set()
8274 struct tg3 *tp = netdev_priv(dev); in tg3_set_loopback() local
8277 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8280 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8281 tg3_mac_loopback(tp, true); in tg3_set_loopback()
8282 netif_carrier_on(tp->dev); in tg3_set_loopback()
8283 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8286 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8289 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8290 tg3_mac_loopback(tp, false); in tg3_set_loopback()
8292 tg3_setup_phy(tp, true); in tg3_set_loopback()
8293 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8301 struct tg3 *tp = netdev_priv(dev); in tg3_fix_features() local
8303 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8319 static void tg3_rx_prodring_free(struct tg3 *tp, in tg3_rx_prodring_free() argument
8324 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8326 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8327 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8328 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8330 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_rx_prodring_free()
8333 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8334 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8342 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8343 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8344 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8346 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_free()
8347 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8348 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8360 static int tg3_rx_prodring_alloc(struct tg3 *tp, in tg3_rx_prodring_alloc() argument
8370 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8372 TG3_RX_STD_BUFF_RING_SIZE(tp)); in tg3_rx_prodring_alloc()
8375 TG3_RX_JMB_BUFF_RING_SIZE(tp)); in tg3_rx_prodring_alloc()
8380 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8383 if (tg3_flag(tp, 5780_CLASS) && in tg3_rx_prodring_alloc()
8384 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8386 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8392 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8403 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8406 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i, in tg3_rx_prodring_alloc()
8408 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8411 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8414 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8419 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_rx_prodring_alloc()
8422 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8424 if (!tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_rx_prodring_alloc()
8427 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8438 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8441 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i, in tg3_rx_prodring_alloc()
8443 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8446 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8449 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8458 tg3_rx_prodring_free(tp, tpr); in tg3_rx_prodring_alloc()
8462 static void tg3_rx_prodring_fini(struct tg3 *tp, in tg3_rx_prodring_fini() argument
8470 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8475 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8481 static int tg3_rx_prodring_init(struct tg3 *tp, in tg3_rx_prodring_init() argument
8484 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8489 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8490 TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_init()
8496 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_init()
8497 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8502 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8503 TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_init()
8513 tg3_rx_prodring_fini(tp, tpr); in tg3_rx_prodring_init()
8524 static void tg3_free_rings(struct tg3 *tp) in tg3_free_rings() argument
8528 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8529 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8531 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8547 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8558 static int tg3_init_rings(struct tg3 *tp) in tg3_init_rings() argument
8563 tg3_free_rings(tp); in tg3_init_rings()
8565 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8566 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8581 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8584 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8585 tg3_free_rings(tp); in tg3_init_rings()
8593 static void tg3_mem_tx_release(struct tg3 *tp) in tg3_mem_tx_release() argument
8597 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8598 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8601 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8611 static int tg3_mem_tx_acquire(struct tg3 *tp) in tg3_mem_tx_acquire() argument
8614 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8619 if (tg3_flag(tp, ENABLE_TSS)) in tg3_mem_tx_acquire()
8622 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8628 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8639 tg3_mem_tx_release(tp); in tg3_mem_tx_acquire()
8643 static void tg3_mem_rx_release(struct tg3 *tp) in tg3_mem_rx_release() argument
8647 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8648 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8650 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8655 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8656 TG3_RX_RCB_RING_BYTES(tp), in tg3_mem_rx_release()
8663 static int tg3_mem_rx_acquire(struct tg3 *tp) in tg3_mem_rx_acquire() argument
8667 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8672 if (tg3_flag(tp, ENABLE_RSS)) in tg3_mem_rx_acquire()
8676 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8678 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8685 if (!i && tg3_flag(tp, ENABLE_RSS)) in tg3_mem_rx_acquire()
8688 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8689 TG3_RX_RCB_RING_BYTES(tp), in tg3_mem_rx_acquire()
8699 tg3_mem_rx_release(tp); in tg3_mem_rx_acquire()
8707 static void tg3_free_consistent(struct tg3 *tp) in tg3_free_consistent() argument
8711 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8712 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8715 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8722 tg3_mem_rx_release(tp); in tg3_free_consistent()
8723 tg3_mem_tx_release(tp); in tg3_free_consistent()
8725 if (tp->hw_stats) { in tg3_free_consistent()
8726 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8727 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8728 tp->hw_stats = NULL; in tg3_free_consistent()
8736 static int tg3_alloc_consistent(struct tg3 *tp) in tg3_alloc_consistent() argument
8740 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8742 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8743 if (!tp->hw_stats) in tg3_alloc_consistent()
8746 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8747 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8750 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8759 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_alloc_consistent()
8788 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp)) in tg3_alloc_consistent()
8794 tg3_free_consistent(tp); in tg3_alloc_consistent()
8803 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent) in tg3_stop_block() argument
8808 if (tg3_flag(tp, 5705_PLUS)) { in tg3_stop_block()
8830 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8831 dev_err(&tp->pdev->dev, in tg3_stop_block()
8845 dev_err(&tp->pdev->dev, in tg3_stop_block()
8855 static int tg3_abort_hw(struct tg3 *tp, bool silent) in tg3_abort_hw() argument
8859 tg3_disable_ints(tp); in tg3_abort_hw()
8861 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8862 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8863 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8868 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8869 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
8872 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8873 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); in tg3_abort_hw()
8874 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); in tg3_abort_hw()
8875 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8876 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); in tg3_abort_hw()
8877 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); in tg3_abort_hw()
8879 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); in tg3_abort_hw()
8880 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8881 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); in tg3_abort_hw()
8882 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8883 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); in tg3_abort_hw()
8884 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8885 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); in tg3_abort_hw()
8887 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8888 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
8891 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
8892 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
8900 dev_err(&tp->pdev->dev, in tg3_abort_hw()
8906 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); in tg3_abort_hw()
8907 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8908 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); in tg3_abort_hw()
8913 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); in tg3_abort_hw()
8914 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); in tg3_abort_hw()
8917 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
8918 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
8927 static void tg3_save_pci_state(struct tg3 *tp) in tg3_save_pci_state() argument
8929 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
8933 static void tg3_restore_pci_state(struct tg3 *tp) in tg3_restore_pci_state() argument
8938 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
8939 tp->misc_host_ctrl); in tg3_restore_pci_state()
8943 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && in tg3_restore_pci_state()
8944 tg3_flag(tp, PCIX_MODE)) in tg3_restore_pci_state()
8947 if (tg3_flag(tp, ENABLE_APE)) in tg3_restore_pci_state()
8951 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
8953 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
8955 if (!tg3_flag(tp, PCI_EXPRESS)) { in tg3_restore_pci_state()
8956 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
8957 tp->pci_cacheline_sz); in tg3_restore_pci_state()
8958 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
8959 tp->pci_lat_timer); in tg3_restore_pci_state()
8963 if (tg3_flag(tp, PCIX_MODE)) { in tg3_restore_pci_state()
8966 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8969 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8973 if (tg3_flag(tp, 5780_CLASS)) { in tg3_restore_pci_state()
8978 if (tg3_flag(tp, USING_MSI)) { in tg3_restore_pci_state()
8981 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
8982 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
8984 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
8985 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
8993 static void tg3_override_clk(struct tg3 *tp) in tg3_override_clk() argument
8997 switch (tg3_asic_rev(tp)) { in tg3_override_clk()
9014 static void tg3_restore_clk(struct tg3 *tp) in tg3_restore_clk() argument
9018 switch (tg3_asic_rev(tp)) { in tg3_restore_clk()
9037 static int tg3_chip_reset(struct tg3 *tp) in tg3_chip_reset() argument
9038 __releases(tp->lock) in tg3_chip_reset()
9039 __acquires(tp->lock) in tg3_chip_reset()
9045 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9048 tg3_nvram_lock(tp); in tg3_chip_reset()
9050 tg3_ape_lock(tp, TG3_APE_LOCK_GRC); in tg3_chip_reset()
9055 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9061 tg3_save_pci_state(tp); in tg3_chip_reset()
9063 if (tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_chip_reset()
9064 tg3_flag(tp, 5755_PLUS)) in tg3_chip_reset()
9073 write_op = tp->write32; in tg3_chip_reset()
9075 tp->write32 = tg3_write32; in tg3_chip_reset()
9083 tg3_flag_set(tp, CHIP_RESETTING); in tg3_chip_reset()
9084 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9085 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9095 tg3_full_unlock(tp); in tg3_chip_reset()
9097 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9098 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9100 tg3_full_lock(tp, 0); in tg3_chip_reset()
9102 if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_chip_reset()
9110 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_chip_reset()
9112 if (tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_chip_reset()
9113 !tg3_flag(tp, 57765_PLUS) && in tg3_chip_reset()
9118 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) { in tg3_chip_reset()
9124 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_chip_reset()
9135 tg3_override_clk(tp); in tg3_chip_reset()
9138 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
9144 tp->write32 = write_op; in tg3_chip_reset()
9167 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9171 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9174 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) { in tg3_chip_reset()
9182 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9183 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9193 if (!tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
9195 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9198 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9205 tg3_restore_pci_state(tp); in tg3_chip_reset()
9207 tg3_flag_clear(tp, CHIP_RESETTING); in tg3_chip_reset()
9208 tg3_flag_clear(tp, ERROR_PROCESSED); in tg3_chip_reset()
9211 if (tg3_flag(tp, 5780_CLASS)) in tg3_chip_reset()
9215 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) { in tg3_chip_reset()
9216 tg3_stop_fw(tp); in tg3_chip_reset()
9220 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_chip_reset()
9226 tg3_stop_fw(tp); in tg3_chip_reset()
9227 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_chip_reset()
9230 err = tg3_poll_fw(tp); in tg3_chip_reset()
9234 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9236 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) { in tg3_chip_reset()
9242 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9243 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_chip_reset()
9244 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9245 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) in tg3_chip_reset()
9246 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9247 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9250 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9251 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9252 val = tp->mac_mode; in tg3_chip_reset()
9253 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9254 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9255 val = tp->mac_mode; in tg3_chip_reset()
9262 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); in tg3_chip_reset()
9264 tg3_mdio_start(tp); in tg3_chip_reset()
9266 if (tg3_flag(tp, PCI_EXPRESS) && in tg3_chip_reset()
9267 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && in tg3_chip_reset()
9268 tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_chip_reset()
9269 !tg3_flag(tp, 57765_PLUS)) { in tg3_chip_reset()
9275 tg3_restore_clk(tp); in tg3_chip_reset()
9278 tg3_flag_clear(tp, ENABLE_ASF); in tg3_chip_reset()
9279 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9282 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); in tg3_chip_reset()
9283 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); in tg3_chip_reset()
9287 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); in tg3_chip_reset()
9289 tg3_flag_set(tp, ENABLE_ASF); in tg3_chip_reset()
9290 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9291 if (tg3_flag(tp, 5750_PLUS)) in tg3_chip_reset()
9292 tg3_flag_set(tp, ASF_NEW_HANDSHAKE); in tg3_chip_reset()
9294 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg); in tg3_chip_reset()
9296 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9298 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9310 static int tg3_halt(struct tg3 *tp, int kind, bool silent) in tg3_halt() argument
9314 tg3_stop_fw(tp); in tg3_halt()
9316 tg3_write_sig_pre_reset(tp, kind); in tg3_halt()
9318 tg3_abort_hw(tp, silent); in tg3_halt()
9319 err = tg3_chip_reset(tp); in tg3_halt()
9321 __tg3_set_mac_addr(tp, false); in tg3_halt()
9323 tg3_write_sig_legacy(tp, kind); in tg3_halt()
9324 tg3_write_sig_post_reset(tp, kind); in tg3_halt()
9326 if (tp->hw_stats) { in tg3_halt()
9328 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9329 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9332 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9340 struct tg3 *tp = netdev_priv(dev); in tg3_set_mac_addr() local
9353 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_set_mac_addr()
9366 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9367 __tg3_set_mac_addr(tp, skip_mac_1); in tg3_set_mac_addr()
9369 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9375 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, in tg3_set_bdinfo() argument
9379 tg3_write_mem(tp, in tg3_set_bdinfo()
9382 tg3_write_mem(tp, in tg3_set_bdinfo()
9385 tg3_write_mem(tp, in tg3_set_bdinfo()
9389 if (!tg3_flag(tp, 5705_PLUS)) in tg3_set_bdinfo()
9390 tg3_write_mem(tp, in tg3_set_bdinfo()
9396 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec) in tg3_coal_tx_init() argument
9400 if (!tg3_flag(tp, ENABLE_TSS)) { in tg3_coal_tx_init()
9409 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9421 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9428 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec) in tg3_coal_rx_init() argument
9431 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9433 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_coal_rx_init()
9455 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9462 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) in __tg3_set_coalesce() argument
9464 tg3_coal_tx_init(tp, ec); in __tg3_set_coalesce()
9465 tg3_coal_rx_init(tp, ec); in __tg3_set_coalesce()
9467 if (!tg3_flag(tp, 5705_PLUS)) { in __tg3_set_coalesce()
9473 if (!tp->link_up) in __tg3_set_coalesce()
9481 static void tg3_tx_rcbs_disable(struct tg3 *tp) in tg3_tx_rcbs_disable() argument
9486 if (!tg3_flag(tp, 5705_PLUS)) in tg3_tx_rcbs_disable()
9488 else if (tg3_flag(tp, 5717_PLUS)) in tg3_tx_rcbs_disable()
9490 else if (tg3_flag(tp, 57765_CLASS) || in tg3_tx_rcbs_disable()
9491 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_tx_rcbs_disable()
9498 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, in tg3_tx_rcbs_disable()
9503 static void tg3_tx_rcbs_init(struct tg3 *tp) in tg3_tx_rcbs_init() argument
9508 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx_rcbs_init()
9511 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9512 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9517 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9524 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp) in tg3_rx_ret_rcbs_disable() argument
9529 if (tg3_flag(tp, 5717_PLUS)) in tg3_rx_ret_rcbs_disable()
9531 else if (!tg3_flag(tp, 5705_PLUS)) in tg3_rx_ret_rcbs_disable()
9533 else if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_rx_ret_rcbs_disable()
9534 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_rx_ret_rcbs_disable()
9535 tg3_flag(tp, 57765_CLASS)) in tg3_rx_ret_rcbs_disable()
9542 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, in tg3_rx_ret_rcbs_disable()
9547 static void tg3_rx_ret_rcbs_init(struct tg3 *tp) in tg3_rx_ret_rcbs_init() argument
9552 if (tg3_flag(tp, ENABLE_RSS)) in tg3_rx_ret_rcbs_init()
9555 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9556 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9561 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9562 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9568 static void tg3_rings_reset(struct tg3 *tp) in tg3_rings_reset() argument
9572 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9574 tg3_tx_rcbs_disable(tp); in tg3_rings_reset()
9576 tg3_rx_ret_rcbs_disable(tp); in tg3_rings_reset()
9579 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9580 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9581 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9582 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9585 if (tg3_flag(tp, SUPPORT_MSIX)) { in tg3_rings_reset()
9586 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9587 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9588 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9589 if (tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
9590 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9591 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9592 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9593 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9594 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9595 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9597 if (!tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
9598 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9600 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9601 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9602 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9603 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9607 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_rings_reset()
9624 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9634 tg3_tx_rcbs_init(tp); in tg3_rings_reset()
9635 tg3_rx_ret_rcbs_init(tp); in tg3_rings_reset()
9638 static void tg3_setup_rxbd_thresholds(struct tg3 *tp) in tg3_setup_rxbd_thresholds() argument
9642 if (!tg3_flag(tp, 5750_PLUS) || in tg3_setup_rxbd_thresholds()
9643 tg3_flag(tp, 5780_CLASS) || in tg3_setup_rxbd_thresholds()
9644 tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_setup_rxbd_thresholds()
9645 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_setup_rxbd_thresholds()
9646 tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9648 else if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_setup_rxbd_thresholds()
9649 tg3_asic_rev(tp) == ASIC_REV_5787) in tg3_setup_rxbd_thresholds()
9654 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9655 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9660 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9663 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_setup_rxbd_thresholds()
9668 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9673 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9701 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) in tg3_set_multi() argument
9712 struct tg3 *tp = netdev_priv(dev); in __tg3_set_rx_mode() local
9715 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9722 if (!tg3_flag(tp, ENABLE_ASF)) in __tg3_set_rx_mode()
9731 tg3_set_multi(tp, 1); in __tg3_set_rx_mode()
9734 tg3_set_multi(tp, 0); in __tg3_set_rx_mode()
9757 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) { in __tg3_set_rx_mode()
9765 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9766 i + TG3_UCAST_ADDR_IDX(tp)); in __tg3_set_rx_mode()
9771 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9772 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9778 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt) in tg3_rss_init_dflt_indir_tbl() argument
9783 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9786 static void tg3_rss_check_indir_tbl(struct tg3 *tp) in tg3_rss_check_indir_tbl() argument
9790 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_rss_check_indir_tbl()
9793 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9794 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9800 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9805 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9808 static void tg3_rss_write_indir_tbl(struct tg3 *tp) in tg3_rss_write_indir_tbl() argument
9814 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9818 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9825 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp) in tg3_lso_rd_dma_workaround_bit() argument
9827 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_lso_rd_dma_workaround_bit()
9834 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) in tg3_reset_hw() argument
9838 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9840 tg3_disable_ints(tp); in tg3_reset_hw()
9842 tg3_stop_fw(tp); in tg3_reset_hw()
9844 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); in tg3_reset_hw()
9846 if (tg3_flag(tp, INIT_COMPLETE)) in tg3_reset_hw()
9847 tg3_abort_hw(tp, 1); in tg3_reset_hw()
9849 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9850 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9851 tg3_phy_pull_config(tp); in tg3_reset_hw()
9852 tg3_eee_pull_config(tp, NULL); in tg3_reset_hw()
9853 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9857 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
9858 tg3_setup_eee(tp); in tg3_reset_hw()
9861 tg3_phy_reset(tp); in tg3_reset_hw()
9863 err = tg3_chip_reset(tp); in tg3_reset_hw()
9867 tg3_write_sig_legacy(tp, RESET_KIND_INIT); in tg3_reset_hw()
9869 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { in tg3_reset_hw()
9890 if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_reset_hw()
9905 if (tg3_flag(tp, L1PLLPD_EN)) { in tg3_reset_hw()
9919 if (tg3_flag(tp, 57765_CLASS)) { in tg3_reset_hw()
9920 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { in tg3_reset_hw()
9935 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) { in tg3_reset_hw()
9969 if (!tg3_flag(tp, CPMU_PRESENT)) { in tg3_reset_hw()
9970 if (!tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
9971 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
9972 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
9975 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && in tg3_reset_hw()
9976 tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
9982 if (tg3_flag(tp, ENABLE_APE)) { in tg3_reset_hw()
9993 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) { in tg3_reset_hw()
10005 err = tg3_init_rings(tp); in tg3_reset_hw()
10009 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10012 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) in tg3_reset_hw()
10014 if (!tg3_flag(tp, 57765_CLASS) && in tg3_reset_hw()
10015 tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_reset_hw()
10016 tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_reset_hw()
10018 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10019 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 && in tg3_reset_hw()
10020 tg3_asic_rev(tp) != ASIC_REV_5761) { in tg3_reset_hw()
10024 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10027 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10031 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10039 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10042 if (tp->rxptpctl) in tg3_reset_hw()
10044 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10046 if (tg3_flag(tp, PTP_CAPABLE)) in tg3_reset_hw()
10049 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10058 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
10060 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) { in tg3_reset_hw()
10062 if (tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_reset_hw()
10068 } else if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10071 fw_len = tp->fw_len; in tg3_reset_hw()
10079 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10081 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10083 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10085 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10088 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10090 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10092 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10095 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10097 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10100 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_reset_hw()
10102 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_reset_hw()
10103 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_reset_hw()
10104 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10105 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) in tg3_reset_hw()
10114 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10118 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1) in tg3_reset_hw()
10121 tg3_setup_rxbd_thresholds(tp); in tg3_reset_hw()
10144 if (!tg3_flag(tp, 5717_PLUS)) in tg3_reset_hw()
10149 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10156 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10157 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { in tg3_reset_hw()
10159 if (tg3_flag(tp, JUMBO_RING_ENABLE)) { in tg3_reset_hw()
10164 val = TG3_RX_JMB_RING_SIZE(tp) << in tg3_reset_hw()
10168 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || in tg3_reset_hw()
10169 tg3_flag(tp, 57765_CLASS) || in tg3_reset_hw()
10170 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10178 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10179 val = TG3_RX_STD_RING_SIZE(tp); in tg3_reset_hw()
10189 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10193 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10196 tg3_rings_reset(tp); in tg3_reset_hw()
10199 __tg3_set_mac_addr(tp, false); in tg3_reset_hw()
10203 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10212 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10213 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10233 if (tg3_asic_rev(tp) == ASIC_REV_5717) in tg3_reset_hw()
10236 if (tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_reset_hw()
10237 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10238 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_reset_hw()
10243 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_reset_hw()
10244 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_reset_hw()
10245 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_reset_hw()
10246 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_reset_hw()
10249 !tg3_flag(tp, IS_5788)) { in tg3_reset_hw()
10254 if (tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
10257 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_reset_hw()
10258 tp->dma_limit = 0; in tg3_reset_hw()
10259 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10261 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10265 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
10266 tg3_flag(tp, HW_TSO_2) || in tg3_reset_hw()
10267 tg3_flag(tp, HW_TSO_3)) in tg3_reset_hw()
10270 if (tg3_flag(tp, 57765_PLUS) || in tg3_reset_hw()
10271 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10272 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_reset_hw()
10275 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10276 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10279 if (tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_reset_hw()
10280 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_reset_hw()
10281 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10282 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_reset_hw()
10283 tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10286 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10292 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10293 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10304 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_reset_hw()
10305 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10306 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10309 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10321 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
10326 tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10347 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10349 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
10355 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10357 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10366 tg3_write_mem(tp, i, 0); in tg3_reset_hw()
10371 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10375 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10378 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10379 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10385 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10388 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
10389 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10390 if (!tg3_flag(tp, 5705_PLUS) && in tg3_reset_hw()
10391 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10392 tg3_asic_rev(tp) != ASIC_REV_5700) in tg3_reset_hw()
10393 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10394 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10403 if (!tg3_flag(tp, IS_NIC)) { in tg3_reset_hw()
10410 if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_reset_hw()
10414 if (tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_reset_hw()
10417 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10418 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10421 if (tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_reset_hw()
10422 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10425 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10428 if (tg3_flag(tp, USING_MSIX)) { in tg3_reset_hw()
10431 if (tp->irq_cnt > 1) in tg3_reset_hw()
10433 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_reset_hw()
10438 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
10449 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_reset_hw()
10450 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_reset_hw()
10451 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_reset_hw()
10452 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 || in tg3_reset_hw()
10453 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) { in tg3_reset_hw()
10456 !tg3_flag(tp, IS_5788)) { in tg3_reset_hw()
10462 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
10465 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_reset_hw()
10471 if (tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
10474 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10476 if (tg3_asic_rev(tp) == ASIC_REV_5703) { in tg3_reset_hw()
10479 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_reset_hw()
10483 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10490 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_reset_hw()
10491 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_reset_hw()
10493 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) in tg3_reset_hw()
10498 val |= tg3_lso_rd_dma_workaround_bit(tp); in tg3_reset_hw()
10500 tg3_flag_set(tp, 5719_5720_RDMA_BUG); in tg3_reset_hw()
10505 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10508 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_reset_hw()
10517 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_reset_hw()
10521 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
10522 tg3_flag(tp, HW_TSO_2) || in tg3_reset_hw()
10523 tg3_flag(tp, HW_TSO_3)) in tg3_reset_hw()
10526 if (tg3_flag(tp, ENABLE_TSS)) in tg3_reset_hw()
10531 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { in tg3_reset_hw()
10532 err = tg3_load_5701_a0_firmware_fix(tp); in tg3_reset_hw()
10537 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_reset_hw()
10541 tg3_load_57766_firmware(tp); in tg3_reset_hw()
10544 if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10545 err = tg3_load_tso_firmware(tp); in tg3_reset_hw()
10550 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10552 if (tg3_flag(tp, 5755_PLUS) || in tg3_reset_hw()
10553 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_reset_hw()
10554 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10556 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10557 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10559 tp->tx_mode &= ~val; in tg3_reset_hw()
10560 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10563 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10566 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_reset_hw()
10569 tg3_rss_write_indir_tbl(tp); in tg3_reset_hw()
10577 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10578 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
10579 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10581 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10582 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10584 if (tg3_flag(tp, ENABLE_RSS)) in tg3_reset_hw()
10585 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10592 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10595 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10598 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10602 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10605 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10606 if ((tg3_asic_rev(tp) == ASIC_REV_5704) && in tg3_reset_hw()
10607 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10615 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) in tg3_reset_hw()
10622 if (tg3_flag(tp, 57765_CLASS)) in tg3_reset_hw()
10628 if (tg3_asic_rev(tp) == ASIC_REV_5704 && in tg3_reset_hw()
10629 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10631 tg3_flag_set(tp, HW_AUTONEG); in tg3_reset_hw()
10634 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10635 tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_reset_hw()
10640 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10641 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10642 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10645 if (!tg3_flag(tp, USE_PHYLIB)) { in tg3_reset_hw()
10646 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10647 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10649 err = tg3_setup_phy(tp, false); in tg3_reset_hw()
10653 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10654 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10658 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { in tg3_reset_hw()
10659 tg3_writephy(tp, MII_TG3_TEST1, in tg3_reset_hw()
10661 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); in tg3_reset_hw()
10666 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10674 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) in tg3_reset_hw()
10678 if (tg3_flag(tp, ENABLE_ASF)) in tg3_reset_hw()
10716 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
10718 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, in tg3_reset_hw()
10721 tg3_write_sig_post_reset(tp, RESET_KIND_INIT); in tg3_reset_hw()
10729 static int tg3_init_hw(struct tg3 *tp, bool reset_phy) in tg3_init_hw() argument
10735 tg3_enable_register_access(tp); in tg3_init_hw()
10736 tg3_poll_fw(tp); in tg3_init_hw()
10738 tg3_switch_clocks(tp); in tg3_init_hw()
10742 return tg3_reset_hw(tp, reset_phy); in tg3_init_hw()
10745 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir) in tg3_sd_scan_scratchpad() argument
10752 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len); in tg3_sd_scan_scratchpad()
10766 struct tg3 *tp = dev_get_drvdata(dev); in tg3_show_temp() local
10769 spin_lock_bh(&tp->lock); in tg3_show_temp()
10770 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10772 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10792 static void tg3_hwmon_close(struct tg3 *tp) in tg3_hwmon_close() argument
10794 if (tp->hwmon_dev) { in tg3_hwmon_close()
10795 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10796 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10800 static void tg3_hwmon_open(struct tg3 *tp) in tg3_hwmon_open() argument
10804 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10807 tg3_sd_scan_scratchpad(tp, ocirs); in tg3_hwmon_open()
10820 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10821 tp, tg3_groups); in tg3_hwmon_open()
10822 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10823 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10836 static void tg3_periodic_fetch_stats(struct tg3 *tp) in tg3_periodic_fetch_stats() argument
10838 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10840 if (!tp->link_up) in tg3_periodic_fetch_stats()
10856 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) && in tg3_periodic_fetch_stats()
10862 val &= ~tg3_lso_rd_dma_workaround_bit(tp); in tg3_periodic_fetch_stats()
10864 tg3_flag_clear(tp, 5719_5720_RDMA_BUG); in tg3_periodic_fetch_stats()
10883 if (tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_periodic_fetch_stats()
10884 tg3_asic_rev(tp) != ASIC_REV_5762 && in tg3_periodic_fetch_stats()
10885 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 && in tg3_periodic_fetch_stats()
10886 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) { in tg3_periodic_fetch_stats()
10902 static void tg3_chk_missed_msi(struct tg3 *tp) in tg3_chk_missed_msi() argument
10906 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
10907 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
10927 struct tg3 *tp = (struct tg3 *) __opaque; in tg3_timer() local
10929 spin_lock(&tp->lock); in tg3_timer()
10931 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
10932 spin_unlock(&tp->lock); in tg3_timer()
10936 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_timer()
10937 tg3_flag(tp, 57765_CLASS)) in tg3_timer()
10938 tg3_chk_missed_msi(tp); in tg3_timer()
10940 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { in tg3_timer()
10945 if (!tg3_flag(tp, TAGGED_STATUS)) { in tg3_timer()
10950 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
10952 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
10954 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
10959 spin_unlock(&tp->lock); in tg3_timer()
10960 tg3_reset_task_schedule(tp); in tg3_timer()
10966 if (!--tp->timer_counter) { in tg3_timer()
10967 if (tg3_flag(tp, 5705_PLUS)) in tg3_timer()
10968 tg3_periodic_fetch_stats(tp); in tg3_timer()
10970 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
10971 tg3_phy_eee_enable(tp); in tg3_timer()
10973 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_timer()
10980 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
10987 tg3_setup_phy(tp, false); in tg3_timer()
10988 } else if (tg3_flag(tp, POLL_SERDES)) { in tg3_timer()
10992 if (tp->link_up && in tg3_timer()
10996 if (!tp->link_up && in tg3_timer()
11002 if (!tp->serdes_counter) { in tg3_timer()
11004 (tp->mac_mode & in tg3_timer()
11007 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11010 tg3_setup_phy(tp, false); in tg3_timer()
11012 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11013 tg3_flag(tp, 5780_CLASS)) { in tg3_timer()
11014 tg3_serdes_parallel_detect(tp); in tg3_timer()
11015 } else if (tg3_flag(tp, POLL_CPMU_LINK)) { in tg3_timer()
11020 if (link_up != tp->link_up) in tg3_timer()
11021 tg3_setup_phy(tp, false); in tg3_timer()
11024 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11044 if (!--tp->asf_counter) { in tg3_timer()
11045 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_timer()
11046 tg3_wait_for_event_ack(tp); in tg3_timer()
11048 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, in tg3_timer()
11050 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); in tg3_timer()
11051 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, in tg3_timer()
11054 tg3_generate_fw_event(tp); in tg3_timer()
11056 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11059 spin_unlock(&tp->lock); in tg3_timer()
11062 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11063 add_timer(&tp->timer); in tg3_timer()
11066 static void tg3_timer_init(struct tg3 *tp) in tg3_timer_init() argument
11068 if (tg3_flag(tp, TAGGED_STATUS) && in tg3_timer_init()
11069 tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_timer_init()
11070 !tg3_flag(tp, 57765_CLASS)) in tg3_timer_init()
11071 tp->timer_offset = HZ; in tg3_timer_init()
11073 tp->timer_offset = HZ / 10; in tg3_timer_init()
11075 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11077 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11078 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11081 init_timer(&tp->timer); in tg3_timer_init()
11082 tp->timer.data = (unsigned long) tp; in tg3_timer_init()
11083 tp->timer.function = tg3_timer; in tg3_timer_init()
11086 static void tg3_timer_start(struct tg3 *tp) in tg3_timer_start() argument
11088 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11089 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11091 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11092 add_timer(&tp->timer); in tg3_timer_start()
11095 static void tg3_timer_stop(struct tg3 *tp) in tg3_timer_stop() argument
11097 del_timer_sync(&tp->timer); in tg3_timer_stop()
11103 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy) in tg3_restart_hw() argument
11104 __releases(tp->lock) in tg3_restart_hw()
11105 __acquires(tp->lock) in tg3_restart_hw()
11109 err = tg3_init_hw(tp, reset_phy); in tg3_restart_hw()
11111 netdev_err(tp->dev, in tg3_restart_hw()
11113 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_restart_hw()
11114 tg3_full_unlock(tp); in tg3_restart_hw()
11115 tg3_timer_stop(tp); in tg3_restart_hw()
11116 tp->irq_sync = 0; in tg3_restart_hw()
11117 tg3_napi_enable(tp); in tg3_restart_hw()
11118 dev_close(tp->dev); in tg3_restart_hw()
11119 tg3_full_lock(tp, 0); in tg3_restart_hw()
11126 struct tg3 *tp = container_of(work, struct tg3, reset_task); in tg3_reset_task() local
11130 tg3_full_lock(tp, 0); in tg3_reset_task()
11132 if (!netif_running(tp->dev)) { in tg3_reset_task()
11133 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11134 tg3_full_unlock(tp); in tg3_reset_task()
11139 tg3_full_unlock(tp); in tg3_reset_task()
11141 tg3_phy_stop(tp); in tg3_reset_task()
11143 tg3_netif_stop(tp); in tg3_reset_task()
11145 tg3_full_lock(tp, 1); in tg3_reset_task()
11147 if (tg3_flag(tp, TX_RECOVERY_PENDING)) { in tg3_reset_task()
11148 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11149 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11150 tg3_flag_set(tp, MBOX_WRITE_REORDER); in tg3_reset_task()
11151 tg3_flag_clear(tp, TX_RECOVERY_PENDING); in tg3_reset_task()
11154 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_reset_task()
11155 err = tg3_init_hw(tp, true); in tg3_reset_task()
11159 tg3_netif_start(tp); in tg3_reset_task()
11162 tg3_full_unlock(tp); in tg3_reset_task()
11165 tg3_phy_start(tp); in tg3_reset_task()
11167 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11171 static int tg3_request_irq(struct tg3 *tp, int irq_num) in tg3_request_irq() argument
11176 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11178 if (tp->irq_cnt == 1) in tg3_request_irq()
11179 name = tp->dev->name; in tg3_request_irq()
11184 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11187 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11190 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11193 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11197 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_request_irq()
11199 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_request_irq()
11204 if (tg3_flag(tp, TAGGED_STATUS)) in tg3_request_irq()
11212 static int tg3_test_interrupt(struct tg3 *tp) in tg3_test_interrupt() argument
11214 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11215 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11222 tg3_disable_ints(tp); in tg3_test_interrupt()
11230 if (tg3_flag(tp, 57765_PLUS)) { in tg3_test_interrupt()
11241 tg3_enable_ints(tp); in tg3_test_interrupt()
11243 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11258 if (tg3_flag(tp, 57765_PLUS) && in tg3_test_interrupt()
11265 tg3_disable_ints(tp); in tg3_test_interrupt()
11269 err = tg3_request_irq(tp, 0); in tg3_test_interrupt()
11276 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { in tg3_test_interrupt()
11289 static int tg3_test_msi(struct tg3 *tp) in tg3_test_msi() argument
11294 if (!tg3_flag(tp, USING_MSI)) in tg3_test_msi()
11300 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11301 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11304 err = tg3_test_interrupt(tp); in tg3_test_msi()
11306 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11316 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11320 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11322 pci_disable_msi(tp->pdev); in tg3_test_msi()
11324 tg3_flag_clear(tp, USING_MSI); in tg3_test_msi()
11325 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11327 err = tg3_request_irq(tp, 0); in tg3_test_msi()
11334 tg3_full_lock(tp, 1); in tg3_test_msi()
11336 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_test_msi()
11337 err = tg3_init_hw(tp, true); in tg3_test_msi()
11339 tg3_full_unlock(tp); in tg3_test_msi()
11342 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11347 static int tg3_request_firmware(struct tg3 *tp) in tg3_request_firmware() argument
11351 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11352 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11353 tp->fw_needed); in tg3_request_firmware()
11357 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11364 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11365 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11366 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11367 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11368 release_firmware(tp->fw); in tg3_request_firmware()
11369 tp->fw = NULL; in tg3_request_firmware()
11374 tp->fw_needed = NULL; in tg3_request_firmware()
11378 static u32 tg3_irq_count(struct tg3 *tp) in tg3_irq_count() argument
11380 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11388 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11394 static bool tg3_enable_msix(struct tg3 *tp) in tg3_enable_msix() argument
11399 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11400 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11401 if (!tp->rxq_cnt) in tg3_enable_msix()
11402 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11403 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11404 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11410 if (!tp->txq_req) in tg3_enable_msix()
11411 tp->txq_cnt = 1; in tg3_enable_msix()
11413 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11415 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11420 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11423 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11424 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11425 tp->irq_cnt, rc); in tg3_enable_msix()
11426 tp->irq_cnt = rc; in tg3_enable_msix()
11427 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11428 if (tp->txq_cnt) in tg3_enable_msix()
11429 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11432 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11433 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11435 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11436 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11440 if (tp->irq_cnt == 1) in tg3_enable_msix()
11443 tg3_flag_set(tp, ENABLE_RSS); in tg3_enable_msix()
11445 if (tp->txq_cnt > 1) in tg3_enable_msix()
11446 tg3_flag_set(tp, ENABLE_TSS); in tg3_enable_msix()
11448 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11453 static void tg3_ints_init(struct tg3 *tp) in tg3_ints_init() argument
11455 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && in tg3_ints_init()
11456 !tg3_flag(tp, TAGGED_STATUS)) { in tg3_ints_init()
11460 netdev_warn(tp->dev, in tg3_ints_init()
11465 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) in tg3_ints_init()
11466 tg3_flag_set(tp, USING_MSIX); in tg3_ints_init()
11467 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11468 tg3_flag_set(tp, USING_MSI); in tg3_ints_init()
11470 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
11472 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11474 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_ints_init()
11479 if (!tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
11480 tp->irq_cnt = 1; in tg3_ints_init()
11481 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11484 if (tp->irq_cnt == 1) { in tg3_ints_init()
11485 tp->txq_cnt = 1; in tg3_ints_init()
11486 tp->rxq_cnt = 1; in tg3_ints_init()
11487 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11488 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11492 static void tg3_ints_fini(struct tg3 *tp) in tg3_ints_fini() argument
11494 if (tg3_flag(tp, USING_MSIX)) in tg3_ints_fini()
11495 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11496 else if (tg3_flag(tp, USING_MSI)) in tg3_ints_fini()
11497 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11498 tg3_flag_clear(tp, USING_MSI); in tg3_ints_fini()
11499 tg3_flag_clear(tp, USING_MSIX); in tg3_ints_fini()
11500 tg3_flag_clear(tp, ENABLE_RSS); in tg3_ints_fini()
11501 tg3_flag_clear(tp, ENABLE_TSS); in tg3_ints_fini()
11504 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq, in tg3_start() argument
11507 struct net_device *dev = tp->dev; in tg3_start()
11514 tg3_ints_init(tp); in tg3_start()
11516 tg3_rss_check_indir_tbl(tp); in tg3_start()
11521 err = tg3_alloc_consistent(tp); in tg3_start()
11525 tg3_napi_init(tp); in tg3_start()
11527 tg3_napi_enable(tp); in tg3_start()
11529 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11530 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11531 err = tg3_request_irq(tp, i); in tg3_start()
11534 tnapi = &tp->napi[i]; in tg3_start()
11541 tg3_full_lock(tp, 0); in tg3_start()
11544 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_start()
11546 err = tg3_init_hw(tp, reset_phy); in tg3_start()
11548 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_start()
11549 tg3_free_rings(tp); in tg3_start()
11552 tg3_full_unlock(tp); in tg3_start()
11557 if (test_irq && tg3_flag(tp, USING_MSI)) { in tg3_start()
11558 err = tg3_test_msi(tp); in tg3_start()
11561 tg3_full_lock(tp, 0); in tg3_start()
11562 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_start()
11563 tg3_free_rings(tp); in tg3_start()
11564 tg3_full_unlock(tp); in tg3_start()
11569 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { in tg3_start()
11577 tg3_phy_start(tp); in tg3_start()
11579 tg3_hwmon_open(tp); in tg3_start()
11581 tg3_full_lock(tp, 0); in tg3_start()
11583 tg3_timer_start(tp); in tg3_start()
11584 tg3_flag_set(tp, INIT_COMPLETE); in tg3_start()
11585 tg3_enable_ints(tp); in tg3_start()
11587 tg3_ptp_resume(tp); in tg3_start()
11589 tg3_full_unlock(tp); in tg3_start()
11603 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11604 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11609 tg3_napi_disable(tp); in tg3_start()
11610 tg3_napi_fini(tp); in tg3_start()
11611 tg3_free_consistent(tp); in tg3_start()
11614 tg3_ints_fini(tp); in tg3_start()
11619 static void tg3_stop(struct tg3 *tp) in tg3_stop() argument
11623 tg3_reset_task_cancel(tp); in tg3_stop()
11624 tg3_netif_stop(tp); in tg3_stop()
11626 tg3_timer_stop(tp); in tg3_stop()
11628 tg3_hwmon_close(tp); in tg3_stop()
11630 tg3_phy_stop(tp); in tg3_stop()
11632 tg3_full_lock(tp, 1); in tg3_stop()
11634 tg3_disable_ints(tp); in tg3_stop()
11636 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_stop()
11637 tg3_free_rings(tp); in tg3_stop()
11638 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_stop()
11640 tg3_full_unlock(tp); in tg3_stop()
11642 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11643 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11647 tg3_ints_fini(tp); in tg3_stop()
11649 tg3_napi_fini(tp); in tg3_stop()
11651 tg3_free_consistent(tp); in tg3_stop()
11656 struct tg3 *tp = netdev_priv(dev); in tg3_open() local
11659 if (tp->pcierr_recovery) { in tg3_open()
11665 if (tp->fw_needed) { in tg3_open()
11666 err = tg3_request_firmware(tp); in tg3_open()
11667 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_open()
11669 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11670 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11671 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11672 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11673 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11675 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { in tg3_open()
11679 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11680 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_open()
11681 } else if (!tg3_flag(tp, TSO_CAPABLE)) { in tg3_open()
11682 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11683 tg3_flag_set(tp, TSO_CAPABLE); in tg3_open()
11687 tg3_carrier_off(tp); in tg3_open()
11689 err = tg3_power_up(tp); in tg3_open()
11693 tg3_full_lock(tp, 0); in tg3_open()
11695 tg3_disable_ints(tp); in tg3_open()
11696 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_open()
11698 tg3_full_unlock(tp); in tg3_open()
11700 err = tg3_start(tp, in tg3_open()
11701 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11704 tg3_frob_aux_power(tp, false); in tg3_open()
11705 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11713 struct tg3 *tp = netdev_priv(dev); in tg3_close() local
11715 if (tp->pcierr_recovery) { in tg3_close()
11721 tg3_stop(tp); in tg3_close()
11724 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev)); in tg3_close()
11725 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev)); in tg3_close()
11727 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11728 tg3_power_down_prepare(tp); in tg3_close()
11730 tg3_carrier_off(tp); in tg3_close()
11740 static u64 tg3_calc_crc_errors(struct tg3 *tp) in tg3_calc_crc_errors() argument
11742 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11744 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11745 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_calc_crc_errors()
11746 tg3_asic_rev(tp) == ASIC_REV_5701)) { in tg3_calc_crc_errors()
11749 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { in tg3_calc_crc_errors()
11750 tg3_writephy(tp, MII_TG3_TEST1, in tg3_calc_crc_errors()
11752 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); in tg3_calc_crc_errors()
11756 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11758 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11768 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats) in tg3_get_estats() argument
11770 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11771 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
11852 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats) in tg3_get_nstats() argument
11854 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
11855 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
11897 tg3_calc_crc_errors(tp); in tg3_get_nstats()
11902 stats->rx_dropped = tp->rx_dropped; in tg3_get_nstats()
11903 stats->tx_dropped = tp->tx_dropped; in tg3_get_nstats()
11914 struct tg3 *tp = netdev_priv(dev); in tg3_get_regs() local
11920 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
11923 tg3_full_lock(tp, 0); in tg3_get_regs()
11925 tg3_dump_legacy_regs(tp, (u32 *)_p); in tg3_get_regs()
11927 tg3_full_unlock(tp); in tg3_get_regs()
11932 struct tg3 *tp = netdev_priv(dev); in tg3_get_eeprom_len() local
11934 return tp->nvram_size; in tg3_get_eeprom_len()
11939 struct tg3 *tp = netdev_priv(dev); in tg3_get_eeprom() local
11945 if (tg3_flag(tp, NO_NVRAM)) in tg3_get_eeprom()
11955 if (tg3_flag(tp, CPMU_PRESENT)) { in tg3_get_eeprom()
11965 tg3_override_clk(tp); in tg3_get_eeprom()
11975 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
11987 ret = tg3_nvram_read_be32(tp, offset + i, &val); in tg3_get_eeprom()
12011 ret = tg3_nvram_read_be32(tp, b_offset, &val); in tg3_get_eeprom()
12021 tg3_restore_clk(tp); in tg3_get_eeprom()
12030 struct tg3 *tp = netdev_priv(dev); in tg3_set_eeprom() local
12036 if (tg3_flag(tp, NO_NVRAM) || in tg3_set_eeprom()
12045 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12059 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12076 ret = tg3_nvram_write_block(tp, offset, len, buf); in tg3_set_eeprom()
12086 struct tg3 *tp = netdev_priv(dev); in tg3_get_settings() local
12088 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_get_settings()
12090 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_settings()
12092 phydev = tp->mdio_bus->phy_map[tp->phy_addr]; in tg3_get_settings()
12098 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_settings()
12102 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_settings()
12114 cmd->advertising = tp->link_config.advertising; in tg3_get_settings()
12115 if (tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_get_settings()
12116 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_settings()
12117 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_settings()
12123 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_settings()
12127 if (netif_running(dev) && tp->link_up) { in tg3_get_settings()
12128 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed); in tg3_get_settings()
12129 cmd->duplex = tp->link_config.active_duplex; in tg3_get_settings()
12130 cmd->lp_advertising = tp->link_config.rmt_adv; in tg3_get_settings()
12131 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_settings()
12132 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_settings()
12142 cmd->phy_address = tp->phy_addr; in tg3_get_settings()
12144 cmd->autoneg = tp->link_config.autoneg; in tg3_get_settings()
12152 struct tg3 *tp = netdev_priv(dev); in tg3_set_settings() local
12155 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_settings()
12157 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_settings()
12159 phydev = tp->mdio_bus->phy_map[tp->phy_addr]; in tg3_set_settings()
12177 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_settings()
12181 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_settings()
12202 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_settings()
12215 tg3_full_lock(tp, 0); in tg3_set_settings()
12217 tp->link_config.autoneg = cmd->autoneg; in tg3_set_settings()
12219 tp->link_config.advertising = (cmd->advertising | in tg3_set_settings()
12221 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_settings()
12222 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_settings()
12224 tp->link_config.advertising = 0; in tg3_set_settings()
12225 tp->link_config.speed = speed; in tg3_set_settings()
12226 tp->link_config.duplex = cmd->duplex; in tg3_set_settings()
12229 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_settings()
12231 tg3_warn_mgmt_link_flap(tp); in tg3_set_settings()
12234 tg3_setup_phy(tp, true); in tg3_set_settings()
12236 tg3_full_unlock(tp); in tg3_set_settings()
12243 struct tg3 *tp = netdev_priv(dev); in tg3_get_drvinfo() local
12247 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12248 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12253 struct tg3 *tp = netdev_priv(dev); in tg3_get_wol() local
12255 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12260 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12267 struct tg3 *tp = netdev_priv(dev); in tg3_set_wol() local
12268 struct device *dp = &tp->pdev->dev; in tg3_set_wol()
12273 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) in tg3_set_wol()
12279 tg3_flag_set(tp, WOL_ENABLE); in tg3_set_wol()
12281 tg3_flag_clear(tp, WOL_ENABLE); in tg3_set_wol()
12288 struct tg3 *tp = netdev_priv(dev); in tg3_get_msglevel() local
12289 return tp->msg_enable; in tg3_get_msglevel()
12294 struct tg3 *tp = netdev_priv(dev); in tg3_set_msglevel() local
12295 tp->msg_enable = value; in tg3_set_msglevel()
12300 struct tg3 *tp = netdev_priv(dev); in tg3_nway_reset() local
12306 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12309 tg3_warn_mgmt_link_flap(tp); in tg3_nway_reset()
12311 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_nway_reset()
12312 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12314 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]); in tg3_nway_reset()
12318 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12320 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_nway_reset()
12321 if (!tg3_readphy(tp, MII_BMCR, &bmcr) && in tg3_nway_reset()
12323 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12324 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | in tg3_nway_reset()
12328 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12336 struct tg3 *tp = netdev_priv(dev); in tg3_get_ringparam() local
12338 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12339 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
12340 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12346 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12347 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
12348 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12352 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12357 struct tg3 *tp = netdev_priv(dev); in tg3_set_ringparam() local
12360 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12361 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12364 (tg3_flag(tp, TSO_BUG) && in tg3_set_ringparam()
12369 tg3_phy_stop(tp); in tg3_set_ringparam()
12370 tg3_netif_stop(tp); in tg3_set_ringparam()
12374 tg3_full_lock(tp, irq_sync); in tg3_set_ringparam()
12376 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12378 if (tg3_flag(tp, MAX_RXPEND_64) && in tg3_set_ringparam()
12379 tp->rx_pending > 63) in tg3_set_ringparam()
12380 tp->rx_pending = 63; in tg3_set_ringparam()
12382 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_set_ringparam()
12383 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12385 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12386 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12389 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_set_ringparam()
12390 err = tg3_restart_hw(tp, false); in tg3_set_ringparam()
12392 tg3_netif_start(tp); in tg3_set_ringparam()
12395 tg3_full_unlock(tp); in tg3_set_ringparam()
12398 tg3_phy_start(tp); in tg3_set_ringparam()
12405 struct tg3 *tp = netdev_priv(dev); in tg3_get_pauseparam() local
12407 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12409 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12414 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12422 struct tg3 *tp = netdev_priv(dev); in tg3_set_pauseparam() local
12425 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12426 tg3_warn_mgmt_link_flap(tp); in tg3_set_pauseparam()
12428 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_pauseparam()
12432 phydev = tp->mdio_bus->phy_map[tp->phy_addr]; in tg3_set_pauseparam()
12439 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12441 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12444 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12450 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12456 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12458 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12460 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12482 tg3_setup_flow_control(tp, 0, 0); in tg3_set_pauseparam()
12484 tp->link_config.advertising &= in tg3_set_pauseparam()
12487 tp->link_config.advertising |= newadv; in tg3_set_pauseparam()
12493 tg3_netif_stop(tp); in tg3_set_pauseparam()
12497 tg3_full_lock(tp, irq_sync); in tg3_set_pauseparam()
12500 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12502 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12504 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12506 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12508 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12510 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12513 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_set_pauseparam()
12514 err = tg3_restart_hw(tp, false); in tg3_set_pauseparam()
12516 tg3_netif_start(tp); in tg3_set_pauseparam()
12519 tg3_full_unlock(tp); in tg3_set_pauseparam()
12522 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12542 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxnfc() local
12544 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxnfc()
12549 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12550 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12571 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxfh_indir_size() local
12573 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxfh_indir_size()
12581 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxfh() local
12590 indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12598 struct tg3 *tp = netdev_priv(dev); in tg3_set_rxfh() local
12612 tp->rss_ind_tbl[i] = indir[i]; in tg3_set_rxfh()
12614 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS)) in tg3_set_rxfh()
12620 tg3_full_lock(tp, 0); in tg3_set_rxfh()
12621 tg3_rss_write_indir_tbl(tp); in tg3_set_rxfh()
12622 tg3_full_unlock(tp); in tg3_set_rxfh()
12630 struct tg3 *tp = netdev_priv(dev); in tg3_get_channels() local
12633 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12634 channel->max_tx = tp->txq_max; in tg3_get_channels()
12637 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12638 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12640 if (tp->rxq_req) in tg3_get_channels()
12641 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12643 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12645 if (tp->txq_req) in tg3_get_channels()
12646 channel->tx_count = tp->txq_req; in tg3_get_channels()
12648 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12655 struct tg3 *tp = netdev_priv(dev); in tg3_set_channels() local
12657 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_set_channels()
12660 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12661 channel->tx_count > tp->txq_max) in tg3_set_channels()
12664 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12665 tp->txq_req = channel->tx_count; in tg3_set_channels()
12670 tg3_stop(tp); in tg3_set_channels()
12672 tg3_carrier_off(tp); in tg3_set_channels()
12674 tg3_start(tp, true, false, false); in tg3_set_channels()
12697 struct tg3 *tp = netdev_priv(dev); in tg3_set_phys_id() local
12699 if (!netif_running(tp->dev)) in tg3_set_phys_id()
12722 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12732 struct tg3 *tp = netdev_priv(dev); in tg3_get_ethtool_stats() local
12734 if (tp->hw_stats) in tg3_get_ethtool_stats()
12735 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats); in tg3_get_ethtool_stats()
12740 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen) in tg3_vpd_readblock() argument
12747 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) in tg3_vpd_readblock()
12754 if (tg3_nvram_read(tp, offset, &val)) in tg3_vpd_readblock()
12764 if (tg3_nvram_read(tp, offset + 4, &offset)) in tg3_vpd_readblock()
12767 offset = tg3_nvram_logical_addr(tp, offset); in tg3_vpd_readblock()
12786 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) in tg3_vpd_readblock()
12796 cnt = pci_read_vpd(tp->pdev, pos, in tg3_vpd_readblock()
12826 static int tg3_test_nvram(struct tg3 *tp) in tg3_test_nvram() argument
12832 if (tg3_flag(tp, NO_NVRAM)) in tg3_test_nvram()
12835 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_test_nvram()
12878 err = tg3_nvram_read_be32(tp, i, &buf[j]); in tg3_test_nvram()
12969 buf = tg3_vpd_readblock(tp, &len); in tg3_test_nvram()
13008 static int tg3_test_link(struct tg3 *tp) in tg3_test_link() argument
13012 if (!netif_running(tp->dev)) in tg3_test_link()
13015 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13021 if (tp->link_up) in tg3_test_link()
13032 static int tg3_test_registers(struct tg3 *tp) in tg3_test_registers() argument
13182 if (tg3_flag(tp, 5705_PLUS)) { in tg3_test_registers()
13184 if (tg3_flag(tp, 5750_PLUS)) in tg3_test_registers()
13195 if (tg3_flag(tp, IS_5788) && in tg3_test_registers()
13245 if (netif_msg_hw(tp)) in tg3_test_registers()
13246 netdev_err(tp->dev, in tg3_test_registers()
13252 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) in tg3_do_mem_test() argument
13262 tg3_write_mem(tp, offset + j, test_pattern[i]); in tg3_do_mem_test()
13263 tg3_read_mem(tp, offset + j, &val); in tg3_do_mem_test()
13271 static int tg3_test_memory(struct tg3 *tp) in tg3_test_memory() argument
13318 if (tg3_flag(tp, 5717_PLUS)) in tg3_test_memory()
13320 else if (tg3_flag(tp, 57765_CLASS) || in tg3_test_memory()
13321 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_test_memory()
13323 else if (tg3_flag(tp, 5755_PLUS)) in tg3_test_memory()
13325 else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_test_memory()
13327 else if (tg3_flag(tp, 5705_PLUS)) in tg3_test_memory()
13333 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); in tg3_test_memory()
13364 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) in tg3_run_loopback() argument
13375 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13377 tnapi = &tp->napi[0]; in tg3_run_loopback()
13378 rnapi = &tp->napi[0]; in tg3_run_loopback()
13379 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13380 if (tg3_flag(tp, ENABLE_RSS)) in tg3_run_loopback()
13381 rnapi = &tp->napi[1]; in tg3_run_loopback()
13382 if (tg3_flag(tp, ENABLE_TSS)) in tg3_run_loopback()
13383 tnapi = &tp->napi[1]; in tg3_run_loopback()
13390 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13395 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13419 if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
13420 tg3_flag(tp, HW_TSO_2) || in tg3_run_loopback()
13421 tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
13429 if (tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
13434 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_run_loopback()
13436 else if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
13437 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_run_loopback()
13448 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in tg3_run_loopback()
13456 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); in tg3_run_loopback()
13457 if (pci_dma_mapping_error(tp->pdev, map)) { in tg3_run_loopback()
13466 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13493 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13555 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, in tg3_run_loopback()
13558 rx_data += TG3_RX_OFFSET(tp); in tg3_run_loopback()
13580 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) in tg3_test_loopback() argument
13586 if (tp->dma_limit) in tg3_test_loopback()
13587 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13589 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13590 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13592 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13600 err = tg3_reset_hw(tp, true); in tg3_test_loopback()
13609 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_test_loopback()
13623 if (tg3_asic_rev(tp) != ASIC_REV_5780 && in tg3_test_loopback()
13624 !tg3_flag(tp, CPMU_PRESENT)) { in tg3_test_loopback()
13625 tg3_mac_loopback(tp, true); in tg3_test_loopback()
13627 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13630 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13631 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13634 tg3_mac_loopback(tp, false); in tg3_test_loopback()
13637 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13638 !tg3_flag(tp, USE_PHYLIB)) { in tg3_test_loopback()
13641 tg3_phy_lpbk_set(tp, 0, false); in tg3_test_loopback()
13650 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13652 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
13653 tg3_run_loopback(tp, ETH_FRAME_LEN, true)) in tg3_test_loopback()
13655 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13656 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13660 tg3_phy_lpbk_set(tp, 0, true); in tg3_test_loopback()
13668 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13671 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
13672 tg3_run_loopback(tp, ETH_FRAME_LEN, true)) in tg3_test_loopback()
13675 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13676 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13682 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13683 tg3_phy_toggle_apd(tp, true); in tg3_test_loopback()
13690 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13698 struct tg3 *tp = netdev_priv(dev); in tg3_self_test() local
13701 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13702 if (tg3_power_up(tp)) { in tg3_self_test()
13707 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_self_test()
13712 if (tg3_test_nvram(tp) != 0) { in tg3_self_test()
13716 if (!doextlpbk && tg3_test_link(tp)) { in tg3_self_test()
13724 tg3_phy_stop(tp); in tg3_self_test()
13725 tg3_netif_stop(tp); in tg3_self_test()
13729 tg3_full_lock(tp, irq_sync); in tg3_self_test()
13730 tg3_halt(tp, RESET_KIND_SUSPEND, 1); in tg3_self_test()
13731 err = tg3_nvram_lock(tp); in tg3_self_test()
13732 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_self_test()
13733 if (!tg3_flag(tp, 5705_PLUS)) in tg3_self_test()
13734 tg3_halt_cpu(tp, TX_CPU_BASE); in tg3_self_test()
13736 tg3_nvram_unlock(tp); in tg3_self_test()
13738 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13739 tg3_phy_reset(tp); in tg3_self_test()
13741 if (tg3_test_registers(tp) != 0) { in tg3_self_test()
13746 if (tg3_test_memory(tp) != 0) { in tg3_self_test()
13754 if (tg3_test_loopback(tp, data, doextlpbk)) in tg3_self_test()
13757 tg3_full_unlock(tp); in tg3_self_test()
13759 if (tg3_test_interrupt(tp) != 0) { in tg3_self_test()
13764 tg3_full_lock(tp, 0); in tg3_self_test()
13766 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_self_test()
13768 tg3_flag_set(tp, INIT_COMPLETE); in tg3_self_test()
13769 err2 = tg3_restart_hw(tp, true); in tg3_self_test()
13771 tg3_netif_start(tp); in tg3_self_test()
13774 tg3_full_unlock(tp); in tg3_self_test()
13777 tg3_phy_start(tp); in tg3_self_test()
13779 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13780 tg3_power_down_prepare(tp); in tg3_self_test()
13786 struct tg3 *tp = netdev_priv(dev); in tg3_hwtstamp_set() local
13789 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_hwtstamp_set()
13804 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13807 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13811 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13815 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13819 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13823 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13827 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13831 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13835 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13839 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13843 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13847 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13851 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13858 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
13860 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
13863 tg3_flag_set(tp, TX_TSTAMP_EN); in tg3_hwtstamp_set()
13865 tg3_flag_clear(tp, TX_TSTAMP_EN); in tg3_hwtstamp_set()
13873 struct tg3 *tp = netdev_priv(dev); in tg3_hwtstamp_get() local
13876 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_hwtstamp_get()
13880 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ? in tg3_hwtstamp_get()
13883 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
13935 struct tg3 *tp = netdev_priv(dev); in tg3_ioctl() local
13938 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_ioctl()
13940 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
13942 phydev = tp->mdio_bus->phy_map[tp->phy_addr]; in tg3_ioctl()
13948 data->phy_id = tp->phy_addr; in tg3_ioctl()
13954 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
13960 spin_lock_bh(&tp->lock); in tg3_ioctl()
13961 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
13963 spin_unlock_bh(&tp->lock); in tg3_ioctl()
13971 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
13977 spin_lock_bh(&tp->lock); in tg3_ioctl()
13978 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
13980 spin_unlock_bh(&tp->lock); in tg3_ioctl()
13999 struct tg3 *tp = netdev_priv(dev); in tg3_get_coalesce() local
14001 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14007 struct tg3 *tp = netdev_priv(dev); in tg3_set_coalesce() local
14011 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_set_coalesce()
14041 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14042 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14043 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14044 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14045 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14046 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14047 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14048 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14049 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14052 tg3_full_lock(tp, 0); in tg3_set_coalesce()
14053 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14054 tg3_full_unlock(tp); in tg3_set_coalesce()
14061 struct tg3 *tp = netdev_priv(dev); in tg3_set_eee() local
14063 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14064 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14068 if (edata->advertised != tp->eee.advertised) { in tg3_set_eee()
14069 netdev_warn(tp->dev, in tg3_set_eee()
14075 netdev_warn(tp->dev, in tg3_set_eee()
14081 tp->eee = *edata; in tg3_set_eee()
14083 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14084 tg3_warn_mgmt_link_flap(tp); in tg3_set_eee()
14086 if (netif_running(tp->dev)) { in tg3_set_eee()
14087 tg3_full_lock(tp, 0); in tg3_set_eee()
14088 tg3_setup_eee(tp); in tg3_set_eee()
14089 tg3_phy_reset(tp); in tg3_set_eee()
14090 tg3_full_unlock(tp); in tg3_set_eee()
14098 struct tg3 *tp = netdev_priv(dev); in tg3_get_eee() local
14100 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14101 netdev_warn(tp->dev, in tg3_get_eee()
14106 *edata = tp->eee; in tg3_get_eee()
14150 struct tg3 *tp = netdev_priv(dev); in tg3_get_stats64() local
14152 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14153 if (!tp->hw_stats) { in tg3_get_stats64()
14154 *stats = tp->net_stats_prev; in tg3_get_stats64()
14155 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14159 tg3_get_nstats(tp, stats); in tg3_get_stats64()
14160 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14167 struct tg3 *tp = netdev_priv(dev); in tg3_set_rx_mode() local
14172 tg3_full_lock(tp, 0); in tg3_set_rx_mode()
14174 tg3_full_unlock(tp); in tg3_set_rx_mode()
14177 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, in tg3_set_mtu() argument
14183 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
14185 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_set_mtu()
14187 tg3_flag_set(tp, JUMBO_RING_ENABLE); in tg3_set_mtu()
14190 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
14191 tg3_flag_set(tp, TSO_CAPABLE); in tg3_set_mtu()
14194 tg3_flag_clear(tp, JUMBO_RING_ENABLE); in tg3_set_mtu()
14200 struct tg3 *tp = netdev_priv(dev); in tg3_change_mtu() local
14204 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) in tg3_change_mtu()
14211 tg3_set_mtu(dev, tp, new_mtu); in tg3_change_mtu()
14215 tg3_phy_stop(tp); in tg3_change_mtu()
14217 tg3_netif_stop(tp); in tg3_change_mtu()
14219 tg3_set_mtu(dev, tp, new_mtu); in tg3_change_mtu()
14221 tg3_full_lock(tp, 1); in tg3_change_mtu()
14223 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_change_mtu()
14228 if (tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_change_mtu()
14231 err = tg3_restart_hw(tp, reset_phy); in tg3_change_mtu()
14234 tg3_netif_start(tp); in tg3_change_mtu()
14236 tg3_full_unlock(tp); in tg3_change_mtu()
14239 tg3_phy_start(tp); in tg3_change_mtu()
14262 static void tg3_get_eeprom_size(struct tg3 *tp) in tg3_get_eeprom_size() argument
14266 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14268 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_get_eeprom_size()
14283 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14284 if (tg3_nvram_read(tp, cursize, &val) != 0) in tg3_get_eeprom_size()
14293 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14296 static void tg3_get_nvram_size(struct tg3 *tp) in tg3_get_nvram_size() argument
14300 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) in tg3_get_nvram_size()
14305 tg3_get_eeprom_size(tp); in tg3_get_nvram_size()
14309 if (tg3_nvram_read(tp, 0xf0, &val) == 0) { in tg3_get_nvram_size()
14322 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14326 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14329 static void tg3_get_nvram_info(struct tg3 *tp) in tg3_get_nvram_info() argument
14335 tg3_flag_set(tp, FLASH); in tg3_get_nvram_info()
14341 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_get_nvram_info()
14342 tg3_flag(tp, 5780_CLASS)) { in tg3_get_nvram_info()
14345 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14346 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14347 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14350 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14351 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14354 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14355 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14356 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14359 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14360 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14361 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14364 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14365 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14369 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14370 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14374 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14375 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14376 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14380 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) in tg3_nvram_get_pagesize() argument
14384 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14387 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14390 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14393 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14396 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14399 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14402 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14407 static void tg3_get_5752_nvram_info(struct tg3 *tp) in tg3_get_5752_nvram_info() argument
14415 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5752_nvram_info()
14420 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14421 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14424 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14425 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14426 tg3_flag_set(tp, FLASH); in tg3_get_5752_nvram_info()
14431 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14432 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14433 tg3_flag_set(tp, FLASH); in tg3_get_5752_nvram_info()
14437 if (tg3_flag(tp, FLASH)) { in tg3_get_5752_nvram_info()
14438 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5752_nvram_info()
14441 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14448 static void tg3_get_5755_nvram_info(struct tg3 *tp) in tg3_get_5755_nvram_info() argument
14456 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5755_nvram_info()
14466 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14467 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5755_nvram_info()
14468 tg3_flag_set(tp, FLASH); in tg3_get_5755_nvram_info()
14469 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14472 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14475 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14478 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14484 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14485 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5755_nvram_info()
14486 tg3_flag_set(tp, FLASH); in tg3_get_5755_nvram_info()
14487 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14489 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14493 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14497 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14504 static void tg3_get_5787_nvram_info(struct tg3 *tp) in tg3_get_5787_nvram_info() argument
14515 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14516 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14517 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14526 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14527 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14528 tg3_flag_set(tp, FLASH); in tg3_get_5787_nvram_info()
14529 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14534 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14535 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14536 tg3_flag_set(tp, FLASH); in tg3_get_5787_nvram_info()
14537 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14542 static void tg3_get_5761_nvram_info(struct tg3 *tp) in tg3_get_5761_nvram_info() argument
14550 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5761_nvram_info()
14564 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14565 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5761_nvram_info()
14566 tg3_flag_set(tp, FLASH); in tg3_get_5761_nvram_info()
14567 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5761_nvram_info()
14568 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14578 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14579 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5761_nvram_info()
14580 tg3_flag_set(tp, FLASH); in tg3_get_5761_nvram_info()
14581 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14586 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14593 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14599 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14605 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14611 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14617 static void tg3_get_5906_nvram_info(struct tg3 *tp) in tg3_get_5906_nvram_info() argument
14619 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14620 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5906_nvram_info()
14621 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14624 static void tg3_get_57780_nvram_info(struct tg3 *tp) in tg3_get_57780_nvram_info() argument
14633 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14634 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14635 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14647 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14648 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14649 tg3_flag_set(tp, FLASH); in tg3_get_57780_nvram_info()
14655 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14659 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14663 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14670 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14671 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14672 tg3_flag_set(tp, FLASH); in tg3_get_57780_nvram_info()
14676 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14679 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14682 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14687 tg3_flag_set(tp, NO_NVRAM); in tg3_get_57780_nvram_info()
14691 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_57780_nvram_info()
14692 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14693 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_57780_nvram_info()
14697 static void tg3_get_5717_nvram_info(struct tg3 *tp) in tg3_get_5717_nvram_info() argument
14706 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14707 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14708 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14720 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14721 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14722 tg3_flag_set(tp, FLASH); in tg3_get_5717_nvram_info()
14730 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14733 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14747 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14748 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14749 tg3_flag_set(tp, FLASH); in tg3_get_5717_nvram_info()
14758 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14761 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14766 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5717_nvram_info()
14770 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5717_nvram_info()
14771 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14772 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5717_nvram_info()
14775 static void tg3_get_5720_nvram_info(struct tg3 *tp) in tg3_get_5720_nvram_info() argument
14782 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_get_5720_nvram_info()
14784 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14807 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14808 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14813 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14815 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14829 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14830 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14831 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14837 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14842 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14846 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14849 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_get_5720_nvram_info()
14850 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14872 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
14873 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14874 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14881 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14887 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14893 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14896 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_get_5720_nvram_info()
14897 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14902 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14906 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5720_nvram_info()
14907 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
14908 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5720_nvram_info()
14910 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_get_5720_nvram_info()
14913 if (tg3_nvram_read(tp, 0, &val)) in tg3_get_5720_nvram_info()
14918 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14923 static void tg3_nvram_init(struct tg3 *tp) in tg3_nvram_init() argument
14925 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_nvram_init()
14927 tg3_flag_clear(tp, NVRAM); in tg3_nvram_init()
14928 tg3_flag_clear(tp, NVRAM_BUFFERED); in tg3_nvram_init()
14929 tg3_flag_set(tp, NO_NVRAM); in tg3_nvram_init()
14945 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_nvram_init()
14946 tg3_asic_rev(tp) != ASIC_REV_5701) { in tg3_nvram_init()
14947 tg3_flag_set(tp, NVRAM); in tg3_nvram_init()
14949 if (tg3_nvram_lock(tp)) { in tg3_nvram_init()
14950 netdev_warn(tp->dev, in tg3_nvram_init()
14955 tg3_enable_nvram_access(tp); in tg3_nvram_init()
14957 tp->nvram_size = 0; in tg3_nvram_init()
14959 if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_nvram_init()
14960 tg3_get_5752_nvram_info(tp); in tg3_nvram_init()
14961 else if (tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_nvram_init()
14962 tg3_get_5755_nvram_info(tp); in tg3_nvram_init()
14963 else if (tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_nvram_init()
14964 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_nvram_init()
14965 tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_nvram_init()
14966 tg3_get_5787_nvram_info(tp); in tg3_nvram_init()
14967 else if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_nvram_init()
14968 tg3_get_5761_nvram_info(tp); in tg3_nvram_init()
14969 else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_nvram_init()
14970 tg3_get_5906_nvram_info(tp); in tg3_nvram_init()
14971 else if (tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_nvram_init()
14972 tg3_flag(tp, 57765_CLASS)) in tg3_nvram_init()
14973 tg3_get_57780_nvram_info(tp); in tg3_nvram_init()
14974 else if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_nvram_init()
14975 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_nvram_init()
14976 tg3_get_5717_nvram_info(tp); in tg3_nvram_init()
14977 else if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_nvram_init()
14978 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_nvram_init()
14979 tg3_get_5720_nvram_info(tp); in tg3_nvram_init()
14981 tg3_get_nvram_info(tp); in tg3_nvram_init()
14983 if (tp->nvram_size == 0) in tg3_nvram_init()
14984 tg3_get_nvram_size(tp); in tg3_nvram_init()
14986 tg3_disable_nvram_access(tp); in tg3_nvram_init()
14987 tg3_nvram_unlock(tp); in tg3_nvram_init()
14990 tg3_flag_clear(tp, NVRAM); in tg3_nvram_init()
14991 tg3_flag_clear(tp, NVRAM_BUFFERED); in tg3_nvram_init()
14993 tg3_get_eeprom_size(tp); in tg3_nvram_init()
15066 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp) in tg3_lookup_by_subsys() argument
15072 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15074 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15080 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) in tg3_get_eeprom_hw_cfg() argument
15084 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15085 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15088 tg3_flag_set(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15089 tg3_flag_set(tp, WOL_CAP); in tg3_get_eeprom_hw_cfg()
15091 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_eeprom_hw_cfg()
15093 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15094 tg3_flag_set(tp, IS_NIC); in tg3_get_eeprom_hw_cfg()
15098 tg3_flag_set(tp, ASPM_WORKAROUND); in tg3_get_eeprom_hw_cfg()
15101 tg3_flag_set(tp, WOL_ENABLE); in tg3_get_eeprom_hw_cfg()
15102 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15107 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); in tg3_get_eeprom_hw_cfg()
15114 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); in tg3_get_eeprom_hw_cfg()
15115 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15117 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); in tg3_get_eeprom_hw_cfg()
15119 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_get_eeprom_hw_cfg()
15120 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_get_eeprom_hw_cfg()
15121 tg3_asic_rev(tp) != ASIC_REV_5703 && in tg3_get_eeprom_hw_cfg()
15123 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); in tg3_get_eeprom_hw_cfg()
15125 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_get_eeprom_hw_cfg()
15126 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); in tg3_get_eeprom_hw_cfg()
15128 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_eeprom_hw_cfg()
15129 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_eeprom_hw_cfg()
15130 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_get_eeprom_hw_cfg()
15131 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5); in tg3_get_eeprom_hw_cfg()
15137 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); in tg3_get_eeprom_hw_cfg()
15148 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15150 if (!tg3_flag(tp, 5705_PLUS)) in tg3_get_eeprom_hw_cfg()
15151 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15153 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15156 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15165 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15169 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15173 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15178 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
15179 tg3_asic_rev(tp) == ASIC_REV_5701) in tg3_get_eeprom_hw_cfg()
15180 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15185 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15186 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && in tg3_get_eeprom_hw_cfg()
15187 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1) in tg3_get_eeprom_hw_cfg()
15188 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15191 if (tg3_flag(tp, 5717_PLUS) || in tg3_get_eeprom_hw_cfg()
15192 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_eeprom_hw_cfg()
15193 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15199 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15203 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15204 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) in tg3_get_eeprom_hw_cfg()
15205 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15211 if ((tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
15212 tg3_asic_rev(tp) == ASIC_REV_5701) && in tg3_get_eeprom_hw_cfg()
15213 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15214 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15216 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) in tg3_get_eeprom_hw_cfg()
15217 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15220 tg3_flag_set(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15221 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15223 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15224 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15225 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15227 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15228 tg3_flag_set(tp, IS_NIC); in tg3_get_eeprom_hw_cfg()
15232 tg3_flag_set(tp, ENABLE_ASF); in tg3_get_eeprom_hw_cfg()
15233 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15234 tg3_flag_set(tp, ASF_NEW_HANDSHAKE); in tg3_get_eeprom_hw_cfg()
15238 tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15239 tg3_flag_set(tp, ENABLE_APE); in tg3_get_eeprom_hw_cfg()
15241 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15243 tg3_flag_clear(tp, WOL_CAP); in tg3_get_eeprom_hw_cfg()
15245 if (tg3_flag(tp, WOL_CAP) && in tg3_get_eeprom_hw_cfg()
15247 tg3_flag_set(tp, WOL_ENABLE); in tg3_get_eeprom_hw_cfg()
15248 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15252 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15257 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15259 if ((tg3_flag(tp, 57765_PLUS) || in tg3_get_eeprom_hw_cfg()
15260 (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_get_eeprom_hw_cfg()
15261 tg3_chip_rev(tp) != CHIPREV_5784_AX)) && in tg3_get_eeprom_hw_cfg()
15263 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15265 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_get_eeprom_hw_cfg()
15268 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); in tg3_get_eeprom_hw_cfg()
15269 if (tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_get_eeprom_hw_cfg()
15270 !tg3_flag(tp, 57765_PLUS) && in tg3_get_eeprom_hw_cfg()
15272 tg3_flag_set(tp, ASPM_WORKAROUND); in tg3_get_eeprom_hw_cfg()
15274 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15276 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15280 tg3_flag_set(tp, RGMII_INBAND_DISABLE); in tg3_get_eeprom_hw_cfg()
15282 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); in tg3_get_eeprom_hw_cfg()
15284 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); in tg3_get_eeprom_hw_cfg()
15287 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15290 if (tg3_flag(tp, WOL_CAP)) in tg3_get_eeprom_hw_cfg()
15291 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15292 tg3_flag(tp, WOL_ENABLE)); in tg3_get_eeprom_hw_cfg()
15294 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15297 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val) in tg3_ape_otp_read() argument
15302 err = tg3_nvram_lock(tp); in tg3_ape_otp_read()
15306 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE); in tg3_ape_otp_read()
15307 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN | in tg3_ape_otp_read()
15309 tg3_ape_read32(tp, TG3_APE_OTP_CTRL); in tg3_ape_otp_read()
15313 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS); in tg3_ape_otp_read()
15315 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA); in tg3_ape_otp_read()
15321 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0); in tg3_ape_otp_read()
15323 tg3_nvram_unlock(tp); in tg3_ape_otp_read()
15330 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd) in tg3_issue_otp_command() argument
15353 static u32 tg3_read_otp_phycfg(struct tg3 *tp) in tg3_read_otp_phycfg() argument
15359 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) in tg3_read_otp_phycfg()
15364 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
15371 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
15379 static void tg3_phy_init_link_config(struct tg3 *tp) in tg3_phy_init_link_config() argument
15383 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15384 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15389 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15398 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15399 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15400 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15401 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15402 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15403 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15405 tp->old_link = -1; in tg3_phy_init_link_config()
15408 static int tg3_phy_probe(struct tg3 *tp) in tg3_phy_probe() argument
15415 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_phy_probe()
15416 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15418 if (tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
15419 switch (tp->pci_fn) { in tg3_phy_probe()
15421 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15424 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15427 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15430 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15435 if (!tg3_flag(tp, ENABLE_ASF) && in tg3_phy_probe()
15436 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15437 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15438 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15441 if (tg3_flag(tp, USE_PHYLIB)) in tg3_phy_probe()
15442 return tg3_phy_init(tp); in tg3_phy_probe()
15448 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
15456 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); in tg3_phy_probe()
15457 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); in tg3_phy_probe()
15467 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15469 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15471 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15473 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15483 p = tg3_lookup_by_subsys(tp); in tg3_phy_probe()
15485 tp->phy_id = p->phy_id; in tg3_phy_probe()
15486 } else if (!tg3_flag(tp, IS_SSB_CORE)) { in tg3_phy_probe()
15497 if (!tp->phy_id || in tg3_phy_probe()
15498 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15499 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15503 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15504 (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_phy_probe()
15505 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_phy_probe()
15506 tg3_asic_rev(tp) == ASIC_REV_57766 || in tg3_phy_probe()
15507 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_phy_probe()
15508 (tg3_asic_rev(tp) == ASIC_REV_5717 && in tg3_phy_probe()
15509 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) || in tg3_phy_probe()
15510 (tg3_asic_rev(tp) == ASIC_REV_57765 && in tg3_phy_probe()
15511 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) { in tg3_phy_probe()
15512 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15514 tp->eee.supported = SUPPORTED_100baseT_Full | in tg3_phy_probe()
15516 tp->eee.advertised = ADVERTISED_100baseT_Full | in tg3_phy_probe()
15518 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15519 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15520 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15523 tg3_phy_init_link_config(tp); in tg3_phy_probe()
15525 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15526 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15527 !tg3_flag(tp, ENABLE_APE) && in tg3_phy_probe()
15528 !tg3_flag(tp, ENABLE_ASF)) { in tg3_phy_probe()
15531 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_phy_probe()
15532 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_phy_probe()
15536 err = tg3_phy_reset(tp); in tg3_phy_probe()
15540 tg3_phy_set_wirespeed(tp); in tg3_phy_probe()
15542 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) { in tg3_phy_probe()
15543 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15544 tp->link_config.flowctrl); in tg3_phy_probe()
15546 tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()
15552 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15553 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
15557 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
15563 static void tg3_read_vpd(struct tg3 *tp) in tg3_read_vpd() argument
15570 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); in tg3_read_vpd()
15606 if (len >= sizeof(tp->fw_ver)) in tg3_read_vpd()
15607 len = sizeof(tp->fw_ver) - 1; in tg3_read_vpd()
15608 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15609 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, in tg3_read_vpd()
15626 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15630 if (tp->board_part_number[0]) in tg3_read_vpd()
15634 if (tg3_asic_rev(tp) == ASIC_REV_5717) { in tg3_read_vpd()
15635 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15636 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15637 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15638 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15639 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15642 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_read_vpd()
15643 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15644 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15645 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15646 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15647 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15648 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15649 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15650 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15653 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) { in tg3_read_vpd()
15654 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15655 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15656 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15657 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15658 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15659 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15660 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15661 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15662 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15663 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15664 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15665 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15668 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_read_vpd()
15669 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15670 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15671 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15672 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15673 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15674 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15675 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15676 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15679 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_read_vpd()
15680 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15683 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15687 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) in tg3_fw_img_is_valid() argument
15691 if (tg3_nvram_read(tp, offset, &val) || in tg3_fw_img_is_valid()
15693 tg3_nvram_read(tp, offset + 4, &val) || in tg3_fw_img_is_valid()
15700 static void tg3_read_bc_ver(struct tg3 *tp) in tg3_read_bc_ver() argument
15706 if (tg3_nvram_read(tp, 0xc, &offset) || in tg3_read_bc_ver()
15707 tg3_nvram_read(tp, 0x4, &start)) in tg3_read_bc_ver()
15710 offset = tg3_nvram_logical_addr(tp, offset); in tg3_read_bc_ver()
15712 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_bc_ver()
15716 if (tg3_nvram_read(tp, offset + 4, &val)) in tg3_read_bc_ver()
15723 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15727 tg3_nvram_read(tp, offset + 8, &ver_offset)) in tg3_read_bc_ver()
15733 if (tg3_nvram_read_be32(tp, offset + i, &v)) in tg3_read_bc_ver()
15736 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15741 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) in tg3_read_bc_ver()
15747 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15752 static void tg3_read_hwsb_ver(struct tg3 *tp) in tg3_read_hwsb_ver() argument
15757 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) in tg3_read_hwsb_ver()
15765 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15768 static void tg3_read_sb_ver(struct tg3 *tp, u32 val) in tg3_read_sb_ver() argument
15772 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15800 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_sb_ver()
15812 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15813 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15817 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15819 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15823 static void tg3_read_mgmtfw_ver(struct tg3 *tp) in tg3_read_mgmtfw_ver() argument
15831 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_mgmtfw_ver()
15841 if (!tg3_flag(tp, 5705_PLUS)) in tg3_read_mgmtfw_ver()
15843 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15846 if (tg3_nvram_read(tp, offset + 4, &offset) || in tg3_read_mgmtfw_ver()
15847 !tg3_fw_img_is_valid(tp, offset) || in tg3_read_mgmtfw_ver()
15848 tg3_nvram_read(tp, offset + 8, &val)) in tg3_read_mgmtfw_ver()
15853 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15855 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15856 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
15860 if (tg3_nvram_read_be32(tp, offset, &v)) in tg3_read_mgmtfw_ver()
15866 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
15870 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
15875 static void tg3_probe_ncsi(struct tg3 *tp) in tg3_probe_ncsi() argument
15879 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_probe_ncsi()
15883 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_probe_ncsi()
15887 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) in tg3_probe_ncsi()
15888 tg3_flag_set(tp, APE_HAS_NCSI); in tg3_probe_ncsi()
15891 static void tg3_read_dash_ver(struct tg3 *tp) in tg3_read_dash_ver() argument
15897 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); in tg3_read_dash_ver()
15899 if (tg3_flag(tp, APE_HAS_NCSI)) in tg3_read_dash_ver()
15901 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
15906 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
15908 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
15916 static void tg3_read_otp_ver(struct tg3 *tp) in tg3_read_otp_ver() argument
15920 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_read_otp_ver()
15923 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) && in tg3_read_otp_ver()
15924 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) && in tg3_read_otp_ver()
15936 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
15937 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
15941 static void tg3_read_fw_ver(struct tg3 *tp) in tg3_read_fw_ver() argument
15946 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
15949 if (tg3_flag(tp, NO_NVRAM)) { in tg3_read_fw_ver()
15950 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
15951 tg3_read_otp_ver(tp); in tg3_read_fw_ver()
15955 if (tg3_nvram_read(tp, 0, &val)) in tg3_read_fw_ver()
15959 tg3_read_bc_ver(tp); in tg3_read_fw_ver()
15961 tg3_read_sb_ver(tp, val); in tg3_read_fw_ver()
15963 tg3_read_hwsb_ver(tp); in tg3_read_fw_ver()
15965 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_read_fw_ver()
15966 if (tg3_flag(tp, ENABLE_APE)) { in tg3_read_fw_ver()
15967 tg3_probe_ncsi(tp); in tg3_read_fw_ver()
15969 tg3_read_dash_ver(tp); in tg3_read_fw_ver()
15971 tg3_read_mgmtfw_ver(tp); in tg3_read_fw_ver()
15975 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
15978 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) in tg3_rx_ret_ring_size() argument
15980 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_rx_ret_ring_size()
15982 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) in tg3_rx_ret_ring_size()
15995 static struct pci_dev *tg3_find_peer(struct tg3 *tp) in tg3_find_peer() argument
15998 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16001 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16002 if (peer && peer != tp->pdev) in tg3_find_peer()
16010 peer = tp->pdev; in tg3_find_peer()
16023 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) in tg3_detect_asic_rev() argument
16025 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16026 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) { in tg3_detect_asic_rev()
16032 tg3_flag_set(tp, CPMU_PRESENT); in tg3_detect_asic_rev()
16034 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16035 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16036 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16037 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16038 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16039 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16040 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16041 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16042 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16043 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16044 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16046 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16047 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16048 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16049 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16050 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16051 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16052 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16053 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16054 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16055 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16060 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16066 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW) in tg3_detect_asic_rev()
16067 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16069 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0) in tg3_detect_asic_rev()
16070 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16072 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_detect_asic_rev()
16073 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_detect_asic_rev()
16074 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_detect_asic_rev()
16075 tg3_flag_set(tp, 5717_PLUS); in tg3_detect_asic_rev()
16077 if (tg3_asic_rev(tp) == ASIC_REV_57765 || in tg3_detect_asic_rev()
16078 tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_detect_asic_rev()
16079 tg3_flag_set(tp, 57765_CLASS); in tg3_detect_asic_rev()
16081 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) || in tg3_detect_asic_rev()
16082 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_detect_asic_rev()
16083 tg3_flag_set(tp, 57765_PLUS); in tg3_detect_asic_rev()
16086 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_detect_asic_rev()
16087 tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_detect_asic_rev()
16088 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_detect_asic_rev()
16089 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_detect_asic_rev()
16090 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_detect_asic_rev()
16091 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_detect_asic_rev()
16092 tg3_flag(tp, 57765_PLUS)) in tg3_detect_asic_rev()
16093 tg3_flag_set(tp, 5755_PLUS); in tg3_detect_asic_rev()
16095 if (tg3_asic_rev(tp) == ASIC_REV_5780 || in tg3_detect_asic_rev()
16096 tg3_asic_rev(tp) == ASIC_REV_5714) in tg3_detect_asic_rev()
16097 tg3_flag_set(tp, 5780_CLASS); in tg3_detect_asic_rev()
16099 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_detect_asic_rev()
16100 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_detect_asic_rev()
16101 tg3_asic_rev(tp) == ASIC_REV_5906 || in tg3_detect_asic_rev()
16102 tg3_flag(tp, 5755_PLUS) || in tg3_detect_asic_rev()
16103 tg3_flag(tp, 5780_CLASS)) in tg3_detect_asic_rev()
16104 tg3_flag_set(tp, 5750_PLUS); in tg3_detect_asic_rev()
16106 if (tg3_asic_rev(tp) == ASIC_REV_5705 || in tg3_detect_asic_rev()
16107 tg3_flag(tp, 5750_PLUS)) in tg3_detect_asic_rev()
16108 tg3_flag_set(tp, 5705_PLUS); in tg3_detect_asic_rev()
16111 static bool tg3_10_100_only_device(struct tg3 *tp, in tg3_10_100_only_device() argument
16116 if ((tg3_asic_rev(tp) == ASIC_REV_5703 && in tg3_10_100_only_device()
16118 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16122 if (tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_10_100_only_device()
16133 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) in tg3_get_invariants() argument
16148 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16150 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16157 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16159 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16161 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16162 tp->misc_host_ctrl); in tg3_get_invariants()
16164 tg3_detect_asic_rev(tp, misc_ctrl_reg); in tg3_get_invariants()
16183 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) || in tg3_get_invariants()
16184 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) { in tg3_get_invariants()
16216 tp->pdev->bus->number)) { in tg3_get_invariants()
16217 tg3_flag_set(tp, ICH_WORKAROUND); in tg3_get_invariants()
16224 if (tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_get_invariants()
16246 tp->pdev->bus->number) && in tg3_get_invariants()
16248 tp->pdev->bus->number)) { in tg3_get_invariants()
16249 tg3_flag_set(tp, 5701_DMA_BUG); in tg3_get_invariants()
16262 if (tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16263 tg3_flag_set(tp, 40BIT_DMA_BUG); in tg3_get_invariants()
16264 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16274 tp->pdev->bus->number) && in tg3_get_invariants()
16276 tp->pdev->bus->number)) { in tg3_get_invariants()
16277 tg3_flag_set(tp, 40BIT_DMA_BUG); in tg3_get_invariants()
16284 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_invariants()
16285 tg3_asic_rev(tp) == ASIC_REV_5714) in tg3_get_invariants()
16286 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16289 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0) in tg3_get_invariants()
16291 else if (tg3_flag(tp, 57765_PLUS)) in tg3_get_invariants()
16292 tg3_flag_set(tp, HW_TSO_3); in tg3_get_invariants()
16293 else if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16294 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16295 tg3_flag_set(tp, HW_TSO_2); in tg3_get_invariants()
16296 else if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
16297 tg3_flag_set(tp, HW_TSO_1); in tg3_get_invariants()
16298 tg3_flag_set(tp, TSO_BUG); in tg3_get_invariants()
16299 if (tg3_asic_rev(tp) == ASIC_REV_5750 && in tg3_get_invariants()
16300 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2) in tg3_get_invariants()
16301 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16302 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_get_invariants()
16303 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_get_invariants()
16304 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_get_invariants()
16305 tg3_flag_set(tp, FW_TSO); in tg3_get_invariants()
16306 tg3_flag_set(tp, TSO_BUG); in tg3_get_invariants()
16307 if (tg3_asic_rev(tp) == ASIC_REV_5705) in tg3_get_invariants()
16308 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16310 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16314 if (tg3_flag(tp, HW_TSO_1) || in tg3_get_invariants()
16315 tg3_flag(tp, HW_TSO_2) || in tg3_get_invariants()
16316 tg3_flag(tp, HW_TSO_3) || in tg3_get_invariants()
16317 tg3_flag(tp, FW_TSO)) { in tg3_get_invariants()
16322 tg3_flag_set(tp, TSO_CAPABLE); in tg3_get_invariants()
16324 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16325 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16326 tp->fw_needed = NULL; in tg3_get_invariants()
16329 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) in tg3_get_invariants()
16330 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16332 if (tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_get_invariants()
16333 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16335 tp->irq_max = 1; in tg3_get_invariants()
16337 if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
16338 tg3_flag_set(tp, SUPPORT_MSI); in tg3_get_invariants()
16339 if (tg3_chip_rev(tp) == CHIPREV_5750_AX || in tg3_get_invariants()
16340 tg3_chip_rev(tp) == CHIPREV_5750_BX || in tg3_get_invariants()
16341 (tg3_asic_rev(tp) == ASIC_REV_5714 && in tg3_get_invariants()
16342 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 && in tg3_get_invariants()
16343 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16344 tg3_flag_clear(tp, SUPPORT_MSI); in tg3_get_invariants()
16346 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16347 tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16348 tg3_flag_set(tp, 1SHOT_MSI); in tg3_get_invariants()
16351 if (tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
16352 tg3_flag_set(tp, SUPPORT_MSIX); in tg3_get_invariants()
16353 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16357 tp->txq_max = 1; in tg3_get_invariants()
16358 tp->rxq_max = 1; in tg3_get_invariants()
16359 if (tp->irq_max > 1) { in tg3_get_invariants()
16360 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16361 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS); in tg3_get_invariants()
16363 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16364 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_get_invariants()
16365 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16368 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16369 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16370 tg3_flag_set(tp, SHORT_DMA_BUG); in tg3_get_invariants()
16372 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_get_invariants()
16373 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16375 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16376 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16377 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_get_invariants()
16378 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16379 tg3_flag_set(tp, LRG_PROD_RING_CAP); in tg3_get_invariants()
16381 if (tg3_flag(tp, 57765_PLUS) && in tg3_get_invariants()
16382 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0) in tg3_get_invariants()
16383 tg3_flag_set(tp, USE_JUMBO_BDFLAG); in tg3_get_invariants()
16385 if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
16386 tg3_flag(tp, 5780_CLASS) || in tg3_get_invariants()
16387 tg3_flag(tp, USE_JUMBO_BDFLAG)) in tg3_get_invariants()
16388 tg3_flag_set(tp, JUMBO_CAPABLE); in tg3_get_invariants()
16390 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16393 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16396 tg3_flag_set(tp, PCI_EXPRESS); in tg3_get_invariants()
16398 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16400 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16401 tg3_flag_clear(tp, HW_TSO_2); in tg3_get_invariants()
16402 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16404 if (tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_get_invariants()
16405 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_get_invariants()
16406 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 || in tg3_get_invariants()
16407 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1) in tg3_get_invariants()
16408 tg3_flag_set(tp, CLKREQ_BUG); in tg3_get_invariants()
16409 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) { in tg3_get_invariants()
16410 tg3_flag_set(tp, L1PLLPD_EN); in tg3_get_invariants()
16412 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_get_invariants()
16417 tg3_flag_set(tp, PCI_EXPRESS); in tg3_get_invariants()
16418 } else if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
16419 tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16420 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16421 if (!tp->pcix_cap) { in tg3_get_invariants()
16422 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16428 tg3_flag_set(tp, PCIX_MODE); in tg3_get_invariants()
16438 !tg3_flag(tp, PCI_EXPRESS)) in tg3_get_invariants()
16439 tg3_flag_set(tp, MBOX_WRITE_REORDER); in tg3_get_invariants()
16441 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16442 &tp->pci_cacheline_sz); in tg3_get_invariants()
16443 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16444 &tp->pci_lat_timer); in tg3_get_invariants()
16445 if (tg3_asic_rev(tp) == ASIC_REV_5703 && in tg3_get_invariants()
16446 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16447 tp->pci_lat_timer = 64; in tg3_get_invariants()
16448 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16449 tp->pci_lat_timer); in tg3_get_invariants()
16455 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) { in tg3_get_invariants()
16459 tg3_flag_set(tp, TXD_MBOX_HWBUG); in tg3_get_invariants()
16466 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16469 tg3_flag_set(tp, PCIX_TARGET_HWBUG); in tg3_get_invariants()
16475 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16476 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16480 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16481 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16485 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16487 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16492 tg3_flag_set(tp, PCI_HIGH_SPEED); in tg3_get_invariants()
16494 tg3_flag_set(tp, PCI_32BIT); in tg3_get_invariants()
16497 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) && in tg3_get_invariants()
16500 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16504 tp->read32 = tg3_read32; in tg3_get_invariants()
16505 tp->write32 = tg3_write32; in tg3_get_invariants()
16506 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16507 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16508 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16509 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16512 if (tg3_flag(tp, PCIX_TARGET_HWBUG)) in tg3_get_invariants()
16513 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16514 else if (tg3_asic_rev(tp) == ASIC_REV_5701 || in tg3_get_invariants()
16515 (tg3_flag(tp, PCI_EXPRESS) && in tg3_get_invariants()
16516 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) { in tg3_get_invariants()
16524 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16527 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { in tg3_get_invariants()
16528 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16529 if (tg3_flag(tp, MBOX_WRITE_REORDER)) in tg3_get_invariants()
16530 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16533 if (tg3_flag(tp, ICH_WORKAROUND)) { in tg3_get_invariants()
16534 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16535 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16536 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16537 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16538 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16539 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16541 iounmap(tp->regs); in tg3_get_invariants()
16542 tp->regs = NULL; in tg3_get_invariants()
16544 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16546 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16548 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16549 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16550 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16551 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16552 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16555 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16556 (tg3_flag(tp, PCIX_MODE) && in tg3_get_invariants()
16557 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16558 tg3_asic_rev(tp) == ASIC_REV_5701))) in tg3_get_invariants()
16559 tg3_flag_set(tp, SRAM_USE_CONFIG); in tg3_get_invariants()
16569 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16570 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_invariants()
16571 tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16572 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16573 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16574 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16576 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16578 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16579 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16580 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_get_invariants()
16581 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); in tg3_get_invariants()
16585 if (tg3_asic_rev(tp) == ASIC_REV_5717) in tg3_get_invariants()
16586 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16588 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16592 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { in tg3_get_invariants()
16593 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16594 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16605 tg3_get_eeprom_hw_cfg(tp); in tg3_get_invariants()
16607 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) { in tg3_get_invariants()
16608 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16609 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16610 tp->fw_needed = NULL; in tg3_get_invariants()
16613 if (tg3_flag(tp, ENABLE_APE)) { in tg3_get_invariants()
16620 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16623 tg3_ape_lock_init(tp); in tg3_get_invariants()
16631 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16632 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16633 tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_get_invariants()
16634 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16639 else if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_get_invariants()
16640 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16642 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_get_invariants()
16643 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_get_invariants()
16644 tg3_flag(tp, 57765_CLASS)) in tg3_get_invariants()
16645 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16647 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16648 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16650 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16651 if (tg3_flag(tp, IS_NIC)) in tg3_get_invariants()
16653 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16657 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16658 tp->grc_local_ctrl |= in tg3_get_invariants()
16662 tg3_pwrsrc_switch_to_vmain(tp); in tg3_get_invariants()
16667 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16668 tg3_flag_set(tp, JUMBO_RING_ENABLE); in tg3_get_invariants()
16671 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16672 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
16673 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || in tg3_get_invariants()
16674 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) { in tg3_get_invariants()
16675 tg3_flag_clear(tp, WOL_SPEED_100MB); in tg3_get_invariants()
16677 tg3_flag_set(tp, WOL_SPEED_100MB); in tg3_get_invariants()
16680 if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16681 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16684 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16685 (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_get_invariants()
16686 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) && in tg3_get_invariants()
16687 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) || in tg3_get_invariants()
16688 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16689 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16690 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16692 if (tg3_chip_rev(tp) == CHIPREV_5703_AX || in tg3_get_invariants()
16693 tg3_chip_rev(tp) == CHIPREV_5704_AX) in tg3_get_invariants()
16694 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16695 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) in tg3_get_invariants()
16696 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16698 if (tg3_flag(tp, 5705_PLUS) && in tg3_get_invariants()
16699 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16700 tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_get_invariants()
16701 tg3_asic_rev(tp) != ASIC_REV_57780 && in tg3_get_invariants()
16702 !tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
16703 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_get_invariants()
16704 tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_get_invariants()
16705 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_get_invariants()
16706 tg3_asic_rev(tp) == ASIC_REV_5761) { in tg3_get_invariants()
16707 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16708 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16709 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16710 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16711 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16713 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16716 if (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_get_invariants()
16717 tg3_chip_rev(tp) != CHIPREV_5784_AX) { in tg3_get_invariants()
16718 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16719 if (tp->phy_otp == 0) in tg3_get_invariants()
16720 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16723 if (tg3_flag(tp, CPMU_PRESENT)) in tg3_get_invariants()
16724 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16726 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16728 tp->coalesce_mode = 0; in tg3_get_invariants()
16729 if (tg3_chip_rev(tp) != CHIPREV_5700_AX && in tg3_get_invariants()
16730 tg3_chip_rev(tp) != CHIPREV_5700_BX) in tg3_get_invariants()
16731 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16734 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16735 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_get_invariants()
16736 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_get_invariants()
16737 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) { in tg3_get_invariants()
16738 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16739 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16742 if (tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_get_invariants()
16743 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_get_invariants()
16744 tg3_flag_set(tp, USE_PHYLIB); in tg3_get_invariants()
16746 err = tg3_mdio_init(tp); in tg3_get_invariants()
16752 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_get_invariants()
16753 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16762 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16764 tg3_switch_clocks(tp); in tg3_get_invariants()
16772 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16775 !tg3_flag(tp, PCIX_TARGET_HWBUG)) { in tg3_get_invariants()
16776 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
16777 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || in tg3_get_invariants()
16778 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 || in tg3_get_invariants()
16779 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) { in tg3_get_invariants()
16786 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16792 tg3_flag_set(tp, PCIX_TARGET_HWBUG); in tg3_get_invariants()
16797 tg3_nvram_init(tp); in tg3_get_invariants()
16800 if (tg3_asic_rev(tp) == ASIC_REV_57766 && in tg3_get_invariants()
16801 !tg3_flag(tp, NO_NVRAM)) in tg3_get_invariants()
16802 tp->fw_needed = NULL; in tg3_get_invariants()
16807 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_get_invariants()
16810 tg3_flag_set(tp, IS_5788); in tg3_get_invariants()
16812 if (!tg3_flag(tp, IS_5788) && in tg3_get_invariants()
16813 tg3_asic_rev(tp) != ASIC_REV_5700) in tg3_get_invariants()
16814 tg3_flag_set(tp, TAGGED_STATUS); in tg3_get_invariants()
16815 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_get_invariants()
16816 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16819 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16820 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16821 tp->misc_host_ctrl); in tg3_get_invariants()
16825 if (tg3_flag(tp, ENABLE_APE)) in tg3_get_invariants()
16826 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16828 tp->mac_mode = 0; in tg3_get_invariants()
16830 if (tg3_10_100_only_device(tp, ent)) in tg3_get_invariants()
16831 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16833 err = tg3_phy_probe(tp); in tg3_get_invariants()
16835 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16837 tg3_mdio_fini(tp); in tg3_get_invariants()
16840 tg3_read_vpd(tp); in tg3_get_invariants()
16841 tg3_read_fw_ver(tp); in tg3_get_invariants()
16843 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16844 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16846 if (tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_get_invariants()
16847 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16849 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16856 if (tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_get_invariants()
16857 tg3_flag_set(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16859 tg3_flag_clear(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16865 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
16866 tg3_asic_rev(tp) == ASIC_REV_5701 && in tg3_get_invariants()
16867 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
16868 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16869 tg3_flag_set(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16873 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
16874 tg3_flag_set(tp, POLL_SERDES); in tg3_get_invariants()
16876 tg3_flag_clear(tp, POLL_SERDES); in tg3_get_invariants()
16878 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF)) in tg3_get_invariants()
16879 tg3_flag_set(tp, POLL_CPMU_LINK); in tg3_get_invariants()
16881 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
16882 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
16883 if (tg3_asic_rev(tp) == ASIC_REV_5701 && in tg3_get_invariants()
16884 tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16885 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
16887 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
16891 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
16892 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
16893 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
16895 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
16900 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_get_invariants()
16901 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_get_invariants()
16902 tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_get_invariants()
16903 tp->rx_std_max_post = 8; in tg3_get_invariants()
16905 if (tg3_flag(tp, ASPM_WORKAROUND)) in tg3_get_invariants()
16906 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
16913 static int tg3_get_macaddr_sparc(struct tg3 *tp) in tg3_get_macaddr_sparc() argument
16915 struct net_device *dev = tp->dev; in tg3_get_macaddr_sparc()
16916 struct pci_dev *pdev = tp->pdev; in tg3_get_macaddr_sparc()
16929 static int tg3_get_default_macaddr_sparc(struct tg3 *tp) in tg3_get_default_macaddr_sparc() argument
16931 struct net_device *dev = tp->dev; in tg3_get_default_macaddr_sparc()
16938 static int tg3_get_device_address(struct tg3 *tp) in tg3_get_device_address() argument
16940 struct net_device *dev = tp->dev; in tg3_get_device_address()
16946 if (!tg3_get_macaddr_sparc(tp)) in tg3_get_device_address()
16950 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_get_device_address()
16951 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]); in tg3_get_device_address()
16957 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_device_address()
16958 tg3_flag(tp, 5780_CLASS)) { in tg3_get_device_address()
16961 if (tg3_nvram_lock(tp)) in tg3_get_device_address()
16964 tg3_nvram_unlock(tp); in tg3_get_device_address()
16965 } else if (tg3_flag(tp, 5717_PLUS)) { in tg3_get_device_address()
16966 if (tp->pci_fn & 1) in tg3_get_device_address()
16968 if (tp->pci_fn > 1) in tg3_get_device_address()
16970 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_device_address()
16974 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); in tg3_get_device_address()
16979 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); in tg3_get_device_address()
16990 if (!tg3_flag(tp, NO_NVRAM) && in tg3_get_device_address()
16991 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && in tg3_get_device_address()
16992 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { in tg3_get_device_address()
17012 if (!tg3_get_default_macaddr_sparc(tp)) in tg3_get_device_address()
17023 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val) in tg3_calc_dma_bndry() argument
17029 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17038 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_calc_dma_bndry()
17039 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_calc_dma_bndry()
17040 !tg3_flag(tp, PCI_EXPRESS)) in tg3_calc_dma_bndry()
17053 if (tg3_flag(tp, 57765_PLUS)) { in tg3_calc_dma_bndry()
17072 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
17097 } else if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
17164 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, in tg3_do_test_dma() argument
17215 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17217 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17219 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17252 static int tg3_test_dma(struct tg3 *tp) in tg3_test_dma() argument
17258 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17265 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17268 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17270 if (tg3_flag(tp, 57765_PLUS)) in tg3_test_dma()
17273 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_test_dma()
17275 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17276 } else if (!tg3_flag(tp, PCIX_MODE)) { in tg3_test_dma()
17277 if (tg3_asic_rev(tp) == ASIC_REV_5705 || in tg3_test_dma()
17278 tg3_asic_rev(tp) == ASIC_REV_5750) in tg3_test_dma()
17279 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17281 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17283 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_test_dma()
17284 tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_test_dma()
17292 if (tg3_flag(tp, 40BIT_DMA_BUG) && in tg3_test_dma()
17293 tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_test_dma()
17294 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17296 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17298 if (tg3_asic_rev(tp) == ASIC_REV_5703) in tg3_test_dma()
17301 tp->dma_rwctrl |= in tg3_test_dma()
17305 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) { in tg3_test_dma()
17307 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17308 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_test_dma()
17310 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17312 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17315 if (tg3_flag(tp, ONE_DMA_AT_ONCE)) in tg3_test_dma()
17316 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17318 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_test_dma()
17319 tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_test_dma()
17320 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17322 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_test_dma()
17323 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_test_dma()
17325 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17337 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17340 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17343 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_test_dma()
17344 tg3_asic_rev(tp) != ASIC_REV_5701) in tg3_test_dma()
17350 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17351 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17352 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17361 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true); in tg3_test_dma()
17363 dev_err(&tp->pdev->dev, in tg3_test_dma()
17370 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false); in tg3_test_dma()
17372 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17382 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17384 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17385 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17386 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17389 dev_err(&tp->pdev->dev, in tg3_test_dma()
17403 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17410 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17411 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17414 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17417 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17421 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17426 static void tg3_init_bufmgr_config(struct tg3 *tp) in tg3_init_bufmgr_config() argument
17428 if (tg3_flag(tp, 57765_PLUS)) { in tg3_init_bufmgr_config()
17429 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17431 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17433 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17436 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17438 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17440 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17442 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_bufmgr_config()
17443 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17445 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17447 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17449 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_init_bufmgr_config()
17450 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17452 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17456 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17458 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17460 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17463 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17465 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17467 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17470 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17472 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17474 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17478 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17479 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17482 static char *tg3_phy_string(struct tg3 *tp) in tg3_phy_string() argument
17484 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17514 static char *tg3_bus_string(struct tg3 *tp, char *str) in tg3_bus_string() argument
17516 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_bus_string()
17519 } else if (tg3_flag(tp, PCIX_MODE)) { in tg3_bus_string()
17538 if (tg3_flag(tp, PCI_HIGH_SPEED)) in tg3_bus_string()
17543 if (tg3_flag(tp, PCI_32BIT)) in tg3_bus_string()
17550 static void tg3_init_coal(struct tg3 *tp) in tg3_init_coal() argument
17552 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17566 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17574 if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_coal()
17585 struct tg3 *tp; in tg3_init_one() local
17608 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); in tg3_init_one()
17616 tp = netdev_priv(dev); in tg3_init_one()
17617 tp->pdev = pdev; in tg3_init_one()
17618 tp->dev = dev; in tg3_init_one()
17619 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17620 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17621 tp->irq_sync = 1; in tg3_init_one()
17622 tp->pcierr_recovery = false; in tg3_init_one()
17625 tp->msg_enable = tg3_debug; in tg3_init_one()
17627 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17630 tg3_flag_set(tp, IS_SSB_CORE); in tg3_init_one()
17632 tg3_flag_set(tp, FLUSH_POSTED_WRITES); in tg3_init_one()
17634 tg3_flag_set(tp, ONE_DMA_AT_ONCE); in tg3_init_one()
17636 tg3_flag_set(tp, USE_PHYLIB); in tg3_init_one()
17637 tg3_flag_set(tp, ROBOSWITCH); in tg3_init_one()
17640 tg3_flag_set(tp, RGMII_MODE); in tg3_init_one()
17647 tp->misc_host_ctrl = in tg3_init_one()
17659 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17662 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17664 spin_lock_init(&tp->lock); in tg3_init_one()
17665 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17666 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17668 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17669 if (!tp->regs) { in tg3_init_one()
17675 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17676 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17677 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17678 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17679 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17680 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17681 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17682 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17683 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17684 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17685 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17686 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17687 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17688 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17689 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17690 tg3_flag_set(tp, ENABLE_APE); in tg3_init_one()
17691 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17692 if (!tp->aperegs) { in tg3_init_one()
17700 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17701 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17708 err = tg3_get_invariants(tp, ent); in tg3_init_one()
17721 if (tg3_flag(tp, IS_5788)) in tg3_init_one()
17723 else if (tg3_flag(tp, 40BIT_DMA_BUG)) { in tg3_init_one()
17754 tg3_init_bufmgr_config(tp); in tg3_init_one()
17759 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) { in tg3_init_one()
17762 if (tg3_flag(tp, 5755_PLUS)) in tg3_init_one()
17770 if ((tg3_flag(tp, HW_TSO_1) || in tg3_init_one()
17771 tg3_flag(tp, HW_TSO_2) || in tg3_init_one()
17772 tg3_flag(tp, HW_TSO_3)) && in tg3_init_one()
17775 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { in tg3_init_one()
17778 if (tg3_flag(tp, HW_TSO_3) || in tg3_init_one()
17779 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_init_one()
17780 (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_init_one()
17781 tg3_chip_rev(tp) != CHIPREV_5784_AX) || in tg3_init_one()
17782 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_init_one()
17783 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_init_one()
17796 if (tg3_asic_rev(tp) != ASIC_REV_5780 && in tg3_init_one()
17797 !tg3_flag(tp, CPMU_PRESENT)) in tg3_init_one()
17804 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 && in tg3_init_one()
17805 !tg3_flag(tp, TSO_CAPABLE) && in tg3_init_one()
17807 tg3_flag_set(tp, MAX_RXPEND_64); in tg3_init_one()
17808 tp->rx_pending = 63; in tg3_init_one()
17811 err = tg3_get_device_address(tp); in tg3_init_one()
17821 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17822 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17824 tnapi->tp = tp; in tg3_init_one()
17841 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_init_one()
17869 tg3_full_lock(tp, 0); in tg3_init_one()
17871 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_init_one()
17872 tg3_full_unlock(tp); in tg3_init_one()
17875 err = tg3_test_dma(tp); in tg3_init_one()
17881 tg3_init_coal(tp); in tg3_init_one()
17885 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_init_one()
17886 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_init_one()
17887 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_init_one()
17888 tg3_flag_set(tp, PTP_CAPABLE); in tg3_init_one()
17890 tg3_timer_init(tp); in tg3_init_one()
17892 tg3_carrier_off(tp); in tg3_init_one()
17900 if (tg3_flag(tp, PTP_CAPABLE)) { in tg3_init_one()
17901 tg3_ptp_init(tp); in tg3_init_one()
17902 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
17903 &tp->pdev->dev); in tg3_init_one()
17904 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
17905 tp->ptp_clock = NULL; in tg3_init_one()
17909 tp->board_part_number, in tg3_init_one()
17910 tg3_chip_rev_id(tp), in tg3_init_one()
17911 tg3_bus_string(tp, str), in tg3_init_one()
17914 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_init_one()
17916 phydev = tp->mdio_bus->phy_map[tp->phy_addr]; in tg3_init_one()
17923 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
17925 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
17932 tg3_phy_string(tp), ethtype, in tg3_init_one()
17933 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
17934 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
17939 tg3_flag(tp, USE_LINKCHG_REG) != 0, in tg3_init_one()
17940 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
17941 tg3_flag(tp, ENABLE_ASF) != 0, in tg3_init_one()
17942 tg3_flag(tp, TSO_CAPABLE) != 0); in tg3_init_one()
17944 tp->dma_rwctrl, in tg3_init_one()
17953 if (tp->aperegs) { in tg3_init_one()
17954 iounmap(tp->aperegs); in tg3_init_one()
17955 tp->aperegs = NULL; in tg3_init_one()
17959 if (tp->regs) { in tg3_init_one()
17960 iounmap(tp->regs); in tg3_init_one()
17961 tp->regs = NULL; in tg3_init_one()
17981 struct tg3 *tp = netdev_priv(dev); in tg3_remove_one() local
17983 tg3_ptp_fini(tp); in tg3_remove_one()
17985 release_firmware(tp->fw); in tg3_remove_one()
17987 tg3_reset_task_cancel(tp); in tg3_remove_one()
17989 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_remove_one()
17990 tg3_phy_fini(tp); in tg3_remove_one()
17991 tg3_mdio_fini(tp); in tg3_remove_one()
17995 if (tp->aperegs) { in tg3_remove_one()
17996 iounmap(tp->aperegs); in tg3_remove_one()
17997 tp->aperegs = NULL; in tg3_remove_one()
17999 if (tp->regs) { in tg3_remove_one()
18000 iounmap(tp->regs); in tg3_remove_one()
18001 tp->regs = NULL; in tg3_remove_one()
18014 struct tg3 *tp = netdev_priv(dev); in tg3_suspend() local
18022 tg3_reset_task_cancel(tp); in tg3_suspend()
18023 tg3_phy_stop(tp); in tg3_suspend()
18024 tg3_netif_stop(tp); in tg3_suspend()
18026 tg3_timer_stop(tp); in tg3_suspend()
18028 tg3_full_lock(tp, 1); in tg3_suspend()
18029 tg3_disable_ints(tp); in tg3_suspend()
18030 tg3_full_unlock(tp); in tg3_suspend()
18034 tg3_full_lock(tp, 0); in tg3_suspend()
18035 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_suspend()
18036 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_suspend()
18037 tg3_full_unlock(tp); in tg3_suspend()
18039 err = tg3_power_down_prepare(tp); in tg3_suspend()
18043 tg3_full_lock(tp, 0); in tg3_suspend()
18045 tg3_flag_set(tp, INIT_COMPLETE); in tg3_suspend()
18046 err2 = tg3_restart_hw(tp, true); in tg3_suspend()
18050 tg3_timer_start(tp); in tg3_suspend()
18053 tg3_netif_start(tp); in tg3_suspend()
18056 tg3_full_unlock(tp); in tg3_suspend()
18059 tg3_phy_start(tp); in tg3_suspend()
18071 struct tg3 *tp = netdev_priv(dev); in tg3_resume() local
18081 tg3_full_lock(tp, 0); in tg3_resume()
18083 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_resume()
18085 tg3_flag_set(tp, INIT_COMPLETE); in tg3_resume()
18086 err = tg3_restart_hw(tp, in tg3_resume()
18087 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18091 tg3_timer_start(tp); in tg3_resume()
18093 tg3_netif_start(tp); in tg3_resume()
18096 tg3_full_unlock(tp); in tg3_resume()
18099 tg3_phy_start(tp); in tg3_resume()
18112 struct tg3 *tp = netdev_priv(dev); in tg3_shutdown() local
18121 tg3_power_down(tp); in tg3_shutdown()
18138 struct tg3 *tp = netdev_priv(netdev); in tg3_io_error_detected() local
18147 tp->pcierr_recovery = true; in tg3_io_error_detected()
18153 tg3_phy_stop(tp); in tg3_io_error_detected()
18155 tg3_netif_stop(tp); in tg3_io_error_detected()
18157 tg3_timer_stop(tp); in tg3_io_error_detected()
18160 tg3_reset_task_cancel(tp); in tg3_io_error_detected()
18165 tg3_full_lock(tp, 0); in tg3_io_error_detected()
18166 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_io_error_detected()
18167 tg3_full_unlock(tp); in tg3_io_error_detected()
18172 tg3_napi_enable(tp); in tg3_io_error_detected()
18197 struct tg3 *tp = netdev_priv(netdev); in tg3_io_slot_reset() local
18218 err = tg3_power_up(tp); in tg3_io_slot_reset()
18226 tg3_napi_enable(tp); in tg3_io_slot_reset()
18244 struct tg3 *tp = netdev_priv(netdev); in tg3_io_resume() local
18252 tg3_full_lock(tp, 0); in tg3_io_resume()
18253 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_io_resume()
18254 tg3_flag_set(tp, INIT_COMPLETE); in tg3_io_resume()
18255 err = tg3_restart_hw(tp, true); in tg3_io_resume()
18257 tg3_full_unlock(tp); in tg3_io_resume()
18264 tg3_timer_start(tp); in tg3_io_resume()
18266 tg3_netif_start(tp); in tg3_io_resume()
18268 tg3_full_unlock(tp); in tg3_io_resume()
18270 tg3_phy_start(tp); in tg3_io_resume()
18273 tp->pcierr_recovery = false; in tg3_io_resume()