Lines Matching refs:int0_enable
1838 u32 int0_enable = 0; in bcmgenet_link_intr_enable() local
1844 int0_enable |= UMAC_IRQ_LINK_EVENT; in bcmgenet_link_intr_enable()
1846 int0_enable |= UMAC_IRQ_LINK_EVENT; in bcmgenet_link_intr_enable()
1849 int0_enable |= UMAC_IRQ_LINK_EVENT; in bcmgenet_link_intr_enable()
1851 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); in bcmgenet_link_intr_enable()
1859 u32 int0_enable = 0; in init_umac() local
1889 int0_enable |= UMAC_IRQ_RXDMA_DONE; in init_umac()
1892 int0_enable |= UMAC_IRQ_TXDMA_DONE; in init_umac()
1909 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); in init_umac()
1919 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); in init_umac()
3012 u32 int0_enable = 0; in bcmgenet_timeout() local
3027 int0_enable = UMAC_IRQ_TXDMA_DONE; in bcmgenet_timeout()
3030 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); in bcmgenet_timeout()