1364 	u32 xmac_base;  in bnx2x_update_pfc_xmac()  local
1368 	xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;  in bnx2x_update_pfc_xmac()
1394 		REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);  in bnx2x_update_pfc_xmac()
1395 		REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);  in bnx2x_update_pfc_xmac()
1396 		REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);  in bnx2x_update_pfc_xmac()
1402 	REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);  in bnx2x_update_pfc_xmac()
1403 	REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);  in bnx2x_update_pfc_xmac()
1404 	REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);  in bnx2x_update_pfc_xmac()
1408 	REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,  in bnx2x_update_pfc_xmac()
1413 	REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,  in bnx2x_update_pfc_xmac()
1720 	u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;  in bnx2x_set_xmac_rxtx()  local
1729 		pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);  in bnx2x_set_xmac_rxtx()
1730 		REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,  in bnx2x_set_xmac_rxtx()
1732 		REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,  in bnx2x_set_xmac_rxtx()
1735 		val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);  in bnx2x_set_xmac_rxtx()
1740 		REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);  in bnx2x_set_xmac_rxtx()
1747 	u32 val, xmac_base;  in bnx2x_xmac_enable()  local
1751 	xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;  in bnx2x_xmac_enable()
1768 		REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,  in bnx2x_xmac_enable()
1771 		REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);  in bnx2x_xmac_enable()
1772 		REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,  in bnx2x_xmac_enable()
1777 	REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);  in bnx2x_xmac_enable()
1780 	REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);  in bnx2x_xmac_enable()
1787 		REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);  in bnx2x_xmac_enable()
1788 		REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);  in bnx2x_xmac_enable()
1790 		REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);  in bnx2x_xmac_enable()
1805 	REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);  in bnx2x_xmac_enable()
12999 		u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;  in bnx2x_link_reset()  local
13003 			REG_WR(bp, xmac_base + XMAC_REG_CTRL,  in bnx2x_link_reset()