3892 	u16 val16, i, lane;  in bnx2x_warpcore_set_10G_KR()  local
3916 			MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);  in bnx2x_warpcore_set_10G_KR()
3917 	val16 &= ~(0x0011 << lane);  in bnx2x_warpcore_set_10G_KR()
3919 			 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);  in bnx2x_warpcore_set_10G_KR()
3922 			MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);  in bnx2x_warpcore_set_10G_KR()
3923 	val16 |= (0x0303 << (lane << 1));  in bnx2x_warpcore_set_10G_KR()
3925 			 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);  in bnx2x_warpcore_set_10G_KR()
4204 	u16 val16, digctrl_kx1, digctrl_kx2;  in bnx2x_warpcore_set_sgmii_speed()  local
4220 				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);  in bnx2x_warpcore_set_sgmii_speed()
4221 		val16 &= 0xcebf;  in bnx2x_warpcore_set_sgmii_speed()
4226 			val16 |= 0x2000;  in bnx2x_warpcore_set_sgmii_speed()
4229 			val16 |= 0x0040;  in bnx2x_warpcore_set_sgmii_speed()
4238 			val16 |= 0x0100;  in bnx2x_warpcore_set_sgmii_speed()
4241 				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);  in bnx2x_warpcore_set_sgmii_speed()
4246 				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);  in bnx2x_warpcore_set_sgmii_speed()
4247 		DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);  in bnx2x_warpcore_set_sgmii_speed()
4608 	u16 val16, lane;  in bnx2x_warpcore_link_reset()  local
4636 			MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);  in bnx2x_warpcore_link_reset()
4637 	val16 |= (0x11 << lane);  in bnx2x_warpcore_link_reset()
4639 		val16 |= (0x22 << lane);  in bnx2x_warpcore_link_reset()
4641 			 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);  in bnx2x_warpcore_link_reset()
4644 			MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);  in bnx2x_warpcore_link_reset()
4645 	val16 &= ~(0x0303 << (lane << 1));  in bnx2x_warpcore_link_reset()
4646 	val16 |= (0x0101 << (lane << 1));  in bnx2x_warpcore_link_reset()
4648 		val16 &= ~(0x0c0c << (lane << 1));  in bnx2x_warpcore_link_reset()
4649 		val16 |= (0x0404 << (lane << 1));  in bnx2x_warpcore_link_reset()
4653 			 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);  in bnx2x_warpcore_link_reset()
4663 	u16 val16;  in bnx2x_set_warpcore_loopback()  local
4682 				MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);  in bnx2x_set_warpcore_loopback()
4683 		val16 |= (1<<lane);  in bnx2x_set_warpcore_loopback()
4685 			val16 |= (2<<lane);  in bnx2x_set_warpcore_loopback()
4688 				 val16);  in bnx2x_set_warpcore_loopback()
10590 	u16 val16;  in bnx2x_848x3_link_reset()  local
10604 				MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);  in bnx2x_848x3_link_reset()
10605 		val16 |= MDIO_84833_SUPER_ISOLATE;  in bnx2x_848x3_link_reset()
10608 				 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);  in bnx2x_848x3_link_reset()