Lines Matching refs:phy
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
223 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
1461 params->phy[phy_index].mdio_ctrl); in bnx2x_set_mdio_emac_per_phy()
1767 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { in bnx2x_xmac_enable()
1798 (params->phy[INT_PHY].supported & in bnx2x_xmac_enable()
2599 struct bnx2x_phy *phy, in bnx2x_cl22_write() argument
2606 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_write()
2607 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_write()
2611 tmp = ((phy->addr << 21) | (reg << 16) | val | in bnx2x_cl22_write()
2614 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl22_write()
2619 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_write()
2629 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_write()
2634 struct bnx2x_phy *phy, in bnx2x_cl22_read() argument
2642 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_read()
2643 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_read()
2647 val = ((phy->addr << 21) | (reg << 16) | in bnx2x_cl22_read()
2650 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl22_read()
2655 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_read()
2668 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_read()
2675 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_read() argument
2682 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { in bnx2x_cl45_read()
2685 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_read()
2688 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_read()
2689 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2692 val = ((phy->addr << 21) | (devad << 16) | reg | in bnx2x_cl45_read()
2695 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2700 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_read()
2713 val = ((phy->addr << 21) | (devad << 16) | in bnx2x_cl45_read()
2716 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2721 val = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_read()
2736 if (phy->flags & FLAGS_MDC_MDIO_WA) { in bnx2x_cl45_read()
2737 phy->flags ^= FLAGS_DUMMY_READ; in bnx2x_cl45_read()
2738 if (phy->flags & FLAGS_DUMMY_READ) { in bnx2x_cl45_read()
2740 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_read()
2744 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_read()
2745 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2750 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_write() argument
2757 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { in bnx2x_cl45_write()
2760 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_write()
2763 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_write()
2764 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2768 tmp = ((phy->addr << 21) | (devad << 16) | reg | in bnx2x_cl45_write()
2771 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2776 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_write()
2788 tmp = ((phy->addr << 21) | (devad << 16) | val | in bnx2x_cl45_write()
2791 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2796 tmp = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_write()
2810 if (phy->flags & FLAGS_MDC_MDIO_WA) { in bnx2x_cl45_write()
2811 phy->flags ^= FLAGS_DUMMY_READ; in bnx2x_cl45_write()
2812 if (phy->flags & FLAGS_DUMMY_READ) { in bnx2x_cl45_write()
2814 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_write()
2817 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_write()
2818 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2961 static int bnx2x_eee_disable(struct bnx2x_phy *phy, in bnx2x_eee_disable() argument
2970 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); in bnx2x_eee_disable()
2977 static int bnx2x_eee_advertise(struct bnx2x_phy *phy, in bnx2x_eee_advertise() argument
2996 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); in bnx2x_eee_advertise()
3014 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, in bnx2x_eee_an_resolve() argument
3023 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); in bnx2x_eee_an_resolve()
3024 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); in bnx2x_eee_an_resolve()
3177 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_read_or_write() argument
3181 bnx2x_cl45_read(bp, phy, devad, reg, &val); in bnx2x_cl45_read_or_write()
3182 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); in bnx2x_cl45_read_or_write()
3186 struct bnx2x_phy *phy, in bnx2x_cl45_read_and_write() argument
3190 bnx2x_cl45_read(bp, phy, devad, reg, &val); in bnx2x_cl45_read_and_write()
3191 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); in bnx2x_cl45_read_and_write()
3202 if (params->phy[phy_index].addr == phy_addr) { in bnx2x_phy_read()
3204 ¶ms->phy[phy_index], devad, in bnx2x_phy_read()
3219 if (params->phy[phy_index].addr == phy_addr) { in bnx2x_phy_write()
3221 ¶ms->phy[phy_index], devad, in bnx2x_phy_write()
3227 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, in bnx2x_get_warpcore_lane() argument
3282 struct bnx2x_phy *phy) in bnx2x_set_aer_mmd() argument
3291 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? in bnx2x_set_aer_mmd()
3292 (phy->addr + ser_lane) : 0; in bnx2x_set_aer_mmd()
3295 aer_val = bnx2x_get_warpcore_lane(phy, params); in bnx2x_set_aer_mmd()
3302 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_set_aer_mmd()
3309 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_set_aer_mmd()
3351 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, in bnx2x_xgxs_specific_func() argument
3361 phy->def_md_devad); in bnx2x_xgxs_specific_func()
3380 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, in bnx2x_xgxs_deassert()
3384 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, in bnx2x_calc_ieee_aneg_adv() argument
3393 switch (phy->req_flow_ctrl) { in bnx2x_calc_ieee_aneg_adv()
3442 params->phy[actual_phy_idx].req_flow_ctrl = in set_phy_vars()
3445 params->phy[actual_phy_idx].req_line_speed = in set_phy_vars()
3448 params->phy[actual_phy_idx].speed_cap_mask = in set_phy_vars()
3451 params->phy[actual_phy_idx].req_duplex = in set_phy_vars()
3460 params->phy[actual_phy_idx].req_flow_ctrl, in set_phy_vars()
3461 params->phy[actual_phy_idx].req_line_speed, in set_phy_vars()
3462 params->phy[actual_phy_idx].speed_cap_mask); in set_phy_vars()
3467 struct bnx2x_phy *phy, in bnx2x_ext_phy_set_pause() argument
3473 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); in bnx2x_ext_phy_set_pause()
3478 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_ext_phy_set_pause()
3490 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); in bnx2x_ext_phy_set_pause()
3493 static void bnx2x_pause_resolve(struct bnx2x_phy *phy, in bnx2x_pause_resolve() argument
3540 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, in bnx2x_ext_phy_update_adv_fc() argument
3548 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { in bnx2x_ext_phy_update_adv_fc()
3549 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); in bnx2x_ext_phy_update_adv_fc()
3550 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); in bnx2x_ext_phy_update_adv_fc()
3553 u8 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_ext_phy_update_adv_fc()
3555 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3562 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3564 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3567 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3569 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3579 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3582 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3591 bnx2x_pause_resolve(phy, params, vars, pause_result); in bnx2x_ext_phy_update_adv_fc()
3595 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, in bnx2x_ext_phy_resolve_fc() argument
3601 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { in bnx2x_ext_phy_resolve_fc()
3603 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_ext_phy_resolve_fc()
3604 bnx2x_ext_phy_update_adv_fc(phy, params, vars); in bnx2x_ext_phy_resolve_fc()
3606 vars->flow_ctrl = phy->req_flow_ctrl; in bnx2x_ext_phy_resolve_fc()
3607 } else if (phy->req_line_speed != SPEED_AUTO_NEG) in bnx2x_ext_phy_resolve_fc()
3611 bnx2x_ext_phy_update_adv_fc(phy, params, vars); in bnx2x_ext_phy_resolve_fc()
3634 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, in bnx2x_warpcore_enable_AN_KR2() argument
3661 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR2()
3665 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR2()
3675 struct bnx2x_phy *phy) in bnx2x_disable_kr2() argument
3700 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_disable_kr2()
3708 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, in bnx2x_warpcore_set_lpi_passthrough() argument
3714 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_lpi_passthrough()
3716 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_lpi_passthrough()
3720 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy, in bnx2x_warpcore_restart_AN_KR() argument
3725 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_restart_AN_KR()
3726 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_restart_AN_KR()
3728 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_restart_AN_KR()
3732 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_restart_AN_KR()
3735 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, in bnx2x_warpcore_enable_AN_KR() argument
3754 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR()
3757 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3761 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3766 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || in bnx2x_warpcore_enable_AN_KR()
3772 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); in bnx2x_warpcore_enable_AN_KR()
3776 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || in bnx2x_warpcore_enable_AN_KR()
3781 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_enable_AN_KR()
3784 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3786 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_enable_AN_KR()
3791 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_enable_AN_KR()
3792 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3796 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_warpcore_enable_AN_KR()
3797 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3800 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3803 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3808 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3812 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3822 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3829 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_warpcore_enable_AN_KR()
3831 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3835 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3838 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_warpcore_enable_AN_KR()
3839 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || in bnx2x_warpcore_enable_AN_KR()
3840 (phy->req_line_speed == SPEED_20000)) { in bnx2x_warpcore_enable_AN_KR()
3842 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_enable_AN_KR()
3845 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3849 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3851 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_enable_AN_KR()
3853 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); in bnx2x_warpcore_enable_AN_KR()
3856 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3861 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3876 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3880 bnx2x_disable_kr2(params, vars, phy); in bnx2x_warpcore_enable_AN_KR()
3884 bnx2x_warpcore_restart_AN_KR(phy, params); in bnx2x_warpcore_enable_AN_KR()
3887 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, in bnx2x_warpcore_set_10G_KR() argument
3907 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_set_10G_KR()
3910 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_set_10G_KR()
3912 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_10G_KR()
3915 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3918 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3921 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3924 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3927 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_set_10G_KR()
3929 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_10G_KR()
3932 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_10G_KR()
3936 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3940 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3944 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3948 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3950 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3955 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, in bnx2x_warpcore_set_10G_XFI() argument
3965 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3969 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3973 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); in bnx2x_warpcore_set_10G_XFI()
3976 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3980 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3984 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3988 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3993 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3995 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4000 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4056 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4060 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_set_10G_XFI()
4061 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4064 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4069 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4073 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4076 bnx2x_warpcore_set_lpi_passthrough(phy, params); in bnx2x_warpcore_set_10G_XFI()
4079 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4083 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4087 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4091 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, in bnx2x_warpcore_set_20G_force_KR2() argument
4097 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_20G_force_KR2()
4101 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4104 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_set_20G_force_KR2()
4106 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4108 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4111 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4115 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4119 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4122 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4125 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4129 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4131 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4135 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_20G_force_KR2()
4138 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4141 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_set_20G_force_KR2()
4145 struct bnx2x_phy *phy, in bnx2x_warpcore_set_20G_DXGXS() argument
4149 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4153 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4156 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4159 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4162 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4165 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4168 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4171 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4174 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4177 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4181 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4185 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4189 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4193 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4198 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, in bnx2x_warpcore_set_sgmii_speed() argument
4207 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4210 bnx2x_warpcore_set_lpi_passthrough(phy, params); in bnx2x_warpcore_set_sgmii_speed()
4212 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_warpcore_set_sgmii_speed()
4214 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4219 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4222 switch (phy->req_line_speed) { in bnx2x_warpcore_set_sgmii_speed()
4233 "Speed not supported: 0x%x\n", phy->req_line_speed); in bnx2x_warpcore_set_sgmii_speed()
4237 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_warpcore_set_sgmii_speed()
4240 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4244 phy->req_line_speed); in bnx2x_warpcore_set_sgmii_speed()
4245 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4251 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4258 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4263 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4265 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4270 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4275 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4281 struct bnx2x_phy *phy, in bnx2x_warpcore_reset_lane() argument
4286 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4292 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4294 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4298 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, in bnx2x_warpcore_clear_regs() argument
4321 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_clear_regs()
4325 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, in bnx2x_warpcore_clear_regs()
4328 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_clear_regs()
4329 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_clear_regs()
4373 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, in bnx2x_is_sfp_module_plugged() argument
4391 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, in bnx2x_warpcore_get_sigdet() argument
4397 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_get_sigdet()
4399 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, in bnx2x_warpcore_get_sigdet()
4405 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, in bnx2x_warpcore_config_runtime() argument
4419 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_config_runtime()
4428 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, in bnx2x_warpcore_config_runtime()
4438 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_config_runtime()
4439 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_runtime()
4442 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_config_runtime()
4458 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, in bnx2x_warpcore_config_sfi() argument
4461 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_config_sfi()
4463 bnx2x_warpcore_clear_regs(phy, params, lane); in bnx2x_warpcore_config_sfi()
4466 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { in bnx2x_warpcore_config_sfi()
4468 bnx2x_warpcore_set_10G_XFI(phy, params, 0); in bnx2x_warpcore_config_sfi()
4471 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); in bnx2x_warpcore_config_sfi()
4476 struct bnx2x_phy *phy, in bnx2x_sfp_e3_set_transmitter() argument
4492 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) in bnx2x_sfp_e3_set_transmitter()
4496 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, in bnx2x_warpcore_config_init() argument
4503 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_config_init()
4511 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_config_init()
4512 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_config_init()
4515 (phy->req_line_speed && in bnx2x_warpcore_config_init()
4516 ((phy->req_line_speed == SPEED_100) || in bnx2x_warpcore_config_init()
4517 (phy->req_line_speed == SPEED_10)))) { in bnx2x_warpcore_config_init()
4520 bnx2x_warpcore_clear_regs(phy, params, lane); in bnx2x_warpcore_config_init()
4521 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); in bnx2x_warpcore_config_init()
4527 bnx2x_warpcore_enable_AN_KR(phy, params, vars); in bnx2x_warpcore_config_init()
4530 bnx2x_warpcore_set_10G_KR(phy, params, vars); in bnx2x_warpcore_config_init()
4535 bnx2x_warpcore_clear_regs(phy, params, lane); in bnx2x_warpcore_config_init()
4538 bnx2x_warpcore_set_10G_XFI(phy, params, 1); in bnx2x_warpcore_config_init()
4547 bnx2x_warpcore_set_sgmii_speed(phy, in bnx2x_warpcore_config_init()
4562 if (bnx2x_is_sfp_module_plugged(phy, params)) in bnx2x_warpcore_config_init()
4563 bnx2x_sfp_module_detection(phy, params); in bnx2x_warpcore_config_init()
4566 phy, 1); in bnx2x_warpcore_config_init()
4569 bnx2x_warpcore_config_sfi(phy, params); in bnx2x_warpcore_config_init()
4578 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); in bnx2x_warpcore_config_init()
4581 bnx2x_sfp_module_detection(phy, params); in bnx2x_warpcore_config_init()
4585 bnx2x_warpcore_enable_AN_KR(phy, params, vars); in bnx2x_warpcore_config_init()
4588 bnx2x_warpcore_set_20G_force_KR2(phy, params); in bnx2x_warpcore_config_init()
4600 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_init()
4604 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, in bnx2x_warpcore_link_reset() argument
4609 bnx2x_sfp_e3_set_transmitter(params, phy, 0); in bnx2x_warpcore_link_reset()
4611 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_link_reset()
4613 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_link_reset()
4617 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4620 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4624 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_link_reset()
4627 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4631 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4633 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_link_reset()
4635 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4638 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_warpcore_link_reset()
4640 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4643 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4647 if (phy->flags & FLAGS_WC_DUAL_MODE) { in bnx2x_warpcore_link_reset()
4652 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4655 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_link_reset()
4659 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, in bnx2x_set_warpcore_loopback() argument
4666 params->loopback_mode, phy->req_line_speed); in bnx2x_set_warpcore_loopback()
4668 if (phy->req_line_speed < SPEED_10000 || in bnx2x_set_warpcore_loopback()
4669 phy->supported & SUPPORTED_20000baseKR2_Full) { in bnx2x_set_warpcore_loopback()
4673 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_set_warpcore_loopback()
4676 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4680 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_set_warpcore_loopback()
4681 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4684 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_set_warpcore_loopback()
4686 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4691 bnx2x_set_aer_mmd(params, phy); in bnx2x_set_warpcore_loopback()
4694 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4697 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4841 params->phy[INT_PHY].media_type = in bnx2x_link_status_update()
4844 params->phy[EXT_PHY1].media_type = in bnx2x_link_status_update()
4847 params->phy[EXT_PHY2].media_type = in bnx2x_link_status_update()
4878 struct bnx2x_phy *phy) in bnx2x_set_master_ln() argument
4887 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_master_ln()
4892 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_master_ln()
4899 struct bnx2x_phy *phy, in bnx2x_reset_unicore() argument
4905 CL22_RD_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4910 CL22_WR_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4923 CL22_RD_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4943 struct bnx2x_phy *phy) in bnx2x_set_swap_lanes() argument
4959 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4966 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4972 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4978 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4984 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, in bnx2x_set_parallel_detection() argument
4989 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4993 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) in bnx2x_set_parallel_detection()
4998 phy->speed_cap_mask, control2); in bnx2x_set_parallel_detection()
4999 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5004 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && in bnx2x_set_parallel_detection()
5005 (phy->speed_cap_mask & in bnx2x_set_parallel_detection()
5009 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5014 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5023 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5029 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5037 static void bnx2x_set_autoneg(struct bnx2x_phy *phy, in bnx2x_set_autoneg() argument
5046 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5057 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5063 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5074 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5079 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5092 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5099 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5105 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5113 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5117 if (phy->speed_cap_mask & in bnx2x_set_autoneg()
5120 if (phy->speed_cap_mask & in bnx2x_set_autoneg()
5124 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5135 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5141 static void bnx2x_program_serdes(struct bnx2x_phy *phy, in bnx2x_program_serdes() argument
5149 CL22_RD_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5155 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_program_serdes()
5157 CL22_WR_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5164 CL22_RD_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5184 CL22_WR_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5190 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, in bnx2x_set_brcm_cl37_advertisement() argument
5197 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) in bnx2x_set_brcm_cl37_advertisement()
5199 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) in bnx2x_set_brcm_cl37_advertisement()
5201 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_brcm_cl37_advertisement()
5205 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_brcm_cl37_advertisement()
5210 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, in bnx2x_set_ieee_aneg_advertisement() argument
5218 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5221 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5226 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5231 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, in bnx2x_restart_autoneg() argument
5242 CL22_RD_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5247 CL22_WR_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5255 CL22_RD_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5262 CL22_WR_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5271 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, in bnx2x_initialize_sgmii_process() argument
5280 CL22_RD_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5289 CL22_WR_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5299 CL22_RD_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5327 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_initialize_sgmii_process()
5330 CL22_WR_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5337 bnx2x_restart_autoneg(phy, params, 0); in bnx2x_initialize_sgmii_process()
5343 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, in bnx2x_direct_parallel_detect_used() argument
5348 if (phy->req_line_speed != SPEED_AUTO_NEG) in bnx2x_direct_parallel_detect_used()
5350 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5354 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5364 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5377 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, in bnx2x_update_adv_fc() argument
5392 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5396 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5406 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5410 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5420 bnx2x_pause_resolve(phy, params, vars, pause_result); in bnx2x_update_adv_fc()
5424 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, in bnx2x_flow_ctrl_resolve() argument
5433 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { in bnx2x_flow_ctrl_resolve()
5435 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_flow_ctrl_resolve()
5436 bnx2x_update_adv_fc(phy, params, vars, gp_status); in bnx2x_flow_ctrl_resolve()
5438 vars->flow_ctrl = phy->req_flow_ctrl; in bnx2x_flow_ctrl_resolve()
5439 } else if (phy->req_line_speed != SPEED_AUTO_NEG) in bnx2x_flow_ctrl_resolve()
5443 if (bnx2x_direct_parallel_detect_used(phy, params)) { in bnx2x_flow_ctrl_resolve()
5447 bnx2x_update_adv_fc(phy, params, vars, gp_status); in bnx2x_flow_ctrl_resolve()
5452 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, in bnx2x_check_fallback_to_cl37() argument
5459 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5467 CL22_WR_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5474 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5490 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5511 CL22_WR_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5516 bnx2x_restart_autoneg(phy, params, 0); in bnx2x_check_fallback_to_cl37()
5520 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, in bnx2x_xgxs_an_resolve() argument
5529 if (bnx2x_direct_parallel_detect_used(phy, params)) in bnx2x_xgxs_an_resolve()
5533 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, in bnx2x_get_link_speed_duplex() argument
5541 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_get_link_speed_duplex()
5624 static int bnx2x_link_settings_status(struct bnx2x_phy *phy, in bnx2x_link_settings_status() argument
5634 CL22_RD_OVER_CL45(bp, phy, in bnx2x_link_settings_status()
5645 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, in bnx2x_link_settings_status()
5653 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); in bnx2x_link_settings_status()
5654 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_link_settings_status()
5655 bnx2x_xgxs_an_resolve(phy, params, vars, in bnx2x_link_settings_status()
5659 if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_link_settings_status()
5662 bnx2x_check_fallback_to_cl37(phy, params); in bnx2x_link_settings_status()
5671 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, in bnx2x_link_settings_status()
5682 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, in bnx2x_link_settings_status()
5698 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, in bnx2x_warpcore_read_status() argument
5706 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_read_status()
5709 (phy->flags & FLAGS_WC_DUAL_MODE)) { in bnx2x_warpcore_read_status()
5710 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5712 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5715 } else if ((phy->req_line_speed > SPEED_10000) && in bnx2x_warpcore_read_status()
5716 (phy->supported & SUPPORTED_20000baseMLD2_Full)) { in bnx2x_warpcore_read_status()
5718 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5720 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5726 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_warpcore_read_status()
5728 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5737 if (phy->supported & SUPPORTED_20000baseKR2_Full) { in bnx2x_warpcore_read_status()
5739 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5741 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5747 if (phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_warpcore_read_status()
5749 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5757 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5764 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_warpcore_read_status()
5773 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5784 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5798 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5801 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5811 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, in bnx2x_warpcore_read_status()
5815 if ((!link_up) && (phy->media_type == ETH_PHY_KR) && in bnx2x_warpcore_read_status()
5816 (!(phy->flags & FLAGS_WC_DUAL_MODE))) in bnx2x_warpcore_read_status()
5826 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; in bnx2x_set_gmii_tx_driver() local
5832 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5846 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5855 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5909 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, in bnx2x_set_preemphasis() argument
5918 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_preemphasis()
5921 phy->rx_preemphasis[i]); in bnx2x_set_preemphasis()
5926 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_preemphasis()
5929 phy->tx_preemphasis[i]); in bnx2x_set_preemphasis()
5933 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, in bnx2x_xgxs_config_init() argument
5944 bnx2x_set_preemphasis(phy, params); in bnx2x_xgxs_config_init()
5953 bnx2x_set_autoneg(phy, params, vars, 0); in bnx2x_xgxs_config_init()
5956 bnx2x_program_serdes(phy, params, vars); in bnx2x_xgxs_config_init()
5962 bnx2x_set_brcm_cl37_advertisement(phy, params); in bnx2x_xgxs_config_init()
5965 bnx2x_set_ieee_aneg_advertisement(phy, params, in bnx2x_xgxs_config_init()
5969 bnx2x_set_autoneg(phy, params, vars, enable_cl73); in bnx2x_xgxs_config_init()
5972 bnx2x_restart_autoneg(phy, params, enable_cl73); in bnx2x_xgxs_config_init()
5978 bnx2x_initialize_sgmii_process(phy, params, vars); in bnx2x_xgxs_config_init()
5982 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, in bnx2x_prepare_xgxs() argument
5988 if ((phy->req_line_speed && in bnx2x_prepare_xgxs()
5989 ((phy->req_line_speed == SPEED_100) || in bnx2x_prepare_xgxs()
5990 (phy->req_line_speed == SPEED_10))) || in bnx2x_prepare_xgxs()
5991 (!phy->req_line_speed && in bnx2x_prepare_xgxs()
5992 (phy->speed_cap_mask >= in bnx2x_prepare_xgxs()
5994 (phy->speed_cap_mask < in bnx2x_prepare_xgxs()
5996 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) in bnx2x_prepare_xgxs()
6001 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_prepare_xgxs()
6002 bnx2x_set_aer_mmd(params, phy); in bnx2x_prepare_xgxs()
6003 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in bnx2x_prepare_xgxs()
6004 bnx2x_set_master_ln(params, phy); in bnx2x_prepare_xgxs()
6006 rc = bnx2x_reset_unicore(params, phy, 0); in bnx2x_prepare_xgxs()
6011 bnx2x_set_aer_mmd(params, phy); in bnx2x_prepare_xgxs()
6013 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { in bnx2x_prepare_xgxs()
6014 bnx2x_set_master_ln(params, phy); in bnx2x_prepare_xgxs()
6015 bnx2x_set_swap_lanes(params, phy); in bnx2x_prepare_xgxs()
6022 struct bnx2x_phy *phy, in bnx2x_wait_reset_complete() argument
6028 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) in bnx2x_wait_reset_complete()
6029 bnx2x_cl22_read(bp, phy, in bnx2x_wait_reset_complete()
6032 bnx2x_cl45_read(bp, phy, in bnx2x_wait_reset_complete()
6064 params->phy[INT_PHY].type != in bnx2x_link_int_enable()
6074 params->phy[INT_PHY].type != in bnx2x_link_int_enable()
6230 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); in bnx2x_get_ext_phy_fw_version()
6232 if (params->phy[EXT_PHY1].format_fw_ver) { in bnx2x_get_ext_phy_fw_version()
6233 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, in bnx2x_get_ext_phy_fw_version()
6239 (params->phy[EXT_PHY2].ver_addr != 0)) { in bnx2x_get_ext_phy_fw_version()
6240 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); in bnx2x_get_ext_phy_fw_version()
6241 if (params->phy[EXT_PHY2].format_fw_ver) { in bnx2x_get_ext_phy_fw_version()
6245 status |= params->phy[EXT_PHY2].format_fw_ver( in bnx2x_get_ext_phy_fw_version()
6256 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, in bnx2x_set_xgxs_loopback() argument
6262 if (phy->req_line_speed != SPEED_1000) { in bnx2x_set_xgxs_loopback()
6276 bnx2x_cl45_write(bp, phy, in bnx2x_set_xgxs_loopback()
6282 bnx2x_cl45_write(bp, phy, in bnx2x_set_xgxs_loopback()
6289 bnx2x_set_aer_mmd(params, phy); in bnx2x_set_xgxs_loopback()
6299 bnx2x_cl45_read(bp, phy, 5, in bnx2x_set_xgxs_loopback()
6303 bnx2x_cl45_write(bp, phy, 5, in bnx2x_set_xgxs_loopback()
6326 if (params->phy[phy_idx].set_link_led) { in bnx2x_set_led()
6327 params->phy[phy_idx].set_link_led( in bnx2x_set_led()
6328 ¶ms->phy[phy_idx], params, mode); in bnx2x_set_led()
6340 if (params->phy[EXT_PHY1].type == in bnx2x_set_led()
6358 if (((params->phy[EXT_PHY1].type == in bnx2x_set_led()
6360 (params->phy[EXT_PHY1].type == in bnx2x_set_led()
6396 } else if ((params->phy[EXT_PHY1].type == in bnx2x_set_led()
6466 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; in bnx2x_test_link()
6508 ext_phy_link_up = params->phy[EXT_PHY1].read_status( in bnx2x_test_link()
6509 ¶ms->phy[EXT_PHY1], in bnx2x_test_link()
6515 serdes_phy_type = ((params->phy[phy_index].media_type == in bnx2x_test_link()
6517 (params->phy[phy_index].media_type == in bnx2x_test_link()
6519 (params->phy[phy_index].media_type == in bnx2x_test_link()
6521 (params->phy[phy_index].media_type == in bnx2x_test_link()
6526 if (params->phy[phy_index].read_status) { in bnx2x_test_link()
6528 params->phy[phy_index].read_status( in bnx2x_test_link()
6529 ¶ms->phy[phy_index], in bnx2x_test_link()
6550 vars->line_speed = params->phy[INT_PHY].req_line_speed; in bnx2x_link_initialize()
6557 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); in bnx2x_link_initialize()
6563 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || in bnx2x_link_initialize()
6565 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; in bnx2x_link_initialize() local
6569 bnx2x_set_parallel_detection(phy, params); in bnx2x_link_initialize()
6570 if (params->phy[INT_PHY].config_init) in bnx2x_link_initialize()
6571 params->phy[INT_PHY].config_init(phy, params, vars); in bnx2x_link_initialize()
6577 vars->line_speed = params->phy[INT_PHY].req_line_speed; in bnx2x_link_initialize()
6581 if (params->phy[INT_PHY].supported & in bnx2x_link_initialize()
6592 if (params->phy[phy_index].supported & in bnx2x_link_initialize()
6603 params->phy[phy_index].config_init( in bnx2x_link_initialize()
6604 ¶ms->phy[phy_index], in bnx2x_link_initialize()
6618 static void bnx2x_int_link_reset(struct bnx2x_phy *phy, in bnx2x_int_link_reset() argument
6626 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, in bnx2x_common_ext_link_reset() argument
6774 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { in bnx2x_update_link_up()
6841 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); in bnx2x_link_update()
6871 struct bnx2x_phy *phy = ¶ms->phy[phy_index]; in bnx2x_link_update() local
6872 if (!phy->read_status) in bnx2x_link_update()
6875 cur_link_up = phy->read_status(phy, params, in bnx2x_link_update()
6929 if (params->phy[INT_PHY].read_status) in bnx2x_link_update()
6930 params->phy[INT_PHY].read_status( in bnx2x_link_update()
6931 ¶ms->phy[INT_PHY], in bnx2x_link_update()
6951 if (params->phy[EXT_PHY2].phy_specific_func) { in bnx2x_link_update()
6954 params->phy[EXT_PHY2].phy_specific_func( in bnx2x_link_update()
6955 ¶ms->phy[EXT_PHY2], in bnx2x_link_update()
6962 if (params->phy[active_external_phy].supported & in bnx2x_link_update()
6976 if (params->phy[phy_index].flags & in bnx2x_link_update()
7023 params->phy[EXT_PHY1].flags & in bnx2x_link_update()
7025 if (!(params->phy[EXT_PHY1].flags & in bnx2x_link_update()
7034 if (params->phy[INT_PHY].config_init) in bnx2x_link_update()
7035 params->phy[INT_PHY].config_init( in bnx2x_link_update()
7036 ¶ms->phy[INT_PHY], params, in bnx2x_link_update()
7092 struct bnx2x_phy *phy, in bnx2x_save_bcm_spirom_ver() argument
7097 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_save_bcm_spirom_ver()
7099 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_save_bcm_spirom_ver()
7102 phy->ver_addr); in bnx2x_save_bcm_spirom_ver()
7106 struct bnx2x_phy *phy, in bnx2x_ext_phy_10G_an_resolve() argument
7110 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_10G_an_resolve()
7113 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_10G_an_resolve()
7125 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, in bnx2x_8073_resolve_fc() argument
7130 if (phy->req_line_speed == SPEED_10 || in bnx2x_8073_resolve_fc()
7131 phy->req_line_speed == SPEED_100) { in bnx2x_8073_resolve_fc()
7132 vars->flow_ctrl = phy->req_flow_ctrl; in bnx2x_8073_resolve_fc()
7136 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && in bnx2x_8073_resolve_fc()
7141 bnx2x_cl45_read(bp, phy, in bnx2x_8073_resolve_fc()
7145 bnx2x_cl45_read(bp, phy, in bnx2x_8073_resolve_fc()
7153 bnx2x_pause_resolve(phy, params, vars, pause_result); in bnx2x_8073_resolve_fc()
7159 struct bnx2x_phy *phy, in bnx2x_8073_8727_external_rom_boot() argument
7168 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7174 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7179 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7184 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7190 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7210 bnx2x_cl45_read(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7213 bnx2x_cl45_read(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7219 ((fw_msgout & 0xff) != 0x03 && (phy->type == in bnx2x_8073_8727_external_rom_boot()
7223 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7226 bnx2x_save_bcm_spirom_ver(bp, phy, port); in bnx2x_8073_8727_external_rom_boot()
7239 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_8073_is_snr_needed() argument
7245 bnx2x_cl45_read(bp, phy, in bnx2x_8073_is_snr_needed()
7254 bnx2x_cl45_read(bp, phy, in bnx2x_8073_is_snr_needed()
7265 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_8073_xaui_wa() argument
7269 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7284 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7303 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7321 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_807x_force_10G() argument
7324 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7326 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7328 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7330 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7335 struct bnx2x_phy *phy, in bnx2x_8073_set_pause_cl37() argument
7340 bnx2x_cl45_read(bp, phy, in bnx2x_8073_set_pause_cl37()
7345 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_8073_set_pause_cl37()
7364 bnx2x_cl45_write(bp, phy, in bnx2x_8073_set_pause_cl37()
7369 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, in bnx2x_8073_specific_func() argument
7377 bnx2x_cl45_write(bp, phy, in bnx2x_8073_specific_func()
7379 bnx2x_cl45_write(bp, phy, in bnx2x_8073_specific_func()
7385 static int bnx2x_8073_config_init(struct bnx2x_phy *phy, in bnx2x_8073_config_init() argument
7405 bnx2x_8073_specific_func(phy, params, PHY_INIT); in bnx2x_8073_config_init()
7406 bnx2x_8073_set_pause_cl37(params, phy, vars); in bnx2x_8073_config_init()
7408 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7411 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7421 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7424 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7437 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7440 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7446 bnx2x_807x_force_10G(bp, phy); in bnx2x_8073_config_init()
7450 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7453 if (phy->req_line_speed != SPEED_AUTO_NEG) { in bnx2x_8073_config_init()
7454 if (phy->req_line_speed == SPEED_10000) { in bnx2x_8073_config_init()
7456 } else if (phy->req_line_speed == SPEED_2500) { in bnx2x_8073_config_init()
7465 if (phy->speed_cap_mask & in bnx2x_8073_config_init()
7470 if (phy->speed_cap_mask & in bnx2x_8073_config_init()
7477 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); in bnx2x_8073_config_init()
7478 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); in bnx2x_8073_config_init()
7480 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && in bnx2x_8073_config_init()
7481 (phy->req_line_speed == SPEED_AUTO_NEG)) || in bnx2x_8073_config_init()
7482 (phy->req_line_speed == SPEED_2500)) { in bnx2x_8073_config_init()
7485 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7498 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); in bnx2x_8073_config_init()
7501 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); in bnx2x_8073_config_init()
7502 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, in bnx2x_8073_config_init()
7503 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? in bnx2x_8073_config_init()
7507 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); in bnx2x_8073_config_init()
7513 if (bnx2x_8073_is_snr_needed(bp, phy)) in bnx2x_8073_config_init()
7514 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7519 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); in bnx2x_8073_config_init()
7521 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); in bnx2x_8073_config_init()
7523 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_8073_config_init()
7527 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in bnx2x_8073_config_init()
7533 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, in bnx2x_8073_read_status() argument
7543 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7549 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7551 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7555 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7559 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7565 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7569 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7571 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7577 ((phy->req_line_speed != SPEED_10000))) { in bnx2x_8073_read_status()
7578 if (bnx2x_8073_xaui_wa(bp, phy) != 0) in bnx2x_8073_read_status()
7581 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7583 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7587 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7589 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7595 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { in bnx2x_8073_read_status()
7600 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7605 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7609 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7640 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7653 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7658 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_8073_read_status()
7659 bnx2x_8073_resolve_fc(phy, params, vars); in bnx2x_8073_read_status()
7664 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_8073_read_status()
7678 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, in bnx2x_8073_link_reset() argument
7697 static int bnx2x_8705_config_init(struct bnx2x_phy *phy, in bnx2x_8705_config_init() argument
7708 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8705_config_init()
7709 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8705_config_init()
7711 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7713 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7715 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7717 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7724 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, in bnx2x_8705_read_status() argument
7732 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7736 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7740 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7743 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7745 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7752 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_8705_read_status()
7761 struct bnx2x_phy *phy, in bnx2x_set_disable_pmd_transmit() argument
7778 bnx2x_cl45_write(bp, phy, in bnx2x_set_disable_pmd_transmit()
7798 struct bnx2x_phy *phy, in bnx2x_sfp_e1e2_set_transmitter() argument
7816 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_e1e2_set_transmitter()
7826 bnx2x_cl45_write(bp, phy, in bnx2x_sfp_e1e2_set_transmitter()
7855 struct bnx2x_phy *phy, in bnx2x_sfp_set_transmitter() argument
7861 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); in bnx2x_sfp_set_transmitter()
7863 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); in bnx2x_sfp_set_transmitter()
7866 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, in bnx2x_8726_read_sfp_module_eeprom() argument
7880 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7885 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7890 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7896 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7915 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7922 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7954 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, in bnx2x_warpcore_read_sfp_module_eeprom() argument
7995 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, in bnx2x_8727_read_sfp_module_eeprom() argument
8013 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8019 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8025 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8031 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8036 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8042 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8053 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8072 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8079 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8090 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, in bnx2x_read_sfp_module_eeprom() argument
8105 switch (phy->type) { in bnx2x_read_sfp_module_eeprom()
8123 rc = read_func(phy, params, dev_addr, addr, xfer_size, in bnx2x_read_sfp_module_eeprom()
8132 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, in bnx2x_get_edc_mode() argument
8140 phy->media_type = ETH_PHY_UNSPECIFIED; in bnx2x_get_edc_mode()
8142 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_get_edc_mode()
8159 phy->media_type = ETH_PHY_DA_TWINAX; in bnx2x_get_edc_mode()
8168 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in bnx2x_get_edc_mode()
8199 phy->media_type = ETH_PHY_SFP_1G_FIBER; in bnx2x_get_edc_mode()
8200 if (phy->req_line_speed != SPEED_1000) { in bnx2x_get_edc_mode()
8202 phy->req_line_speed = SPEED_1000; in bnx2x_get_edc_mode()
8213 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_get_edc_mode()
8215 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_get_edc_mode()
8221 if (params->phy[idx].type == phy->type) { in bnx2x_get_edc_mode()
8226 phy->media_type = ETH_PHY_SFPP_10G_FIBER; in bnx2x_get_edc_mode()
8227 phy->req_line_speed = params->req_line_speed[cfg_idx]; in bnx2x_get_edc_mode()
8241 if (&(params->phy[phy_idx]) == phy) { in bnx2x_get_edc_mode()
8244 media_types |= ((phy->media_type & in bnx2x_get_edc_mode()
8253 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_get_edc_mode()
8274 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, in bnx2x_verify_sfp_module() argument
8282 phy->flags &= ~FLAGS_SFP_NOT_APPROVED; in bnx2x_verify_sfp_module()
8312 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); in bnx2x_verify_sfp_module()
8320 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_verify_sfp_module()
8329 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_verify_sfp_module()
8344 phy->flags |= FLAGS_SFP_NOT_APPROVED; in bnx2x_verify_sfp_module()
8348 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, in bnx2x_wait_for_sfp_module_initialized() argument
8361 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in bnx2x_wait_for_sfp_module_initialized()
8363 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, in bnx2x_wait_for_sfp_module_initialized()
8366 rc = bnx2x_read_sfp_module_eeprom(phy, params, in bnx2x_wait_for_sfp_module_initialized()
8377 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0, in bnx2x_wait_for_sfp_module_initialized()
8383 struct bnx2x_phy *phy, in bnx2x_8727_power_module() argument
8398 if (phy->flags & FLAGS_NOC) in bnx2x_8727_power_module()
8408 bnx2x_cl45_write(bp, phy, in bnx2x_8727_power_module()
8415 struct bnx2x_phy *phy, in bnx2x_8726_set_limiting_mode() argument
8420 bnx2x_cl45_read(bp, phy, in bnx2x_8726_set_limiting_mode()
8429 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8443 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8447 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8451 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8455 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8464 struct bnx2x_phy *phy, in bnx2x_8727_set_limiting_mode() argument
8469 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_limiting_mode()
8474 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8479 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_limiting_mode()
8484 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8489 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8497 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, in bnx2x_8727_specific_func() argument
8505 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_8727_specific_func()
8508 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) in bnx2x_8727_specific_func()
8509 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_8727_specific_func()
8512 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8515 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8518 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8521 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_specific_func()
8525 if (phy->flags & FLAGS_NOC) in bnx2x_8727_specific_func()
8530 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_specific_func()
8532 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8605 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, in bnx2x_warpcore_hw_reset() argument
8620 struct bnx2x_phy *phy, in bnx2x_power_sfp_module() argument
8626 switch (phy->type) { in bnx2x_power_sfp_module()
8629 bnx2x_8727_power_module(params->bp, phy, power); in bnx2x_power_sfp_module()
8639 struct bnx2x_phy *phy, in bnx2x_warpcore_set_limiting_mode() argument
8646 u8 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_set_limiting_mode()
8648 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8666 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8669 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8673 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_set_limiting_mode()
8674 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_set_limiting_mode()
8679 struct bnx2x_phy *phy, in bnx2x_set_limiting_mode() argument
8682 switch (phy->type) { in bnx2x_set_limiting_mode()
8684 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8688 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8691 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); in bnx2x_set_limiting_mode()
8696 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, in bnx2x_sfp_module_detection() argument
8707 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_sfp_module_detection()
8711 bnx2x_power_sfp_module(params, phy, 1); in bnx2x_sfp_module_detection()
8712 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { in bnx2x_sfp_module_detection()
8715 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { in bnx2x_sfp_module_detection()
8727 bnx2x_power_sfp_module(params, phy, 0); in bnx2x_sfp_module_detection()
8738 bnx2x_set_limiting_mode(params, phy, edc_mode); in bnx2x_sfp_module_detection()
8746 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_sfp_module_detection()
8754 struct bnx2x_phy *phy; in bnx2x_handle_module_detect_int() local
8758 phy = ¶ms->phy[INT_PHY]; in bnx2x_handle_module_detect_int()
8760 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_handle_module_detect_int()
8762 phy = ¶ms->phy[EXT_PHY1]; in bnx2x_handle_module_detect_int()
8780 bnx2x_set_aer_mmd(params, phy); in bnx2x_handle_module_detect_int()
8782 bnx2x_power_sfp_module(params, phy, 1); in bnx2x_handle_module_detect_int()
8786 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { in bnx2x_handle_module_detect_int()
8787 bnx2x_sfp_module_detection(phy, params); in bnx2x_handle_module_detect_int()
8794 bnx2x_cl45_read(bp, phy, in bnx2x_handle_module_detect_int()
8801 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_handle_module_detect_int()
8802 bnx2x_warpcore_config_sfi(phy, params); in bnx2x_handle_module_detect_int()
8803 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_handle_module_detect_int()
8816 phy->media_type = ETH_PHY_NOT_PRESENT; in bnx2x_handle_module_detect_int()
8824 struct bnx2x_phy *phy, in bnx2x_sfp_mask_fault() argument
8829 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_mask_fault()
8832 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_mask_fault()
8836 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); in bnx2x_sfp_mask_fault()
8841 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); in bnx2x_sfp_mask_fault()
8846 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, in bnx2x_8706_8726_read_status() argument
8855 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8858 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, in bnx2x_8706_8726_read_status()
8862 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8864 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8868 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8870 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8872 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8874 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8888 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_8706_8726_read_status()
8894 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8706_8726_read_status()
8896 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8706_8726_read_status()
8908 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, in bnx2x_8706_config_init() argument
8920 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8706_config_init()
8921 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8706_config_init()
8925 bnx2x_cl45_read(bp, phy, in bnx2x_8706_config_init()
8940 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); in bnx2x_8706_config_init()
8944 val |= (phy->rx_preemphasis[i] & 0x7); in bnx2x_8706_config_init()
8947 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); in bnx2x_8706_config_init()
8951 if (phy->req_line_speed == SPEED_10000) { in bnx2x_8706_config_init()
8954 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8957 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8961 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8968 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8972 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8975 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8978 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8982 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8984 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8987 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8991 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8706_config_init()
9004 bnx2x_cl45_read(bp, phy, in bnx2x_8706_config_init()
9007 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
9014 static int bnx2x_8706_read_status(struct bnx2x_phy *phy, in bnx2x_8706_read_status() argument
9018 return bnx2x_8706_8726_read_status(phy, params, vars); in bnx2x_8706_read_status()
9024 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, in bnx2x_8726_config_loopback() argument
9029 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); in bnx2x_8726_config_loopback()
9032 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, in bnx2x_8726_external_rom_boot() argument
9040 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9044 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9049 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9053 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9062 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9067 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8726_external_rom_boot()
9070 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, in bnx2x_8726_read_status() argument
9076 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); in bnx2x_8726_read_status()
9078 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_status()
9091 static int bnx2x_8726_config_init(struct bnx2x_phy *phy, in bnx2x_8726_config_init() argument
9098 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in bnx2x_8726_config_init()
9099 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8726_config_init()
9101 bnx2x_8726_external_rom_boot(phy, params); in bnx2x_8726_config_init()
9108 bnx2x_sfp_module_detection(phy, params); in bnx2x_8726_config_init()
9110 if (phy->req_line_speed == SPEED_1000) { in bnx2x_8726_config_init()
9112 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9114 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9116 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9118 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9121 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_8726_config_init()
9122 (phy->speed_cap_mask & in bnx2x_8726_config_init()
9124 ((phy->speed_cap_mask & in bnx2x_8726_config_init()
9129 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_8726_config_init()
9130 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9132 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9134 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9136 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9138 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9143 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9145 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9150 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9159 phy->tx_preemphasis[0], in bnx2x_8726_config_init()
9160 phy->tx_preemphasis[1]); in bnx2x_8726_config_init()
9161 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9164 phy->tx_preemphasis[0]); in bnx2x_8726_config_init()
9166 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9169 phy->tx_preemphasis[1]); in bnx2x_8726_config_init()
9176 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, in bnx2x_8726_link_reset() argument
9182 bnx2x_cl45_write(bp, phy, in bnx2x_8726_link_reset()
9191 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, in bnx2x_8727_set_link_led() argument
9199 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_set_link_led()
9216 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_link_led()
9222 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_link_led()
9226 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_link_led()
9232 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_link_led()
9237 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, in bnx2x_8727_hw_reset() argument
9252 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, in bnx2x_8727_config_speed() argument
9258 if ((phy->req_line_speed == SPEED_1000) || in bnx2x_8727_config_speed()
9259 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { in bnx2x_8727_config_speed()
9261 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9263 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9265 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_speed()
9272 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_speed()
9276 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9280 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_8727_config_speed()
9281 ((phy->speed_cap_mask & in bnx2x_8727_config_speed()
9283 ((phy->speed_cap_mask & in bnx2x_8727_config_speed()
9288 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9290 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9296 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9299 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9301 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9303 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9309 static int bnx2x_8727_config_init(struct bnx2x_phy *phy, in bnx2x_8727_config_init() argument
9318 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8727_config_init()
9322 bnx2x_8727_specific_func(phy, params, PHY_INIT); in bnx2x_8727_config_init()
9326 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9333 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_config_init()
9335 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9339 bnx2x_set_disable_pmd_transmit(params, phy, 0); in bnx2x_8727_config_init()
9341 bnx2x_8727_power_module(bp, phy, 1); in bnx2x_8727_config_init()
9343 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9346 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9349 bnx2x_8727_config_speed(phy, params); in bnx2x_8727_config_init()
9356 phy->tx_preemphasis[0], in bnx2x_8727_config_init()
9357 phy->tx_preemphasis[1]); in bnx2x_8727_config_init()
9358 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9360 phy->tx_preemphasis[0]); in bnx2x_8727_config_init()
9362 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9364 phy->tx_preemphasis[1]); in bnx2x_8727_config_init()
9378 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9382 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9384 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9387 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9395 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, in bnx2x_8727_handle_mod_abs() argument
9404 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9412 phy->media_type = ETH_PHY_NOT_PRESENT; in bnx2x_8727_handle_mod_abs()
9421 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_handle_mod_abs()
9423 bnx2x_cl45_write(bp, phy, in bnx2x_8727_handle_mod_abs()
9430 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9446 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_handle_mod_abs()
9448 bnx2x_cl45_write(bp, phy, in bnx2x_8727_handle_mod_abs()
9457 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9464 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_8727_handle_mod_abs()
9466 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) in bnx2x_8727_handle_mod_abs()
9467 bnx2x_sfp_module_detection(phy, params); in bnx2x_8727_handle_mod_abs()
9472 bnx2x_8727_config_speed(phy, params); in bnx2x_8727_handle_mod_abs()
9480 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, in bnx2x_8727_read_status() argument
9491 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9498 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9504 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, in bnx2x_8727_read_status()
9507 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9513 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9519 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { in bnx2x_8727_read_status()
9521 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9540 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9544 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9549 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9553 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9556 bnx2x_8727_power_module(params->bp, phy, 0); in bnx2x_8727_read_status()
9563 bnx2x_8727_handle_mod_abs(phy, params); in bnx2x_8727_read_status()
9565 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9570 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { in bnx2x_8727_read_status()
9572 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_8727_read_status()
9578 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9603 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_read_status()
9606 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_read_status()
9615 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_8727_read_status()
9621 (phy->req_line_speed == SPEED_1000)) { in bnx2x_8727_read_status()
9622 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9632 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9639 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, in bnx2x_8727_link_reset() argument
9645 bnx2x_set_disable_pmd_transmit(params, phy, 1); in bnx2x_8727_link_reset()
9648 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_8727_link_reset()
9650 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); in bnx2x_8727_link_reset()
9657 static int bnx2x_is_8483x_8485x(struct bnx2x_phy *phy) in bnx2x_is_8483x_8485x() argument
9659 return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_is_8483x_8485x()
9660 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) || in bnx2x_is_8483x_8485x()
9661 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)); in bnx2x_is_8483x_8485x()
9664 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, in bnx2x_save_848xx_spirom_version() argument
9678 if (bnx2x_is_8483x_8485x(phy)) { in bnx2x_save_848xx_spirom_version()
9679 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9681 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9686 bnx2x_cl45_write(bp, phy, reg_set[i].devad, in bnx2x_save_848xx_spirom_version()
9690 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9699 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9705 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); in bnx2x_save_848xx_spirom_version()
9706 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); in bnx2x_save_848xx_spirom_version()
9707 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); in bnx2x_save_848xx_spirom_version()
9709 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9718 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9723 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9725 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); in bnx2x_save_848xx_spirom_version()
9728 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9733 struct bnx2x_phy *phy) in bnx2x_848xx_set_led() argument
9746 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_led()
9752 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_led()
9757 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_848xx_set_led()
9760 if (bnx2x_is_8483x_8485x(phy)) in bnx2x_848xx_set_led()
9766 bnx2x_cl45_read_or_write(bp, phy, in bnx2x_848xx_set_led()
9771 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, in bnx2x_848xx_specific_func() argument
9778 if (!bnx2x_is_8483x_8485x(phy)) { in bnx2x_848xx_specific_func()
9780 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848xx_specific_func()
9789 bnx2x_848xx_set_led(bp, phy); in bnx2x_848xx_specific_func()
9794 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, in bnx2x_848xx_cmn_config_init() argument
9801 bnx2x_848xx_specific_func(phy, params, PHY_INIT); in bnx2x_848xx_cmn_config_init()
9802 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9806 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9810 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_848xx_cmn_config_init()
9811 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9815 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9822 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_848xx_cmn_config_init()
9823 (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9825 (phy->req_line_speed == SPEED_1000)) { in bnx2x_848xx_cmn_config_init()
9828 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_848xx_cmn_config_init()
9834 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9839 if (phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_848xx_cmn_config_init()
9840 if (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9849 if (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9858 if ((phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9860 (phy->supported & SUPPORTED_10baseT_Full)) { in bnx2x_848xx_cmn_config_init()
9866 if ((phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9868 (phy->supported & SUPPORTED_10baseT_Half)) { in bnx2x_848xx_cmn_config_init()
9876 if ((phy->req_line_speed == SPEED_100) && in bnx2x_848xx_cmn_config_init()
9877 (phy->supported & in bnx2x_848xx_cmn_config_init()
9882 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9889 if ((phy->req_line_speed == SPEED_10) && in bnx2x_848xx_cmn_config_init()
9890 (phy->supported & in bnx2x_848xx_cmn_config_init()
9894 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9900 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9904 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_848xx_cmn_config_init()
9910 if (!bnx2x_is_8483x_8485x(phy) || in bnx2x_848xx_cmn_config_init()
9912 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9916 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_848xx_cmn_config_init()
9917 (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9919 (phy->req_line_speed == SPEED_10000)) { in bnx2x_848xx_cmn_config_init()
9924 bp, phy, in bnx2x_848xx_cmn_config_init()
9928 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9932 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9940 static int bnx2x_8481_config_init(struct bnx2x_phy *phy, in bnx2x_8481_config_init() argument
9951 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8481_config_init()
9953 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in bnx2x_8481_config_init()
9954 return bnx2x_848xx_cmn_config_init(phy, params, vars); in bnx2x_8481_config_init()
9960 static int bnx2x_84858_cmd_hdlr(struct bnx2x_phy *phy, in bnx2x_84858_cmd_hdlr() argument
9977 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84858_cmd_hdlr()
9994 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84858_cmd_hdlr()
10002 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84858_cmd_hdlr()
10011 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84858_cmd_hdlr()
10029 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84858_cmd_hdlr()
10037 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, in bnx2x_84833_cmd_hdlr() argument
10045 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10049 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10062 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10066 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10069 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10083 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10087 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
10093 static int bnx2x_848xx_cmd_hdlr(struct bnx2x_phy *phy, in bnx2x_848xx_cmd_hdlr() argument
10100 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) || in bnx2x_848xx_cmd_hdlr()
10105 return bnx2x_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args, in bnx2x_848xx_cmd_hdlr()
10108 return bnx2x_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args, in bnx2x_848xx_cmd_hdlr()
10113 static int bnx2x_848xx_pair_swap_cfg(struct bnx2x_phy *phy, in bnx2x_848xx_pair_swap_cfg() argument
10134 status = bnx2x_848xx_cmd_hdlr(phy, params, in bnx2x_848xx_pair_swap_cfg()
10181 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, in bnx2x_84833_hw_reset_phy() argument
10193 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_84833_hw_reset_phy()
10196 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_84833_hw_reset_phy()
10214 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, in bnx2x_8483x_disable_eee() argument
10225 rc = bnx2x_848xx_cmd_hdlr(phy, params, in bnx2x_8483x_disable_eee()
10232 return bnx2x_eee_disable(phy, params, vars); in bnx2x_8483x_disable_eee()
10235 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, in bnx2x_8483x_enable_eee() argument
10243 rc = bnx2x_848xx_cmd_hdlr(phy, params, in bnx2x_8483x_enable_eee()
10250 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); in bnx2x_8483x_enable_eee()
10254 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, in bnx2x_848x3_config_init() argument
10272 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in bnx2x_848x3_config_init()
10278 bnx2x_cl45_write(bp, phy, in bnx2x_848x3_config_init()
10283 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_848x3_config_init()
10287 if (!bnx2x_is_8483x_8485x(phy)) { in bnx2x_848x3_config_init()
10294 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); in bnx2x_848x3_config_init()
10295 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); in bnx2x_848x3_config_init()
10299 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { in bnx2x_848x3_config_init()
10302 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848x3_config_init()
10311 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10347 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) in bnx2x_848x3_config_init()
10350 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10355 if (bnx2x_is_8483x_8485x(phy)) { in bnx2x_848x3_config_init()
10356 bnx2x_848xx_pair_swap_cfg(phy, params, vars); in bnx2x_848x3_config_init()
10363 rc = bnx2x_848xx_cmd_hdlr(phy, params, in bnx2x_848x3_config_init()
10370 rc = bnx2x_848xx_cmn_config_init(phy, params, vars); in bnx2x_848x3_config_init()
10372 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848x3_config_init()
10374 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in bnx2x_848x3_config_init()
10380 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10386 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10390 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10400 bnx2x_8483x_disable_eee(phy, params, vars); in bnx2x_848x3_config_init()
10404 if ((phy->req_duplex == DUPLEX_FULL) && in bnx2x_848x3_config_init()
10408 rc = bnx2x_8483x_enable_eee(phy, params, vars); in bnx2x_848x3_config_init()
10410 rc = bnx2x_8483x_disable_eee(phy, params, vars); in bnx2x_848x3_config_init()
10419 if (bnx2x_is_8483x_8485x(phy)) { in bnx2x_848x3_config_init()
10421 bnx2x_cl45_read_and_write(bp, phy, in bnx2x_848x3_config_init()
10429 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, in bnx2x_848xx_read_status() argument
10440 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10442 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10452 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_848xx_read_status()
10457 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_read_status()
10462 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10493 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10500 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10512 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_848xx_read_status()
10515 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10533 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10543 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10551 if (bnx2x_is_8483x_8485x(phy)) in bnx2x_848xx_read_status()
10552 bnx2x_eee_an_resolve(phy, params, vars); in bnx2x_848xx_read_status()
10567 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, in bnx2x_8481_hw_reset() argument
10576 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, in bnx2x_8481_link_reset() argument
10579 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10581 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10585 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, in bnx2x_848x3_link_reset() argument
10597 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in bnx2x_848x3_link_reset()
10602 bnx2x_cl45_read(bp, phy, in bnx2x_848x3_link_reset()
10606 bnx2x_cl45_write(bp, phy, in bnx2x_848x3_link_reset()
10612 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, in bnx2x_848xx_set_link_led() argument
10633 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10638 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10643 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10648 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10654 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10669 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10674 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10679 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10684 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10690 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10694 if (phy->type == in bnx2x_848xx_set_link_led()
10711 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10725 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10732 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10738 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10743 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10748 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10753 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10758 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10762 if (phy->type == in bnx2x_848xx_set_link_led()
10779 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10795 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10804 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10811 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10816 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10821 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10826 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10840 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10846 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10852 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10856 if (phy->type == in bnx2x_848xx_set_link_led()
10861 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10880 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_848xx_set_link_led()
10888 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, in bnx2x_54618se_specific_func() argument
10898 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10901 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_specific_func()
10906 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10910 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10917 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, in bnx2x_54618se_config_init() argument
10947 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10949 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_54618se_config_init()
10955 bnx2x_54618se_specific_func(phy, params, PHY_INIT); in bnx2x_54618se_config_init()
10957 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10960 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10964 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10970 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_54618se_config_init()
10981 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10985 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10989 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10998 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_54618se_config_init()
10999 (phy->speed_cap_mask & in bnx2x_54618se_config_init()
11001 (phy->req_line_speed == SPEED_1000)) { in bnx2x_54618se_config_init()
11004 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_54618se_config_init()
11010 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
11013 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
11018 if (phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_54618se_config_init()
11019 if (phy->speed_cap_mask & in bnx2x_54618se_config_init()
11025 if (phy->speed_cap_mask & in bnx2x_54618se_config_init()
11031 if (phy->speed_cap_mask & in bnx2x_54618se_config_init()
11037 if (phy->speed_cap_mask & in bnx2x_54618se_config_init()
11046 if (phy->req_line_speed == SPEED_100) { in bnx2x_54618se_config_init()
11049 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
11054 if (phy->req_line_speed == SPEED_10) { in bnx2x_54618se_config_init()
11056 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
11062 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { in bnx2x_54618se_config_init()
11065 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, in bnx2x_54618se_config_init()
11068 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); in bnx2x_54618se_config_init()
11070 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); in bnx2x_54618se_config_init()
11075 bnx2x_eee_disable(phy, params, vars); in bnx2x_54618se_config_init()
11077 (phy->req_duplex == DUPLEX_FULL) && in bnx2x_54618se_config_init()
11085 bnx2x_eee_advertise(phy, params, vars, in bnx2x_54618se_config_init()
11089 bnx2x_eee_disable(phy, params, vars); in bnx2x_54618se_config_init()
11095 if (phy->flags & FLAGS_EEE) { in bnx2x_54618se_config_init()
11105 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_54618se_config_init()
11110 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
11114 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_54618se_config_init()
11117 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
11124 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, in bnx2x_5461x_set_link_led() argument
11130 bnx2x_cl22_write(bp, phy, in bnx2x_5461x_set_link_led()
11133 bnx2x_cl22_read(bp, phy, in bnx2x_5461x_set_link_led()
11153 bnx2x_cl22_write(bp, phy, in bnx2x_5461x_set_link_led()
11160 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, in bnx2x_54618se_link_reset() argument
11170 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); in bnx2x_54618se_link_reset()
11185 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, in bnx2x_54618se_read_status() argument
11195 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11201 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11238 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11244 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11254 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_54618se_read_status()
11258 bnx2x_cl22_read(bp, phy, 0x5, &val); in bnx2x_54618se_read_status()
11276 bnx2x_cl22_read(bp, phy, 0xa, &val); in bnx2x_54618se_read_status()
11284 if ((phy->flags & FLAGS_EEE) && in bnx2x_54618se_read_status()
11286 bnx2x_eee_an_resolve(phy, params, vars); in bnx2x_54618se_read_status()
11292 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, in bnx2x_54618se_config_loopback() argument
11303 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); in bnx2x_54618se_config_loopback()
11310 bnx2x_cl22_read(bp, phy, 0x00, &val); in bnx2x_54618se_config_loopback()
11313 bnx2x_cl22_write(bp, phy, 0x00, val); in bnx2x_54618se_config_loopback()
11319 bnx2x_cl22_write(bp, phy, 0x18, 7); in bnx2x_54618se_config_loopback()
11320 bnx2x_cl22_read(bp, phy, 0x18, &val); in bnx2x_54618se_config_loopback()
11321 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); in bnx2x_54618se_config_loopback()
11335 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, in bnx2x_7101_config_loopback() argument
11340 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_loopback()
11344 static int bnx2x_7101_config_init(struct bnx2x_phy *phy, in bnx2x_7101_config_init() argument
11357 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_7101_config_init()
11359 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11362 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11365 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_7101_config_init()
11367 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11370 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11374 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11377 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11380 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); in bnx2x_7101_config_init()
11384 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, in bnx2x_7101_read_status() argument
11391 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11393 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11397 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11399 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11406 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11413 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_7101_read_status()
11414 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_7101_read_status()
11437 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_sfx7101_sp_sw_reset() argument
11441 bnx2x_cl45_read(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11448 bnx2x_cl45_write(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11453 bnx2x_cl45_read(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11462 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, in bnx2x_7101_hw_reset() argument
11472 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, in bnx2x_7101_set_link_led() argument
11489 bnx2x_cl45_write(bp, phy, in bnx2x_7101_set_link_led()
12031 struct bnx2x_phy *phy, u8 port, in bnx2x_populate_preemphasis() argument
12059 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); in bnx2x_populate_preemphasis()
12060 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); in bnx2x_populate_preemphasis()
12062 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); in bnx2x_populate_preemphasis()
12063 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); in bnx2x_populate_preemphasis()
12090 struct bnx2x_phy *phy) in bnx2x_populate_int_phy() argument
12106 *phy = phy_warpcore; in bnx2x_populate_int_phy()
12108 phy->flags |= FLAGS_4_PORT_MODE; in bnx2x_populate_int_phy()
12110 phy->flags &= ~FLAGS_4_PORT_MODE; in bnx2x_populate_int_phy()
12121 phy->supported &= (SUPPORTED_10baseT_Half | in bnx2x_populate_int_phy()
12130 phy->media_type = ETH_PHY_BASE_T; in bnx2x_populate_int_phy()
12133 phy->supported &= (SUPPORTED_1000baseT_Full | in bnx2x_populate_int_phy()
12138 phy->media_type = ETH_PHY_XFP_FIBER; in bnx2x_populate_int_phy()
12141 phy->supported &= (SUPPORTED_1000baseT_Full | in bnx2x_populate_int_phy()
12146 phy->media_type = ETH_PHY_SFPP_10G_FIBER; in bnx2x_populate_int_phy()
12149 phy->media_type = ETH_PHY_KR; in bnx2x_populate_int_phy()
12150 phy->supported &= (SUPPORTED_1000baseKX_Full | in bnx2x_populate_int_phy()
12158 phy->media_type = ETH_PHY_KR; in bnx2x_populate_int_phy()
12159 phy->flags |= FLAGS_WC_DUAL_MODE; in bnx2x_populate_int_phy()
12160 phy->supported &= (SUPPORTED_20000baseMLD2_Full | in bnx2x_populate_int_phy()
12166 phy->media_type = ETH_PHY_KR; in bnx2x_populate_int_phy()
12167 phy->flags |= FLAGS_WC_DUAL_MODE; in bnx2x_populate_int_phy()
12168 phy->supported &= (SUPPORTED_20000baseKR2_Full | in bnx2x_populate_int_phy()
12175 phy->flags &= ~FLAGS_TX_ERROR_CHECK; in bnx2x_populate_int_phy()
12188 phy->flags |= FLAGS_MDC_MDIO_WA; in bnx2x_populate_int_phy()
12190 phy->flags |= FLAGS_MDC_MDIO_WA_B0; in bnx2x_populate_int_phy()
12197 *phy = phy_serdes; in bnx2x_populate_int_phy()
12203 *phy = phy_xgxs; in bnx2x_populate_int_phy()
12210 phy->addr = (u8)phy_addr; in bnx2x_populate_int_phy()
12211 phy->mdio_ctrl = bnx2x_get_emac_base(bp, in bnx2x_populate_int_phy()
12215 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; in bnx2x_populate_int_phy()
12217 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; in bnx2x_populate_int_phy()
12220 port, phy->addr, phy->mdio_ctrl); in bnx2x_populate_int_phy()
12222 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); in bnx2x_populate_int_phy()
12231 struct bnx2x_phy *phy) in bnx2x_populate_ext_phy() argument
12242 *phy = phy_8073; in bnx2x_populate_ext_phy()
12245 *phy = phy_8705; in bnx2x_populate_ext_phy()
12248 *phy = phy_8706; in bnx2x_populate_ext_phy()
12252 *phy = phy_8726; in bnx2x_populate_ext_phy()
12257 *phy = phy_8727; in bnx2x_populate_ext_phy()
12258 phy->flags |= FLAGS_NOC; in bnx2x_populate_ext_phy()
12263 *phy = phy_8727; in bnx2x_populate_ext_phy()
12266 *phy = phy_8481; in bnx2x_populate_ext_phy()
12269 *phy = phy_84823; in bnx2x_populate_ext_phy()
12272 *phy = phy_84833; in bnx2x_populate_ext_phy()
12275 *phy = phy_84834; in bnx2x_populate_ext_phy()
12278 *phy = phy_84858; in bnx2x_populate_ext_phy()
12282 *phy = phy_54618se; in bnx2x_populate_ext_phy()
12284 phy->flags |= FLAGS_EEE; in bnx2x_populate_ext_phy()
12287 *phy = phy_7101; in bnx2x_populate_ext_phy()
12290 *phy = phy_null; in bnx2x_populate_ext_phy()
12293 *phy = phy_null; in bnx2x_populate_ext_phy()
12301 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); in bnx2x_populate_ext_phy()
12302 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); in bnx2x_populate_ext_phy()
12311 phy->ver_addr = shmem_base + offsetof(struct shmem_region, in bnx2x_populate_ext_phy()
12323 phy->ver_addr = shmem2_base + in bnx2x_populate_ext_phy()
12334 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); in bnx2x_populate_ext_phy()
12336 if (bnx2x_is_8483x_8485x(phy) && (phy->ver_addr)) { in bnx2x_populate_ext_phy()
12340 u32 raw_ver = REG_RD(bp, phy->ver_addr); in bnx2x_populate_ext_phy()
12343 phy->supported &= ~(SUPPORTED_100baseT_Half | in bnx2x_populate_ext_phy()
12350 phy->addr, phy->mdio_ctrl); in bnx2x_populate_ext_phy()
12355 u32 shmem2_base, u8 port, struct bnx2x_phy *phy) in bnx2x_populate_phy() argument
12358 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; in bnx2x_populate_phy()
12360 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); in bnx2x_populate_phy()
12362 port, phy); in bnx2x_populate_phy()
12367 struct bnx2x_phy *phy, in bnx2x_phy_def_cfg() argument
12377 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12385 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12392 phy_index, link_config, phy->speed_cap_mask); in bnx2x_phy_def_cfg()
12394 phy->req_duplex = DUPLEX_FULL; in bnx2x_phy_def_cfg()
12397 phy->req_duplex = DUPLEX_HALF; in bnx2x_phy_def_cfg()
12399 phy->req_line_speed = SPEED_10; in bnx2x_phy_def_cfg()
12402 phy->req_duplex = DUPLEX_HALF; in bnx2x_phy_def_cfg()
12404 phy->req_line_speed = SPEED_100; in bnx2x_phy_def_cfg()
12407 phy->req_line_speed = SPEED_1000; in bnx2x_phy_def_cfg()
12410 phy->req_line_speed = SPEED_2500; in bnx2x_phy_def_cfg()
12413 phy->req_line_speed = SPEED_10000; in bnx2x_phy_def_cfg()
12416 phy->req_line_speed = SPEED_AUTO_NEG; in bnx2x_phy_def_cfg()
12422 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; in bnx2x_phy_def_cfg()
12425 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; in bnx2x_phy_def_cfg()
12428 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; in bnx2x_phy_def_cfg()
12431 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; in bnx2x_phy_def_cfg()
12434 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_phy_def_cfg()
12476 struct bnx2x_phy *phy; in bnx2x_phy_probe() local
12494 phy = ¶ms->phy[actual_phy_idx]; in bnx2x_phy_probe()
12497 phy) != 0) { in bnx2x_phy_probe()
12504 *phy = phy_null; in bnx2x_phy_probe()
12507 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) in bnx2x_phy_probe()
12512 phy->flags &= ~FLAGS_TX_ERROR_CHECK; in bnx2x_phy_probe()
12516 phy->flags |= FLAGS_MDC_MDIO_WA_G; in bnx2x_phy_probe()
12530 media_types |= ((phy->media_type & in bnx2x_phy_probe()
12537 bnx2x_phy_def_cfg(params, phy, phy_index); in bnx2x_phy_probe()
12600 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); in bnx2x_init_xmac_loopback()
12601 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); in bnx2x_init_xmac_loopback()
12602 params->phy[INT_PHY].config_loopback( in bnx2x_init_xmac_loopback()
12603 ¶ms->phy[INT_PHY], in bnx2x_init_xmac_loopback()
12629 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; in bnx2x_init_xgxs_loopback()
12667 if (params->phy[phy_index].config_loopback) in bnx2x_init_xgxs_loopback()
12668 params->phy[phy_index].config_loopback( in bnx2x_init_xgxs_loopback()
12669 ¶ms->phy[phy_index], in bnx2x_init_xgxs_loopback()
12712 struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; in bnx2x_avoid_link_flap() local
12713 if (phy->phy_specific_func) { in bnx2x_avoid_link_flap()
12715 phy->phy_specific_func(phy, params, PHY_INIT); in bnx2x_avoid_link_flap()
12717 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || in bnx2x_avoid_link_flap()
12718 (phy->media_type == ETH_PHY_SFP_1G_FIBER) || in bnx2x_avoid_link_flap()
12719 (phy->media_type == ETH_PHY_DA_TWINAX)) in bnx2x_avoid_link_flap()
12720 bnx2x_verify_sfp_module(phy, params); in bnx2x_avoid_link_flap()
12968 if (params->phy[phy_index].link_reset) { in bnx2x_link_reset()
12970 ¶ms->phy[phy_index]); in bnx2x_link_reset()
12971 params->phy[phy_index].link_reset( in bnx2x_link_reset()
12972 ¶ms->phy[phy_index], in bnx2x_link_reset()
12975 if (params->phy[phy_index].flags & in bnx2x_link_reset()
12987 if (params->phy[INT_PHY].link_reset) in bnx2x_link_reset()
12988 params->phy[INT_PHY].link_reset( in bnx2x_link_reset()
12989 ¶ms->phy[INT_PHY], params); in bnx2x_link_reset()
13070 struct bnx2x_phy phy[PORT_MAX]; in bnx2x_8073_common_init_phy() local
13096 port_of_path, &phy[port]) != in bnx2x_8073_common_init_phy()
13117 bnx2x_cl45_write(bp, &phy[port], in bnx2x_8073_common_init_phy()
13126 if (phy[PORT_0].addr & 0x1) { in bnx2x_8073_common_init_phy()
13127 phy_blk[PORT_0] = &(phy[PORT_1]); in bnx2x_8073_common_init_phy()
13128 phy_blk[PORT_1] = &(phy[PORT_0]); in bnx2x_8073_common_init_phy()
13130 phy_blk[PORT_0] = &(phy[PORT_0]); in bnx2x_8073_common_init_phy()
13131 phy_blk[PORT_1] = &(phy[PORT_1]); in bnx2x_8073_common_init_phy()
13198 struct bnx2x_phy phy; in bnx2x_8726_common_init_phy() local
13221 port, &phy) != in bnx2x_8726_common_init_phy()
13228 bnx2x_cl45_write(bp, &phy, in bnx2x_8726_common_init_phy()
13293 struct bnx2x_phy phy[PORT_MAX]; in bnx2x_8727_common_init_phy() local
13337 port_of_path, &phy[port]) != in bnx2x_8727_common_init_phy()
13352 bnx2x_cl45_write(bp, &phy[port], in bnx2x_8727_common_init_phy()
13358 if (phy[PORT_0].addr & 0x1) { in bnx2x_8727_common_init_phy()
13359 phy_blk[PORT_0] = &(phy[PORT_1]); in bnx2x_8727_common_init_phy()
13360 phy_blk[PORT_1] = &(phy[PORT_0]); in bnx2x_8727_common_init_phy()
13362 phy_blk[PORT_0] = &(phy[PORT_0]); in bnx2x_8727_common_init_phy()
13363 phy_blk[PORT_1] = &(phy[PORT_1]); in bnx2x_8727_common_init_phy()
13667 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, in bnx2x_sfp_tx_fault_detection() argument
13703 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { in bnx2x_sfp_tx_fault_detection()
13712 struct bnx2x_phy *phy) in bnx2x_kr2_recovery() argument
13716 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); in bnx2x_kr2_recovery()
13717 bnx2x_warpcore_restart_AN_KR(phy, params); in bnx2x_kr2_recovery()
13722 struct bnx2x_phy *phy) in bnx2x_check_kr2_wa() argument
13738 sigdet = bnx2x_warpcore_get_sigdet(phy, params); in bnx2x_check_kr2_wa()
13741 bnx2x_kr2_recovery(params, vars, phy); in bnx2x_check_kr2_wa()
13747 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_check_kr2_wa()
13748 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_check_kr2_wa()
13750 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_check_kr2_wa()
13752 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_check_kr2_wa()
13754 bnx2x_set_aer_mmd(params, phy); in bnx2x_check_kr2_wa()
13759 bnx2x_kr2_recovery(params, vars, phy); in bnx2x_check_kr2_wa()
13778 bnx2x_kr2_recovery(params, vars, phy); in bnx2x_check_kr2_wa()
13786 bnx2x_disable_kr2(params, vars, phy); in bnx2x_check_kr2_wa()
13788 bnx2x_warpcore_restart_AN_KR(phy, params); in bnx2x_check_kr2_wa()
13798 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { in bnx2x_period_func()
13799 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); in bnx2x_period_func()
13808 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; in bnx2x_period_func() local
13809 bnx2x_set_aer_mmd(params, phy); in bnx2x_period_func()
13810 if ((phy->supported & SUPPORTED_20000baseKR2_Full) && in bnx2x_period_func()
13811 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) in bnx2x_period_func()
13812 bnx2x_check_kr2_wa(params, vars, phy); in bnx2x_period_func()
13815 bnx2x_warpcore_config_runtime(phy, params, vars); in bnx2x_period_func()
13822 if (bnx2x_is_sfp_module_plugged(phy, params)) { in bnx2x_period_func()
13823 bnx2x_sfp_tx_fault_detection(phy, params, vars); in bnx2x_period_func()
13842 struct bnx2x_phy phy; in bnx2x_fan_failure_det_req() local
13846 port, &phy) in bnx2x_fan_failure_det_req()
13851 fan_failure_det_req |= (phy.flags & in bnx2x_fan_failure_det_req()
13870 if (params->phy[phy_index].hw_reset) { in bnx2x_hw_reset_phy()
13871 params->phy[phy_index].hw_reset( in bnx2x_hw_reset_phy()
13872 ¶ms->phy[phy_index], in bnx2x_hw_reset_phy()
13874 params->phy[phy_index] = phy_null; in bnx2x_hw_reset_phy()
13894 struct bnx2x_phy phy; in bnx2x_init_mod_abs_int() local
13898 shmem2_base, port, &phy) in bnx2x_init_mod_abs_int()
13903 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { in bnx2x_init_mod_abs_int()