1461 				   params->phy[phy_index].mdio_ctrl);  in bnx2x_set_mdio_emac_per_phy()
2606 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_write()
2607 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in bnx2x_cl22_write()
2614 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl22_write()
2619 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_write()
2629 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in bnx2x_cl22_write()
2642 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_read()
2643 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in bnx2x_cl22_read()
2650 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl22_read()
2655 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_read()
2668 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in bnx2x_cl22_read()
2685 		bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);  in bnx2x_cl45_read()
2689 		bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_read()
2695 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl45_read()
2700 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_read()
2716 		REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl45_read()
2721 			val = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_read()
2745 		bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_read()
2760 		bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);  in bnx2x_cl45_write()
2764 		bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_write()
2771 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl45_write()
2776 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_write()
2791 		REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl45_write()
2796 			tmp = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_write()
2818 		bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_write()
8312 	fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);  in bnx2x_verify_sfp_module()
11506 	.mdio_ctrl	= 0,
11532 	.mdio_ctrl	= 0,
11567 	.mdio_ctrl	= 0,
11602 	.mdio_ctrl	= 0,
11642 	.mdio_ctrl	= 0,
11671 	.mdio_ctrl	= 0,
11702 	.mdio_ctrl	= 0,
11730 	.mdio_ctrl	= 0,
11761 	.mdio_ctrl	= 0,
11793 	.mdio_ctrl	= 0,
11823 	.mdio_ctrl	= 0,
11860 	.mdio_ctrl	= 0,
11897 	.mdio_ctrl	= 0,
11931 	.mdio_ctrl	= 0,
11965 	.mdio_ctrl	= 0,
11998 	.mdio_ctrl	= 0,
12211 	phy->mdio_ctrl = bnx2x_get_emac_base(bp,  in bnx2x_populate_int_phy()
12220 		   port, phy->addr, phy->mdio_ctrl);  in bnx2x_populate_int_phy()
12334 	phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);  in bnx2x_populate_ext_phy()
12350 		   phy->addr, phy->mdio_ctrl);  in bnx2x_populate_ext_phy()